36 .pll_div_m = {2, 1, 1},
37 .pll_div_n = {2, 1, 1},
60 .p_div = {1, 120, 30, 60, 1, 1},
CDCE906 PLL driver function declarations.
@ CDCE906_S1_CFG_Yx_FIXED_OUTPUT_CTRL
Definition cdce906.h:62
@ CDCE906_PLL_FVCO_80_200MHZ
Definition cdce906.h:50
@ CDCE906_PLL_VCO_MUX_PLL
Definition cdce906.h:45
@ CDCE906_Yx_Px_SEL_P5
Definition cdce906.h:97
@ CDCE906_Yx_Px_SEL_P1
Definition cdce906.h:93
@ CDCE906_Yx_Px_SEL_P3
Definition cdce906.h:95
@ CDCE906_Yx_Px_SEL_P2
Definition cdce906.h:94
@ CDCE906_Yx_Px_SEL_P4
Definition cdce906.h:96
@ CDCE906_Yx_Px_SEL_P0
Definition cdce906.h:92
@ CDCE906_CLK_SRC_CLKIN_DIFF
Definition cdce906.h:40
@ CDCE906_Yx_SLEW_CFG_NOMINAL_1NS
Definition cdce906.h:86
@ CDCE906_SSC_MOD_AMOUNT_OFF
Definition cdce906.h:102
@ CDCE906_S0_CFG_POWER_DOWN_CTRL
Definition cdce906.h:55
@ CDCE906_SSC_MOD_FREQ_3286
Definition cdce906.h:122
@ CDCE906_Yx_OUT_CFG_DIS_HIGH
Definition cdce906.h:81
@ CDCE906_Yx_OUT_CFG_EN
Definition cdce906.h:78
@ CDCE906_Yx_OUT_CFG_DIS_LOW
Definition cdce906.h:80
@ CDCE906_Px_PLL_SEL_PLL1
Definition cdce906.h:70
@ CDCE906_Px_PLL_SEL_BYPASS
Definition cdce906.h:69
enum cdce906_clk_src clksrc
Definition cdce906.h:132