Core Register type definitions. More...
Topics | |
| Nested Vectored Interrupt Controller (NVIC) | |
| Type definitions for the NVIC Registers. | |
Data Structures | |
| union | APSR_Type |
| Union type to access the Application Program Status Register (APSR). More... | |
| union | IPSR_Type |
| Union type to access the Interrupt Program Status Register (IPSR). More... | |
| union | xPSR_Type |
| Union type to access the Special-Purpose Program Status Registers (xPSR). More... | |
| union | CONTROL_Type |
| Union type to access the Control Registers (CONTROL). More... | |
| #define | APSR_N_Pos 31U |
| #define | APSR_N_Msk (1UL << APSR_N_Pos) |
| #define | APSR_Z_Pos 30U |
| #define | APSR_Z_Msk (1UL << APSR_Z_Pos) |
| #define | APSR_C_Pos 29U |
| #define | APSR_C_Msk (1UL << APSR_C_Pos) |
| #define | APSR_V_Pos 28U |
| #define | APSR_V_Msk (1UL << APSR_V_Pos) |
| #define | APSR_Q_Pos 27U |
| #define | APSR_Q_Msk (1UL << APSR_Q_Pos) |
| #define | IPSR_ISR_Pos 0U |
| #define | IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
| #define | xPSR_N_Pos 31U |
| #define | xPSR_N_Msk (1UL << xPSR_N_Pos) |
| #define | xPSR_Z_Pos 30U |
| #define | xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
| #define | xPSR_C_Pos 29U |
| #define | xPSR_C_Msk (1UL << xPSR_C_Pos) |
| #define | xPSR_V_Pos 28U |
| #define | xPSR_V_Msk (1UL << xPSR_V_Pos) |
| #define | xPSR_Q_Pos 27U |
| #define | xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
| #define | xPSR_ICI_IT_2_Pos 25U |
| #define | xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
| #define | xPSR_T_Pos 24U |
| #define | xPSR_T_Msk (1UL << xPSR_T_Pos) |
| #define | xPSR_ICI_IT_1_Pos 10U |
| #define | xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
| #define | xPSR_ISR_Pos 0U |
| #define | xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
| #define | CONTROL_SPSEL_Pos 1U |
| #define | CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
| #define | CONTROL_nPRIV_Pos 0U |
| #define | CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
Detailed Description
Core Register type definitions.
Macro Definition Documentation
◆ APSR_C_Msk
| #define APSR_C_Msk (1UL << APSR_C_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: C Mask
◆ APSR_C_Pos
| #define APSR_C_Pos 29U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: C Position
◆ APSR_N_Msk
| #define APSR_N_Msk (1UL << APSR_N_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: N Mask
◆ APSR_N_Pos
| #define APSR_N_Pos 31U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: N Position
◆ APSR_Q_Msk
| #define APSR_Q_Msk (1UL << APSR_Q_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: Q Mask
◆ APSR_Q_Pos
| #define APSR_Q_Pos 27U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: Q Position
◆ APSR_V_Msk
| #define APSR_V_Msk (1UL << APSR_V_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: V Mask
◆ APSR_V_Pos
| #define APSR_V_Pos 28U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: V Position
◆ APSR_Z_Msk
| #define APSR_Z_Msk (1UL << APSR_Z_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: Z Mask
◆ APSR_Z_Pos
| #define APSR_Z_Pos 30U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
APSR: Z Position
◆ CONTROL_nPRIV_Msk
| #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
CONTROL: nPRIV Mask
◆ CONTROL_nPRIV_Pos
| #define CONTROL_nPRIV_Pos 0U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
CONTROL: nPRIV Position
◆ CONTROL_SPSEL_Msk
| #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
CONTROL: SPSEL Mask
◆ CONTROL_SPSEL_Pos
| #define CONTROL_SPSEL_Pos 1U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
CONTROL: SPSEL Position
◆ IPSR_ISR_Msk
| #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
IPSR: ISR Mask
◆ IPSR_ISR_Pos
| #define IPSR_ISR_Pos 0U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
IPSR: ISR Position
◆ xPSR_C_Msk
| #define xPSR_C_Msk (1UL << xPSR_C_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: C Mask
◆ xPSR_C_Pos
| #define xPSR_C_Pos 29U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: C Position
◆ xPSR_ICI_IT_1_Msk
| #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: ICI/IT part 1 Mask
◆ xPSR_ICI_IT_1_Pos
| #define xPSR_ICI_IT_1_Pos 10U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: ICI/IT part 1 Position
◆ xPSR_ICI_IT_2_Msk
| #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: ICI/IT part 2 Mask
◆ xPSR_ICI_IT_2_Pos
| #define xPSR_ICI_IT_2_Pos 25U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: ICI/IT part 2 Position
◆ xPSR_ISR_Msk
| #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: ISR Mask
◆ xPSR_ISR_Pos
| #define xPSR_ISR_Pos 0U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: ISR Position
◆ xPSR_N_Msk
| #define xPSR_N_Msk (1UL << xPSR_N_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: N Mask
◆ xPSR_N_Pos
| #define xPSR_N_Pos 31U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: N Position
◆ xPSR_Q_Msk
| #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: Q Mask
◆ xPSR_Q_Pos
| #define xPSR_Q_Pos 27U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: Q Position
◆ xPSR_T_Msk
| #define xPSR_T_Msk (1UL << xPSR_T_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: T Mask
◆ xPSR_T_Pos
| #define xPSR_T_Pos 24U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: T Position
◆ xPSR_V_Msk
| #define xPSR_V_Msk (1UL << xPSR_V_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: V Mask
◆ xPSR_V_Pos
| #define xPSR_V_Pos 28U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: V Position
◆ xPSR_Z_Msk
| #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: Z Mask
◆ xPSR_Z_Pos
| #define xPSR_Z_Pos 30U |
#include <port/ucontroller/nxp/lpc17xx/bootloader/inc/core_cm3.h>
xPSR: Z Position
