Collaboration diagram for Configuration_of_CMSIS:

Enumerations
enum	IRQn_Type { Reset_IRQn = -15 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WDT_IRQn = 0 , TIMER0_IRQn = 1 , TIMER1_IRQn = 2 , TIMER2_IRQn = 3 , TIMER3_IRQn = 4 , UART0_IRQn = 5 , UART1_IRQn = 6 , UART2_IRQn = 7 , UART3_IRQn = 8 , PWM1_IRQn = 9 , I2C0_IRQn = 10 , I2C1_IRQn = 11 , I2C2_IRQn = 12 , SPI_IRQn = 13 , SSP0_IRQn = 14 , SSP1_IRQn = 15 , PLL0_IRQn = 16 , RTC_IRQn = 17 , EINT0_IRQn = 18 , EINT1_IRQn = 19 , EINT2_IRQn = 20 , EINT3_IRQn = 21 , ADC_IRQn = 22 , BOD_IRQn = 23 , USB_IRQn = 24 , CAN_IRQn = 25 , DMA_IRQn = 26 , I2S_IRQn = 27 , ENET_IRQn = 28 , RIT_IRQn = 29 , MCPWM_IRQn = 30 , QEI_IRQn = 31 , PLL1_IRQn = 32 , USBActivity_IRQn = 33 , CANActivity_IRQn = 34 }

Detailed Description

Macro Definition Documentation

#define __CM3_REV 0x0000U

CM3 Core Revision

#define __FPU_PRESENT 0

FPU present

#define __MPU_PRESENT 1

MPU present

#define __NVIC_PRIO_BITS 5

Number of Bits used for Priority Levels

#define __Vendor_SysTickConfig 0

Set to 1 if different SysTick Config is used

Enumerator
Reset_IRQn	-15 Reset Vector, invoked on Power up and warm reset
NonMaskableInt_IRQn	-14 Non maskable Interrupt, cannot be stopped or preempted
HardFault_IRQn	-13 Hard Fault, all classes of Fault
MemoryManagement_IRQn	-12 Memory Management, MPU mismatch, including Access Violation and No Match
BusFault_IRQn	-11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault
UsageFault_IRQn	-10 Usage Fault, i.e. Undef Instruction, Illegal State Transition
SVCall_IRQn	-5 System Service Call via SVC instruction
DebugMonitor_IRQn	-4 Debug Monitor
PendSV_IRQn	-2 Pendable request for system service
SysTick_IRQn	-1 System Tick Timer
WDT_IRQn	0 WDT
TIMER0_IRQn	1 TIMER0
TIMER1_IRQn	2 TIMER1
TIMER2_IRQn	3 TIMER2
TIMER3_IRQn	4 TIMER3
UART0_IRQn	5 UART0
UART1_IRQn	6 UART1
UART2_IRQn	7 UART2
UART3_IRQn	8 UART3
PWM1_IRQn	9 PWM1
I2C0_IRQn	10 I2C0
I2C1_IRQn	11 I2C1
I2C2_IRQn	12 I2C2
SPI_IRQn	13 SPI
SSP0_IRQn	14 SSP0
SSP1_IRQn	15 SSP1
PLL0_IRQn	16 PLL0
RTC_IRQn	17 RTC
EINT0_IRQn	18 EINT0
EINT1_IRQn	19 EINT1
EINT2_IRQn	20 EINT2
EINT3_IRQn	21 EINT3
ADC_IRQn	22 ADC
BOD_IRQn	23 BOD
USB_IRQn	24 USB
CAN_IRQn	25 CAN
DMA_IRQn	26 DMA
I2S_IRQn	27 I2S
ENET_IRQn	28 ENET
RIT_IRQn	29 RIT
MCPWM_IRQn	30 MCPWM
QEI_IRQn	31 QEI
PLL1_IRQn	32 PLL1
USBActivity_IRQn	33 USBActivity
CANActivity_IRQn	34 CANActivity