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cmsis_armcc.h
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1/**************************************************************************/
7/*
8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#ifndef __CMSIS_ARMCC_H
26#define __CMSIS_ARMCC_H
27
28
29#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30 #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31#endif
32
33/* CMSIS compiler control architecture macros */
34#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
35 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36 #define __ARM_ARCH_6M__ 1
37#endif
38
39#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40 #define __ARM_ARCH_7M__ 1
41#endif
42
43#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44 #define __ARM_ARCH_7EM__ 1
45#endif
46
47 /* __ARM_ARCH_8M_BASE__ not applicable */
48 /* __ARM_ARCH_8M_MAIN__ not applicable */
49
50/* CMSIS compiler control DSP macros */
51#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
52 #define __ARM_FEATURE_DSP 1
53#endif
54
55/* CMSIS compiler specific defines */
56#ifndef __ASM
57 #define __ASM __asm
58#endif
59#ifndef __INLINE
60 #define __INLINE __inline
61#endif
62#ifndef __STATIC_INLINE
63 #define __STATIC_INLINE static __inline
64#endif
65#ifndef __STATIC_FORCEINLINE
66 #define __STATIC_FORCEINLINE static __forceinline
67#endif
68#ifndef __NO_RETURN
69 #define __NO_RETURN __declspec(noreturn)
70#endif
71#ifndef __USED
72 #define __USED __attribute__((used))
73#endif
74#ifndef __WEAK
75 #define __WEAK __attribute__((weak))
76#endif
77#ifndef __PACKED
78 #define __PACKED __attribute__((packed))
79#endif
80#ifndef __PACKED_STRUCT
81 #define __PACKED_STRUCT __packed struct
82#endif
83#ifndef __PACKED_UNION
84 #define __PACKED_UNION __packed union
85#endif
86#ifndef __UNALIGNED_UINT32 /* deprecated */
87 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
88#endif
89#ifndef __UNALIGNED_UINT16_WRITE
90 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
91#endif
92#ifndef __UNALIGNED_UINT16_READ
93 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
94#endif
95#ifndef __UNALIGNED_UINT32_WRITE
96 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
97#endif
98#ifndef __UNALIGNED_UINT32_READ
99 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
100#endif
101#ifndef __ALIGNED
102 #define __ALIGNED(x) __attribute__((aligned(x)))
103#endif
104#ifndef __RESTRICT
105 #define __RESTRICT __restrict
106#endif
107#ifndef __COMPILER_BARRIER
108 #define __COMPILER_BARRIER() __memory_changed()
109#endif
110
111/* ######################### Startup and Lowlevel Init ######################## */
112
113#ifndef __PROGRAM_START
114#define __PROGRAM_START __main
115#endif
116
117#ifndef __INITIAL_SP
118#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
119#endif
120
121#ifndef __STACK_LIMIT
122#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
123#endif
124
125#ifndef __VECTOR_TABLE
126#define __VECTOR_TABLE __Vectors
127#endif
128
129#ifndef __VECTOR_TABLE_ATTRIBUTE
130#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
131#endif
132
133/* ########################### Core Function Access ########################### */
144/* intrinsic void __enable_irq(); */
145
146
152/* intrinsic void __disable_irq(); */
153
159__STATIC_INLINE uint32_t __get_CONTROL(void)
160{
161 register uint32_t __regControl __ASM("control");
162 return(__regControl);
163}
164
165
171__STATIC_INLINE void __set_CONTROL(uint32_t control)
172{
173 register uint32_t __regControl __ASM("control");
174 __regControl = control;
175}
176
177
183__STATIC_INLINE uint32_t __get_IPSR(void)
184{
185 register uint32_t __regIPSR __ASM("ipsr");
186 return(__regIPSR);
187}
188
189
195__STATIC_INLINE uint32_t __get_APSR(void)
196{
197 register uint32_t __regAPSR __ASM("apsr");
198 return(__regAPSR);
199}
200
201
207__STATIC_INLINE uint32_t __get_xPSR(void)
208{
209 register uint32_t __regXPSR __ASM("xpsr");
210 return(__regXPSR);
211}
212
213
219__STATIC_INLINE uint32_t __get_PSP(void)
220{
221 register uint32_t __regProcessStackPointer __ASM("psp");
222 return(__regProcessStackPointer);
223}
224
225
231__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
232{
233 register uint32_t __regProcessStackPointer __ASM("psp");
234 __regProcessStackPointer = topOfProcStack;
235}
236
237
243__STATIC_INLINE uint32_t __get_MSP(void)
244{
245 register uint32_t __regMainStackPointer __ASM("msp");
246 return(__regMainStackPointer);
247}
248
249
255__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
256{
257 register uint32_t __regMainStackPointer __ASM("msp");
258 __regMainStackPointer = topOfMainStack;
259}
260
261
267__STATIC_INLINE uint32_t __get_PRIMASK(void)
268{
269 register uint32_t __regPriMask __ASM("primask");
270 return(__regPriMask);
271}
272
273
279__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
280{
281 register uint32_t __regPriMask __ASM("primask");
282 __regPriMask = (priMask);
283}
284
285
286#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
287 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
288
294#define __enable_fault_irq __enable_fiq
295
296
302#define __disable_fault_irq __disable_fiq
303
304
310__STATIC_INLINE uint32_t __get_BASEPRI(void)
311{
312 register uint32_t __regBasePri __ASM("basepri");
313 return(__regBasePri);
314}
315
316
322__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
323{
324 register uint32_t __regBasePri __ASM("basepri");
325 __regBasePri = (basePri & 0xFFU);
326}
327
328
335__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
336{
337 register uint32_t __regBasePriMax __ASM("basepri_max");
338 __regBasePriMax = (basePri & 0xFFU);
339}
340
341
347__STATIC_INLINE uint32_t __get_FAULTMASK(void)
348{
349 register uint32_t __regFaultMask __ASM("faultmask");
350 return(__regFaultMask);
351}
352
353
359__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
360{
361 register uint32_t __regFaultMask __ASM("faultmask");
362 __regFaultMask = (faultMask & (uint32_t)1U);
363}
364
365#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
366 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
367
368
374__STATIC_INLINE uint32_t __get_FPSCR(void)
375{
376#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
377 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
378 register uint32_t __regfpscr __ASM("fpscr");
379 return(__regfpscr);
380#else
381 return(0U);
382#endif
383}
384
385
391__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
392{
393#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
394 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
395 register uint32_t __regfpscr __ASM("fpscr");
396 __regfpscr = (fpscr);
397#else
398 (void)fpscr;
399#endif
400}
401
402
406/* ########################## Core Instruction Access ######################### */
416#define __NOP __nop
417
418
423#define __WFI __wfi
424
425
431#define __WFE __wfe
432
433
438#define __SEV __sev
439
440
447#define __ISB() __isb(0xF)
448
454#define __DSB() __dsb(0xF)
455
461#define __DMB() __dmb(0xF)
462
463
470#define __REV __rev
471
472
479#ifndef __NO_EMBEDDED_ASM
480__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
481{
482 rev16 r0, r0
483 bx lr
484}
485#endif
486
487
494#ifndef __NO_EMBEDDED_ASM
495__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
496{
497 revsh r0, r0
498 bx lr
499}
500#endif
501
502
510#define __ROR __ror
511
512
520#define __BKPT(value) __breakpoint(value)
521
522
529#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
530 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
531 #define __RBIT __rbit
532#else
533__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
534{
535 uint32_t result;
536 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
537
538 result = value; /* r will be reversed bits of v; first get LSB of v */
539 for (value >>= 1U; value != 0U; value >>= 1U)
540 {
541 result <<= 1U;
542 result |= value & 1U;
543 s--;
544 }
545 result <<= s; /* shift when v's highest bits are zero */
546 return result;
547}
548#endif
549
550
557#define __CLZ __clz
558
559
560#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
561 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
562
569#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
570 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
571#else
572 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
573#endif
574
575
582#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
583 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
584#else
585 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
586#endif
587
588
595#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
596 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
597#else
598 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
599#endif
600
601
610#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
611 #define __STREXB(value, ptr) __strex(value, ptr)
612#else
613 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
614#endif
615
616
625#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
626 #define __STREXH(value, ptr) __strex(value, ptr)
627#else
628 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
629#endif
630
631
640#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
641 #define __STREXW(value, ptr) __strex(value, ptr)
642#else
643 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
644#endif
645
646
651#define __CLREX __clrex
652
653
661#define __SSAT __ssat
662
663
671#define __USAT __usat
672
673
681#ifndef __NO_EMBEDDED_ASM
682__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
683{
684 rrx r0, r0
685 bx lr
686}
687#endif
688
689
696#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
697
698
705#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
706
707
714#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
715
716
723#define __STRBT(value, ptr) __strt(value, ptr)
724
725
732#define __STRHT(value, ptr) __strt(value, ptr)
733
734
741#define __STRT(value, ptr) __strt(value, ptr)
742
743#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
744 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
745
753__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
754{
755 if ((sat >= 1U) && (sat <= 32U))
756 {
757 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
758 const int32_t min = -1 - max ;
759 if (val > max)
760 {
761 return max;
762 }
763 else if (val < min)
764 {
765 return min;
766 }
767 }
768 return val;
769}
770
778__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
779{
780 if (sat <= 31U)
781 {
782 const uint32_t max = ((1U << sat) - 1U);
783 if (val > (int32_t)max)
784 {
785 return max;
786 }
787 else if (val < 0)
788 {
789 return 0U;
790 }
791 }
792 return (uint32_t)val;
793}
794
795#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
796 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
797 /* end of group CMSIS_Core_InstructionInterface */
799
800
801/* ################### Compiler specific Intrinsics ########################### */
807#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
808
809#define __SADD8 __sadd8
810#define __QADD8 __qadd8
811#define __SHADD8 __shadd8
812#define __UADD8 __uadd8
813#define __UQADD8 __uqadd8
814#define __UHADD8 __uhadd8
815#define __SSUB8 __ssub8
816#define __QSUB8 __qsub8
817#define __SHSUB8 __shsub8
818#define __USUB8 __usub8
819#define __UQSUB8 __uqsub8
820#define __UHSUB8 __uhsub8
821#define __SADD16 __sadd16
822#define __QADD16 __qadd16
823#define __SHADD16 __shadd16
824#define __UADD16 __uadd16
825#define __UQADD16 __uqadd16
826#define __UHADD16 __uhadd16
827#define __SSUB16 __ssub16
828#define __QSUB16 __qsub16
829#define __SHSUB16 __shsub16
830#define __USUB16 __usub16
831#define __UQSUB16 __uqsub16
832#define __UHSUB16 __uhsub16
833#define __SASX __sasx
834#define __QASX __qasx
835#define __SHASX __shasx
836#define __UASX __uasx
837#define __UQASX __uqasx
838#define __UHASX __uhasx
839#define __SSAX __ssax
840#define __QSAX __qsax
841#define __SHSAX __shsax
842#define __USAX __usax
843#define __UQSAX __uqsax
844#define __UHSAX __uhsax
845#define __USAD8 __usad8
846#define __USADA8 __usada8
847#define __SSAT16 __ssat16
848#define __USAT16 __usat16
849#define __UXTB16 __uxtb16
850#define __UXTAB16 __uxtab16
851#define __SXTB16 __sxtb16
852#define __SXTAB16 __sxtab16
853#define __SMUAD __smuad
854#define __SMUADX __smuadx
855#define __SMLAD __smlad
856#define __SMLADX __smladx
857#define __SMLALD __smlald
858#define __SMLALDX __smlaldx
859#define __SMUSD __smusd
860#define __SMUSDX __smusdx
861#define __SMLSD __smlsd
862#define __SMLSDX __smlsdx
863#define __SMLSLD __smlsld
864#define __SMLSLDX __smlsldx
865#define __SEL __sel
866#define __QADD __qadd
867#define __QSUB __qsub
868
869#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
870 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
871
872#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
873 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
874
875#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
876 ((int64_t)(ARG3) << 32U) ) >> 32U))
877
878#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
879
880#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
884#endif /* __CMSIS_ARMCC_H */
__ASM
#define __ASM
Definition cmsis_armcc.h:57
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:63
__SSAT
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
Signed Saturate.
Definition cmsis_armclang.h:1163
__USAT
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
Unsigned Saturate.
Definition cmsis_armclang.h:1188
sat
uint32_t sat
Definition cmsis_armcc.h:754
__RBIT
#define __RBIT
Reverse bit order of value.
Definition cmsis_armclang.h:929
__REV16
#define __REV16(value)
Reverse byte order (16 bit)
Definition cmsis_armclang.h:883
__REVSH
#define __REVSH(value)
Reverse byte order (16 bit)
Definition cmsis_armclang.h:892
__attribute__
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
Reverse byte order (16 bit)
Definition cmsis_armcc.h:480
__set_CONTROL
__STATIC_INLINE void __set_CONTROL(uint32_t control)
Set Control Register.
Definition cmsis_armcc.h:171
__set_MSP
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Set Main Stack Pointer.
Definition cmsis_armcc.h:255
__set_PSP
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Set Process Stack Pointer.
Definition cmsis_armcc.h:231
__set_FPSCR
#define __set_FPSCR(x)
Set FPSCR.
Definition cmsis_armclang.h:790
__get_PRIMASK
__STATIC_INLINE uint32_t __get_PRIMASK(void)
Get Priority Mask.
Definition cmsis_armcc.h:267
__get_MSP
__STATIC_INLINE uint32_t __get_MSP(void)
Get Main Stack Pointer.
Definition cmsis_armcc.h:243
__get_FPSCR
__STATIC_INLINE uint32_t __get_FPSCR(void)
Get FPSCR.
Definition cmsis_armcc.h:374
__get_CONTROL
__STATIC_INLINE uint32_t __get_CONTROL(void)
Enable IRQ Interrupts.
Definition cmsis_armcc.h:159
__get_PSP
__STATIC_INLINE uint32_t __get_PSP(void)
Get Process Stack Pointer.
Definition cmsis_armcc.h:219
__get_xPSR
__STATIC_INLINE uint32_t __get_xPSR(void)
Get xPSR Register.
Definition cmsis_armcc.h:207
__get_APSR
__STATIC_INLINE uint32_t __get_APSR(void)
Get APSR Register.
Definition cmsis_armcc.h:195
__get_IPSR
__STATIC_INLINE uint32_t __get_IPSR(void)
Get IPSR Register.
Definition cmsis_armcc.h:183
__set_PRIMASK
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Set Priority Mask.
Definition cmsis_armcc.h:279