openMMC
Open Source Modular MMC for AMCs
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adn4604_usercfg.h
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1/*
2 * openMMC -- Open Source modular IPM Controller firmware
3 *
4 * Copyright (C) 2015 Henrique Silva <henrique.silva@lnls.br>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 * @license GPL-3.0+ <http://spdx.org/licenses/GPL-3.0+>
20 */
21
22#ifdef ADN4604_USERCFG_H_
23#error "User configuration for ADN4604 Clock switch already defined by other board port, check the build chain!"
24#else
25#define ADN4604_USERCFG_H_
26
27/* User configuration defines for ADN4604 Clock switch output config */
28#define ADN4604_CFG_OUT_0 0 /* TCLKD_OUT */
29#define ADN4604_CFG_OUT_1 0 /* TCLKC_OUT */
30#define ADN4604_CFG_OUT_2 0 /* TCLKA_OUT */
31#define ADN4604_CFG_OUT_3 0 /* TCLKB_OUT */
32#define ADN4604_CFG_OUT_4 13 /* FPGA_CCLK */
33#define ADN4604_CFG_OUT_5 8 /* FP2_CLK2 */
34#define ADN4604_CFG_OUT_6 5 /* LINK01_CLK */
35#define ADN4604_CFG_OUT_7 15 /* FP2_CLK1 */
36#define ADN4604_CFG_OUT_8 8 /* PCIE_CLK1 */
37#define ADN4604_CFG_OUT_9 5 /* LINK23_CLK */
38#define ADN4604_CFG_OUT_10 5 /* FIN1_CLK3 */
39#define ADN4604_CFG_OUT_11 5 /* FIN1_CLK2 */
40#define ADN4604_CFG_OUT_12 14 /* RTM_SYNC_CLK */
41#define ADN4604_CFG_OUT_13 5 /* OP15C (Aux U-Fl connector) */
42#define ADN4604_CFG_OUT_14 5 /* FIN2_CLK2 */
43#define ADN4604_CFG_OUT_15 5 /* FIN2_CLK3 */
44
45/* Output enable flags */
46#define ADN4604_EN_OUT_0 0 /* TCLKD_OUT */
47#define ADN4604_EN_OUT_1 0 /* TCLKC_OUT */
48#define ADN4604_EN_OUT_2 0 /* TCLKA_OUT */
49#define ADN4604_EN_OUT_3 0 /* TCLKB_OUT */
50#define ADN4604_EN_OUT_4 1 /* FPGA_CCLK */
51#define ADN4604_EN_OUT_5 0 /* FP2_CLK2 */
52#define ADN4604_EN_OUT_6 1 /* LINK01_CLK */
53#define ADN4604_EN_OUT_7 1 /* FP2_CLK1 */
54#define ADN4604_EN_OUT_8 1 /* PCIE_CLK1 */
55#define ADN4604_EN_OUT_9 0 /* LINK23_CLK */
56#define ADN4604_EN_OUT_10 1 /* FIN1_CLK3 */
57#define ADN4604_EN_OUT_11 1 /* FIN1_CLK2 */
58#define ADN4604_EN_OUT_12 0 /* RTM_SYNC_CLK */
59#define ADN4604_EN_OUT_13 1 /* OP15C (Aux U-Fl connector) */
60#define ADN4604_EN_OUT_14 1 /* FIN2_CLK2 */
61#define ADN4604_EN_OUT_15 1 /* FIN2_CLK3 */
62
63#endif