General purpose DMA controller (GPDMA) More...

#include <LPC176x5x.h>

Data Fields
__IM uint32_t	INTSTAT

__IM uint32_t	INTTCSTAT

__OM uint32_t	INTTCCLEAR

__IM uint32_t	INTERRSTAT

__OM uint32_t	INTERRCLR

__IM uint32_t	RAWINTTCSTAT

__IM uint32_t	RAWINTERRSTAT

__IM uint32_t	ENBLDCHNS

__IOM uint32_t	SOFTBREQ

__IOM uint32_t	SOFTSREQ

__IOM uint32_t	SOFTLBREQ

__IOM uint32_t	SOFTLSREQ

__IOM uint32_t	CONFIG

__IOM uint32_t	SYNC

__IM uint32_t	RESERVED [50]

__IOM uint32_t	SRCADDR0

__IOM uint32_t	DESTADDR0

__IOM uint32_t	LLI0

__IOM uint32_t	CONTROL0

__IOM uint32_t	CONFIG0

__IM uint32_t	RESERVED1 [3]

__IOM uint32_t	SRCADDR1

__IOM uint32_t	DESTADDR1

__IOM uint32_t	LLI1

__IOM uint32_t	CONTROL1

__IOM uint32_t	CONFIG1

__IM uint32_t	RESERVED2 [3]

__IOM uint32_t	SRCADDR2

__IOM uint32_t	DESTADDR2

__IOM uint32_t	LLI2

__IOM uint32_t	CONTROL2

__IOM uint32_t	CONFIG2

__IM uint32_t	RESERVED3 [3]

__IOM uint32_t	SRCADDR3

__IOM uint32_t	DESTADDR3

__IOM uint32_t	LLI3

__IOM uint32_t	CONTROL3

__IOM uint32_t	CONFIG3

__IM uint32_t	RESERVED4 [3]

__IOM uint32_t	SRCADDR4

__IOM uint32_t	DESTADDR4

__IOM uint32_t	LLI4

__IOM uint32_t	CONTROL4

__IOM uint32_t	CONFIG4

__IM uint32_t	RESERVED5 [3]

__IOM uint32_t	SRCADDR5

__IOM uint32_t	DESTADDR5

__IOM uint32_t	LLI5

__IOM uint32_t	CONTROL5

__IOM uint32_t	CONFIG5

__IM uint32_t	RESERVED6 [3]

__IOM uint32_t	SRCADDR6

__IOM uint32_t	DESTADDR6

__IOM uint32_t	LLI6

__IOM uint32_t	CONTROL6

__IOM uint32_t	CONFIG6

__IM uint32_t	RESERVED7 [3]

__IOM uint32_t	SRCADDR7

__IOM uint32_t	DESTADDR7

__IOM uint32_t	LLI7

__IOM uint32_t	CONTROL7

__IOM uint32_t	CONFIG7

Detailed Description

General purpose DMA controller (GPDMA)

Field Documentation

◆ CONFIG

__IOM uint32_t LPC_GPDMA_Type::CONFIG

(@ 0x00000030) DMA Configuration Register

◆ CONFIG0

__IOM uint32_t LPC_GPDMA_Type::CONFIG0

(@ 0x00000110) DMA Channel 0 Configuration Register[1]

◆ CONFIG1

__IOM uint32_t LPC_GPDMA_Type::CONFIG1

(@ 0x00000130) DMA Channel 0 Configuration Register[1]

◆ CONFIG2

__IOM uint32_t LPC_GPDMA_Type::CONFIG2

(@ 0x00000150) DMA Channel 0 Configuration Register[1]

◆ CONFIG3

__IOM uint32_t LPC_GPDMA_Type::CONFIG3

(@ 0x00000170) DMA Channel 0 Configuration Register[1]

◆ CONFIG4

__IOM uint32_t LPC_GPDMA_Type::CONFIG4

(@ 0x00000190) DMA Channel 0 Configuration Register[1]

◆ CONFIG5

__IOM uint32_t LPC_GPDMA_Type::CONFIG5

(@ 0x000001B0) DMA Channel 0 Configuration Register[1]

◆ CONFIG6

__IOM uint32_t LPC_GPDMA_Type::CONFIG6

(@ 0x000001D0) DMA Channel 0 Configuration Register[1]

◆ CONFIG7

__IOM uint32_t LPC_GPDMA_Type::CONFIG7

(@ 0x000001F0) DMA Channel 0 Configuration Register[1]

◆ CONTROL0

__IOM uint32_t LPC_GPDMA_Type::CONTROL0

(@ 0x0000010C) DMA Channel 0 Control Register

◆ CONTROL1

__IOM uint32_t LPC_GPDMA_Type::CONTROL1

(@ 0x0000012C) DMA Channel 0 Control Register

◆ CONTROL2

__IOM uint32_t LPC_GPDMA_Type::CONTROL2

(@ 0x0000014C) DMA Channel 0 Control Register

◆ CONTROL3

__IOM uint32_t LPC_GPDMA_Type::CONTROL3

(@ 0x0000016C) DMA Channel 0 Control Register

◆ CONTROL4

__IOM uint32_t LPC_GPDMA_Type::CONTROL4

(@ 0x0000018C) DMA Channel 0 Control Register

◆ CONTROL5

__IOM uint32_t LPC_GPDMA_Type::CONTROL5

(@ 0x000001AC) DMA Channel 0 Control Register

◆ CONTROL6

__IOM uint32_t LPC_GPDMA_Type::CONTROL6

(@ 0x000001CC) DMA Channel 0 Control Register

◆ CONTROL7

__IOM uint32_t LPC_GPDMA_Type::CONTROL7

(@ 0x000001EC) DMA Channel 0 Control Register

◆ DESTADDR0

__IOM uint32_t LPC_GPDMA_Type::DESTADDR0

(@ 0x00000104) DMA Channel 0 Destination Address Register

◆ DESTADDR1

__IOM uint32_t LPC_GPDMA_Type::DESTADDR1

(@ 0x00000124) DMA Channel 0 Destination Address Register

◆ DESTADDR2

__IOM uint32_t LPC_GPDMA_Type::DESTADDR2

(@ 0x00000144) DMA Channel 0 Destination Address Register

◆ DESTADDR3

__IOM uint32_t LPC_GPDMA_Type::DESTADDR3

(@ 0x00000164) DMA Channel 0 Destination Address Register

◆ DESTADDR4

__IOM uint32_t LPC_GPDMA_Type::DESTADDR4

(@ 0x00000184) DMA Channel 0 Destination Address Register

◆ DESTADDR5

__IOM uint32_t LPC_GPDMA_Type::DESTADDR5

(@ 0x000001A4) DMA Channel 0 Destination Address Register

◆ DESTADDR6

__IOM uint32_t LPC_GPDMA_Type::DESTADDR6

(@ 0x000001C4) DMA Channel 0 Destination Address Register

◆ DESTADDR7

__IOM uint32_t LPC_GPDMA_Type::DESTADDR7

(@ 0x000001E4) DMA Channel 0 Destination Address Register

◆ ENBLDCHNS

__IM uint32_t LPC_GPDMA_Type::ENBLDCHNS

(@ 0x0000001C) DMA Enabled Channel Register

◆ INTERRCLR

__OM uint32_t LPC_GPDMA_Type::INTERRCLR

(@ 0x00000010) DMA Interrupt Error Clear Register

◆ INTERRSTAT

__IM uint32_t LPC_GPDMA_Type::INTERRSTAT

(@ 0x0000000C) DMA Interrupt Error Status Register

◆ INTSTAT

__IM uint32_t LPC_GPDMA_Type::INTSTAT

< (@ 0x50004000) GPDMA Structure
(@ 0x00000000) DMA Interrupt Status Register

◆ INTTCCLEAR

__OM uint32_t LPC_GPDMA_Type::INTTCCLEAR

(@ 0x00000008) DMA Interrupt Terminal Count Request Clear Register

◆ INTTCSTAT

__IM uint32_t LPC_GPDMA_Type::INTTCSTAT

(@ 0x00000004) DMA Interrupt Terminal Count Request Status Register

◆ LLI0

__IOM uint32_t LPC_GPDMA_Type::LLI0

(@ 0x00000108) DMA Channel 0 Linked List Item Register

◆ LLI1

__IOM uint32_t LPC_GPDMA_Type::LLI1

(@ 0x00000128) DMA Channel 0 Linked List Item Register

◆ LLI2

__IOM uint32_t LPC_GPDMA_Type::LLI2

(@ 0x00000148) DMA Channel 0 Linked List Item Register

◆ LLI3

__IOM uint32_t LPC_GPDMA_Type::LLI3

(@ 0x00000168) DMA Channel 0 Linked List Item Register

◆ LLI4

__IOM uint32_t LPC_GPDMA_Type::LLI4

(@ 0x00000188) DMA Channel 0 Linked List Item Register

◆ LLI5

__IOM uint32_t LPC_GPDMA_Type::LLI5

(@ 0x000001A8) DMA Channel 0 Linked List Item Register

◆ LLI6

__IOM uint32_t LPC_GPDMA_Type::LLI6

(@ 0x000001C8) DMA Channel 0 Linked List Item Register

◆ LLI7

__IOM uint32_t LPC_GPDMA_Type::LLI7

(@ 0x000001E8) DMA Channel 0 Linked List Item Register

◆ RAWINTERRSTAT

__IM uint32_t LPC_GPDMA_Type::RAWINTERRSTAT

(@ 0x00000018) DMA Raw Error Interrupt Status Register

◆ RAWINTTCSTAT

__IM uint32_t LPC_GPDMA_Type::RAWINTTCSTAT

(@ 0x00000014) DMA Raw Interrupt Terminal Count Status Register

◆ RESERVED

__IM uint32_t LPC_GPDMA_Type::RESERVED[50]

◆ RESERVED1

__IM uint32_t LPC_GPDMA_Type::RESERVED1[3]

◆ RESERVED2

__IM uint32_t LPC_GPDMA_Type::RESERVED2[3]

◆ RESERVED3

__IM uint32_t LPC_GPDMA_Type::RESERVED3[3]

◆ RESERVED4

__IM uint32_t LPC_GPDMA_Type::RESERVED4[3]

◆ RESERVED5

__IM uint32_t LPC_GPDMA_Type::RESERVED5[3]

◆ RESERVED6

__IM uint32_t LPC_GPDMA_Type::RESERVED6[3]

◆ RESERVED7

__IM uint32_t LPC_GPDMA_Type::RESERVED7[3]

◆ SOFTBREQ

__IOM uint32_t LPC_GPDMA_Type::SOFTBREQ

(@ 0x00000020) DMA Software Burst Request Register

◆ SOFTLBREQ

__IOM uint32_t LPC_GPDMA_Type::SOFTLBREQ

(@ 0x00000028) DMA Software Last Burst Request Register

◆ SOFTLSREQ

__IOM uint32_t LPC_GPDMA_Type::SOFTLSREQ

(@ 0x0000002C) DMA Software Last Single Request Register

◆ SOFTSREQ

__IOM uint32_t LPC_GPDMA_Type::SOFTSREQ

(@ 0x00000024) DMA Software Single Request Register

◆ SRCADDR0

__IOM uint32_t LPC_GPDMA_Type::SRCADDR0

(@ 0x00000100) DMA Channel 0 Source Address Register

◆ SRCADDR1

__IOM uint32_t LPC_GPDMA_Type::SRCADDR1

(@ 0x00000120) DMA Channel 0 Source Address Register

◆ SRCADDR2

__IOM uint32_t LPC_GPDMA_Type::SRCADDR2

(@ 0x00000140) DMA Channel 0 Source Address Register

◆ SRCADDR3

__IOM uint32_t LPC_GPDMA_Type::SRCADDR3

(@ 0x00000160) DMA Channel 0 Source Address Register

◆ SRCADDR4

__IOM uint32_t LPC_GPDMA_Type::SRCADDR4

(@ 0x00000180) DMA Channel 0 Source Address Register

◆ SRCADDR5

__IOM uint32_t LPC_GPDMA_Type::SRCADDR5

(@ 0x000001A0) DMA Channel 0 Source Address Register

◆ SRCADDR6

__IOM uint32_t LPC_GPDMA_Type::SRCADDR6

(@ 0x000001C0) DMA Channel 0 Source Address Register

◆ SRCADDR7

__IOM uint32_t LPC_GPDMA_Type::SRCADDR7

(@ 0x000001E0) DMA Channel 0 Source Address Register

◆ SYNC

__IOM uint32_t LPC_GPDMA_Type::SYNC

(@ 0x00000034) DMA Synchronization Register

The documentation for this struct was generated from the following file:

port/ucontroller/nxp/lpc17xx/bootloader/inc/LPC176x5x.h

Data Fields