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LPC176x5x.h
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1/*
2 * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * @file lpc17_headers//LPC176x5x.h
19 * @brief CMSIS HeaderFile
20 * @version 0.2
21 * @date 06. February 2020
22 * @note Generated by SVDConv V3.3.27 on Thursday, 06.02.2020 12:13:27
23 * from File 'LPC176x5x_v0.2.svd',
24 */
25
26
27
38#ifndef LPC176X5X_H
39#define LPC176X5X_H
40
41#ifdef __cplusplus
42extern "C" {
43#endif
44
45
52/* =========================================================================================================================== */
53/* ================ Interrupt Number Definition ================ */
54/* =========================================================================================================================== */
55
56typedef enum {
57/* ======================================= ARM Cortex-M3 Specific Interrupt Numbers ======================================== */
58 Reset_IRQn = -15,
59 NonMaskableInt_IRQn = -14,
60 HardFault_IRQn = -13,
61 MemoryManagement_IRQn = -12,
63 BusFault_IRQn = -11,
65 UsageFault_IRQn = -10,
66 SVCall_IRQn = -5,
67 DebugMonitor_IRQn = -4,
68 PendSV_IRQn = -2,
69 SysTick_IRQn = -1,
70/* ========================================= LPC176x5x Specific Interrupt Numbers ========================================== */
71 WDT_IRQn = 0,
72 TIMER0_IRQn = 1,
73 TIMER1_IRQn = 2,
74 TIMER2_IRQn = 3,
75 TIMER3_IRQn = 4,
76 UART0_IRQn = 5,
77 UART1_IRQn = 6,
78 UART2_IRQn = 7,
79 UART3_IRQn = 8,
80 PWM1_IRQn = 9,
81 I2C0_IRQn = 10,
82 I2C1_IRQn = 11,
83 I2C2_IRQn = 12,
84 SPI_IRQn = 13,
85 SSP0_IRQn = 14,
86 SSP1_IRQn = 15,
87 PLL0_IRQn = 16,
88 RTC_IRQn = 17,
89 EINT0_IRQn = 18,
90 EINT1_IRQn = 19,
91 EINT2_IRQn = 20,
92 EINT3_IRQn = 21,
93 ADC_IRQn = 22,
94 BOD_IRQn = 23,
95 USB_IRQn = 24,
96 CAN_IRQn = 25,
97 DMA_IRQn = 26,
98 I2S_IRQn = 27,
99 ENET_IRQn = 28,
100 RIT_IRQn = 29,
101 MCPWM_IRQn = 30,
102 QEI_IRQn = 31,
103 PLL1_IRQn = 32,
104 USBActivity_IRQn = 33,
105 CANActivity_IRQn = 34
106} IRQn_Type;
107
108
109
110/* =========================================================================================================================== */
111/* ================ Processor and Core Peripheral Section ================ */
112/* =========================================================================================================================== */
113
114/* =========================== Configuration of the ARM Cortex-M3 Processor and Core Peripherals =========================== */
115#define __CM3_REV 0x0000U
116#define __NVIC_PRIO_BITS 5
117#define __Vendor_SysTickConfig 0
118#define __MPU_PRESENT 1
119#define __FPU_PRESENT 0
122 /* End of group Configuration_of_CMSIS */
123
124#include "core_cm3.h"
125// #include "system_LPC176x5x.h" /*!< LPC176x5x System */
126
127#ifndef __IM
128 #define __IM __I
129#endif
130#ifndef __OM
131 #define __OM __O
132#endif
133#ifndef __IOM
134 #define __IOM __IO
135#endif
136
137
138/* ======================================== Start of section using anonymous unions ======================================== */
139#if defined (__CC_ARM)
140 #pragma push
141 #pragma anon_unions
142#elif defined (__ICCARM__)
143 #pragma language=extended
144#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
145 #pragma clang diagnostic push
146 #pragma clang diagnostic ignored "-Wc11-extensions"
147 #pragma clang diagnostic ignored "-Wreserved-id-macro"
148 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
149 #pragma clang diagnostic ignored "-Wnested-anon-types"
150#elif defined (__GNUC__)
151 /* anonymous unions are enabled by default */
152#elif defined (__TMS470__)
153 /* anonymous unions are enabled by default */
154#elif defined (__TASKING__)
155 #pragma warning 586
156#elif defined (__CSMC__)
157 /* anonymous unions are enabled by default */
158#else
159 #warning Not supported compiler type
160#endif
161
162
163/* =========================================================================================================================== */
164/* ================ Device Specific Peripheral Section ================ */
165/* =========================================================================================================================== */
166
167
174/* =========================================================================================================================== */
175/* ================ WDT ================ */
176/* =========================================================================================================================== */
177
178
183typedef struct {
184 __IOM uint32_t MOD;
187 __IOM uint32_t TC;
189 __OM uint32_t FEED;
193 __IM uint32_t TV;
196 __IOM uint32_t CLKSEL;
197} LPC_WDT_Type;
201/* =========================================================================================================================== */
202/* ================ TIMER0 ================ */
203/* =========================================================================================================================== */
204
205
210typedef struct {
211 __IOM uint32_t IR;
215 __IOM uint32_t TCR;
218 __IOM uint32_t TC;
221 __IOM uint32_t PR;
224 __IOM uint32_t PC;
230 __IOM uint32_t MCR;
233 __IOM uint32_t MR[4];
237 __IOM uint32_t CCR;
242 __IM uint32_t CR[2];
245 __IM uint32_t RESERVED[2];
246 __IOM uint32_t EMR;
248 __IM uint32_t RESERVED1[12];
249 __IOM uint32_t CTCR;
252} LPC_TIMER0_Type;
256/* =========================================================================================================================== */
257/* ================ TIMER1 ================ */
258/* =========================================================================================================================== */
259
260
265typedef struct {
266 __IOM uint32_t IR;
270 __IOM uint32_t TCR;
273 __IOM uint32_t TC;
276 __IOM uint32_t PR;
279 __IOM uint32_t PC;
285 __IOM uint32_t MCR;
288 __IOM uint32_t MR[4];
292 __IOM uint32_t CCR;
297 __IM uint32_t CR[2];
300 __IM uint32_t RESERVED[2];
301 __IOM uint32_t EMR;
303 __IM uint32_t RESERVED1[12];
304 __IOM uint32_t CTCR;
307} LPC_TIMER1_Type;
311/* =========================================================================================================================== */
312/* ================ UART0 ================ */
313/* =========================================================================================================================== */
314
315
320typedef struct {
322 union {
323 __IM uint32_t RBR;
325 __OM uint32_t THR;
328 __IOM uint32_t DLL;
332 };
333
334 union {
335 __IOM uint32_t DLM;
339 __IOM uint32_t IER;
342 };
343
344 union {
345 __IM uint32_t IIR;
347 __OM uint32_t FCR;
349 };
350 __IOM uint32_t LCR;
352 __IM uint32_t RESERVED;
353 __IM uint32_t LSR;
355 __IM uint32_t RESERVED1;
356 __IOM uint32_t SCR;
358 __IOM uint32_t ACR;
360 __IM uint32_t RESERVED2;
361 __IOM uint32_t FDR;
363 __IM uint32_t RESERVED3;
364 __IOM uint32_t TER;
366 __IM uint32_t RESERVED4[6];
367 __IOM uint32_t RS485CTRL;
370 __IOM uint32_t RS485ADRMATCH;
372 __IOM uint32_t RS485DLY;
373} LPC_UART0_Type;
377/* =========================================================================================================================== */
378/* ================ UART1 ================ */
379/* =========================================================================================================================== */
380
381
386typedef struct {
388 union {
389 __IM uint32_t RBR;
391 __OM uint32_t THR;
393 __IOM uint32_t DLL;
397 };
398
399 union {
400 __IOM uint32_t DLM;
404 __IOM uint32_t IER;
407 };
408
409 union {
410 __IM uint32_t IIR;
412 __OM uint32_t FCR;
414 };
415 __IOM uint32_t LCR;
417 __IOM uint32_t MCR;
419 __IM uint32_t LSR;
421 __IM uint32_t MSR;
423 __IOM uint32_t SCR;
425 __IOM uint32_t ACR;
427 __IM uint32_t RESERVED;
428 __IOM uint32_t FDR;
430 __IM uint32_t RESERVED1;
431 __IOM uint32_t TER;
433 __IM uint32_t RESERVED2[6];
434 __IOM uint32_t RS485CTRL;
437 __IOM uint32_t RS485ADRMATCH;
439 __IOM uint32_t RS485DLY;
440} LPC_UART1_Type;
444/* =========================================================================================================================== */
445/* ================ PWM1 ================ */
446/* =========================================================================================================================== */
447
448
453typedef struct {
454 __IOM uint32_t IR;
457 __IOM uint32_t TCR;
459 __IOM uint32_t TC;
462 __IOM uint32_t PR;
464 __IOM uint32_t PC;
466 __IOM uint32_t MCR;
469 __IOM uint32_t MR0;
472 __IOM uint32_t MR1;
475 __IOM uint32_t MR2;
478 __IOM uint32_t MR3;
481 __IOM uint32_t CCR;
486 __IOM uint32_t CR[2];
489 __IM uint32_t RESERVED[3];
490 __IOM uint32_t MR4;
493 __IOM uint32_t MR5;
496 __IOM uint32_t MR6;
499 __IOM uint32_t PCR;
502 __IOM uint32_t LER;
504 __IM uint32_t RESERVED1[7];
505 __IOM uint32_t CTCR;
508} LPC_PWM1_Type;
512/* =========================================================================================================================== */
513/* ================ I2C0 ================ */
514/* =========================================================================================================================== */
515
516
521typedef struct {
522 __IOM uint32_t CONSET;
527 __IM uint32_t STAT;
531 __IOM uint32_t DAT;
536 __IOM uint32_t ADR0;
542 __IOM uint32_t SCLH;
544 __IOM uint32_t SCLL;
549 __OM uint32_t CONCLR;
554 __IOM uint32_t MMCTRL;
555 __IOM uint32_t ADR1;
561 __IOM uint32_t ADR2;
567 __IOM uint32_t ADR3;
573 __IM uint32_t DATA_BUFFER;
578 __IOM uint32_t MASK[4];
579} LPC_I2C0_Type;
583/* =========================================================================================================================== */
584/* ================ SPI ================ */
585/* =========================================================================================================================== */
586
587
592typedef struct {
593 __IOM uint32_t CR;
595 __IM uint32_t SR;
597 __IOM uint32_t DR;
602 __IOM uint32_t CCR;
604 __IM uint32_t RESERVED[3];
605 __IOM uint32_t INT;
607} LPC_SPI_Type;
611/* =========================================================================================================================== */
612/* ================ RTC ================ */
613/* =========================================================================================================================== */
614
615
620typedef struct {
621 __IOM uint32_t ILR;
622 __IM uint32_t RESERVED;
623 __IOM uint32_t CCR;
624 __IOM uint32_t CIIR;
625 __IOM uint32_t AMR;
626 __IM uint32_t CTIME0;
627 __IM uint32_t CTIME1;
628 __IM uint32_t CTIME2;
629 __IOM uint32_t SEC;
630 __IOM uint32_t MIN;
631 __IOM uint32_t HRS;
632 __IOM uint32_t DOM;
633 __IOM uint32_t DOW;
634 __IOM uint32_t DOY;
635 __IOM uint32_t MONTH;
636 __IOM uint32_t YEAR;
637 __IOM uint32_t CALIBRATION;
638 __IOM uint32_t GPREG0;
639 __IOM uint32_t GPREG1;
640 __IOM uint32_t GPREG2;
641 __IOM uint32_t GPREG3;
642 __IOM uint32_t GPREG4;
643 __IOM uint32_t RTC_AUXEN;
644 __IOM uint32_t RTC_AUX;
645 __IOM uint32_t ASEC;
646 __IOM uint32_t AMIN;
647 __IOM uint32_t AHRS;
648 __IOM uint32_t ADOM;
649 __IOM uint32_t ADOW;
650 __IOM uint32_t ADOY;
651 __IOM uint32_t AMON;
652 __IOM uint32_t AYRS;
653} LPC_RTC_Type;
657/* =========================================================================================================================== */
658/* ================ GPIOINT ================ */
659/* =========================================================================================================================== */
660
661
666typedef struct {
667 __IM uint32_t STATUS;
668 __IM uint32_t STATR0;
670 __IM uint32_t STATF0;
672 __OM uint32_t CLR0;
673 __IOM uint32_t ENR0;
675 __IOM uint32_t ENF0;
677 __IM uint32_t RESERVED[3];
678 __IM uint32_t STATR2;
680 __IM uint32_t STATF2;
682 __OM uint32_t CLR2;
683 __IOM uint32_t ENR2;
685 __IOM uint32_t ENF2;
687} LPC_GPIOINT_Type;
691/* =========================================================================================================================== */
692/* ================ PINCONNECT ================ */
693/* =========================================================================================================================== */
694
695
700typedef struct {
701 __IOM uint32_t PINSEL0;
702 __IOM uint32_t PINSEL1;
703 __IOM uint32_t PINSEL2;
704 __IOM uint32_t PINSEL3;
705 __IOM uint32_t PINSEL4;
706 __IM uint32_t RESERVED[2];
707 __IOM uint32_t PINSEL7;
708 __IM uint32_t RESERVED1;
709 __IOM uint32_t PINSEL9;
710 __IOM uint32_t PINSEL10;
711 __IM uint32_t RESERVED2[5];
712 __IOM uint32_t PINMODE0;
713 __IOM uint32_t PINMODE1;
714 __IOM uint32_t PINMODE2;
715 __IOM uint32_t PINMODE3;
716 __IOM uint32_t PINMODE4;
717 __IM uint32_t RESERVED3[2];
718 __IOM uint32_t PINMODE7;
719 __IM uint32_t RESERVED4;
720 __IOM uint32_t PINMODE9;
721 __IOM uint32_t PINMODE_OD0;
722 __IOM uint32_t PINMODE_OD1;
723 __IOM uint32_t PINMODE_OD2;
724 __IOM uint32_t PINMODE_OD3;
725 __IOM uint32_t PINMODE_OD4;
726 __IOM uint32_t I2CPADCFG;
727} LPC_PINCONNECT_Type;
731/* =========================================================================================================================== */
732/* ================ SSP1 ================ */
733/* =========================================================================================================================== */
734
735
740typedef struct {
741 __IOM uint32_t CR0;
743 __IOM uint32_t CR1;
745 __IOM uint32_t DR;
747 __IM uint32_t SR;
748 __IOM uint32_t CPSR;
749 __IOM uint32_t IMSC;
750 __IM uint32_t RIS;
751 __IM uint32_t MIS;
752 __OM uint32_t ICR;
753 __IOM uint32_t DMACR;
754} LPC_SSP1_Type;
758/* =========================================================================================================================== */
759/* ================ ADC ================ */
760/* =========================================================================================================================== */
761
762
767typedef struct {
768 __IOM uint32_t CR;
771 __IOM uint32_t GDR;
774 __IM uint32_t RESERVED;
775 __IOM uint32_t INTEN;
780 __IM uint32_t DR[8];
783 __IM uint32_t STAT;
786 __IOM uint32_t TRM;
787} LPC_ADC_Type;
791/* =========================================================================================================================== */
792/* ================ CANAFRAM ================ */
793/* =========================================================================================================================== */
794
795
800typedef struct {
801 __IOM uint32_t MASK[512];
802} LPC_CANAFRAM_Type;
806/* =========================================================================================================================== */
807/* ================ CANAF ================ */
808/* =========================================================================================================================== */
809
810
815typedef struct {
816 __IOM uint32_t AFMR;
817 __IOM uint32_t SFF_SA;
818 __IOM uint32_t SFF_GRP_SA;
819 __IOM uint32_t EFF_SA;
820 __IOM uint32_t EFF_GRP_SA;
821 __IOM uint32_t ENDOFTABLE;
822 __IM uint32_t LUTERRAD;
823 __IM uint32_t LUTERR;
824 __IOM uint32_t FCANIE;
825 __IOM uint32_t FCANIC0;
826 __IOM uint32_t FCANIC1;
827} LPC_CANAF_Type;
831/* =========================================================================================================================== */
832/* ================ CCAN ================ */
833/* =========================================================================================================================== */
834
835
840typedef struct {
841 __IM uint32_t TXSR;
842 __IM uint32_t RXSR;
843 __IM uint32_t MSR;
844} LPC_CCAN_Type;
848/* =========================================================================================================================== */
849/* ================ CAN1 ================ */
850/* =========================================================================================================================== */
851
852
857typedef struct {
858 __IOM uint32_t MOD;
859 __OM uint32_t CMR;
861 __IM uint32_t GSR;
864 __IM uint32_t ICR;
866 __IOM uint32_t IER;
867 __IOM uint32_t BTR;
869 __IOM uint32_t EWL;
871 __IM uint32_t SR;
872 __IOM uint32_t RFS;
874 __IOM uint32_t RID;
876 __IOM uint32_t RDA;
878 __IOM uint32_t RDB;
880 __IOM uint32_t TFI1;
881 __IOM uint32_t TID1;
882 __IOM uint32_t TDA1;
883 __IOM uint32_t TDB1;
884 __IOM uint32_t TFI2;
885 __IOM uint32_t TID2;
886 __IOM uint32_t TDA2;
887 __IOM uint32_t TDB2;
888 __IOM uint32_t TFI3;
889 __IOM uint32_t TID3;
890 __IOM uint32_t TDA3;
891 __IOM uint32_t TDB3;
892} LPC_CAN1_Type;
896/* =========================================================================================================================== */
897/* ================ CAN2 ================ */
898/* =========================================================================================================================== */
899
900
905typedef struct {
906 __IOM uint32_t MOD;
907 __OM uint32_t CMR;
909 __IM uint32_t GSR;
912 __IM uint32_t ICR;
914 __IOM uint32_t IER;
915 __IOM uint32_t BTR;
917 __IOM uint32_t EWL;
919 __IM uint32_t SR;
920 __IOM uint32_t RFS;
922 __IOM uint32_t RID;
924 __IOM uint32_t RDA;
926 __IOM uint32_t RDB;
928 __IOM uint32_t TFI1;
929 __IOM uint32_t TID1;
930 __IOM uint32_t TDA1;
931 __IOM uint32_t TDB1;
932 __IOM uint32_t TFI2;
933 __IOM uint32_t TID2;
934 __IOM uint32_t TDA2;
935 __IOM uint32_t TDB2;
936 __IOM uint32_t TFI3;
937 __IOM uint32_t TID3;
938 __IOM uint32_t TDA3;
939 __IOM uint32_t TDB3;
940} LPC_CAN2_Type;
944/* =========================================================================================================================== */
945/* ================ SSP0 ================ */
946/* =========================================================================================================================== */
947
948
953typedef struct {
954 __IOM uint32_t CR0;
956 __IOM uint32_t CR1;
958 __IOM uint32_t DR;
960 __IM uint32_t SR;
961 __IOM uint32_t CPSR;
962 __IOM uint32_t IMSC;
963 __IM uint32_t RIS;
964 __IM uint32_t MIS;
965 __OM uint32_t ICR;
966 __IOM uint32_t DMACR;
967} LPC_SSP0_Type;
971/* =========================================================================================================================== */
972/* ================ DAC ================ */
973/* =========================================================================================================================== */
974
975
980typedef struct {
981 __IOM uint32_t CR;
984 __IOM uint32_t CTRL;
986 __IOM uint32_t CNTVAL;
989} LPC_DAC_Type;
993/* =========================================================================================================================== */
994/* ================ TIMER2 ================ */
995/* =========================================================================================================================== */
996
997
1002typedef struct {
1003 __IOM uint32_t IR;
1007 __IOM uint32_t TCR;
1010 __IOM uint32_t TC;
1013 __IOM uint32_t PR;
1016 __IOM uint32_t PC;
1022 __IOM uint32_t MCR;
1025 __IOM uint32_t MR[4];
1029 __IOM uint32_t CCR;
1034 __IM uint32_t CR[2];
1037 __IM uint32_t RESERVED[2];
1038 __IOM uint32_t EMR;
1040 __IM uint32_t RESERVED1[12];
1041 __IOM uint32_t CTCR;
1044} LPC_TIMER2_Type;
1048/* =========================================================================================================================== */
1049/* ================ TIMER3 ================ */
1050/* =========================================================================================================================== */
1051
1052
1057typedef struct {
1058 __IOM uint32_t IR;
1062 __IOM uint32_t TCR;
1065 __IOM uint32_t TC;
1068 __IOM uint32_t PR;
1071 __IOM uint32_t PC;
1077 __IOM uint32_t MCR;
1080 __IOM uint32_t MR[4];
1084 __IOM uint32_t CCR;
1089 __IM uint32_t CR[2];
1092 __IM uint32_t RESERVED[2];
1093 __IOM uint32_t EMR;
1095 __IM uint32_t RESERVED1[12];
1096 __IOM uint32_t CTCR;
1099} LPC_TIMER3_Type;
1103/* =========================================================================================================================== */
1104/* ================ UART2 ================ */
1105/* =========================================================================================================================== */
1106
1107
1112typedef struct {
1114 union {
1115 __IM uint32_t RBR;
1117 __OM uint32_t THR;
1120 __IOM uint32_t DLL;
1124 };
1125
1126 union {
1127 __IOM uint32_t DLM;
1131 __IOM uint32_t IER;
1134 };
1135
1136 union {
1137 __IM uint32_t IIR;
1139 __OM uint32_t FCR;
1141 };
1142 __IOM uint32_t LCR;
1144 __IM uint32_t RESERVED;
1145 __IM uint32_t LSR;
1147 __IM uint32_t RESERVED1;
1148 __IOM uint32_t SCR;
1150 __IOM uint32_t ACR;
1152 __IM uint32_t RESERVED2;
1153 __IOM uint32_t FDR;
1155 __IM uint32_t RESERVED3;
1156 __IOM uint32_t TER;
1158 __IM uint32_t RESERVED4[6];
1159 __IOM uint32_t RS485CTRL;
1162 __IOM uint32_t RS485ADRMATCH;
1164 __IOM uint32_t RS485DLY;
1165} LPC_UART2_Type;
1169/* =========================================================================================================================== */
1170/* ================ UART3 ================ */
1171/* =========================================================================================================================== */
1172
1173
1178typedef struct {
1180 union {
1181 __IM uint32_t RBR;
1183 __OM uint32_t THR;
1186 __IOM uint32_t DLL;
1190 };
1191
1192 union {
1193 __IOM uint32_t DLM;
1197 __IOM uint32_t IER;
1200 };
1201
1202 union {
1203 __IM uint32_t IIR;
1205 __OM uint32_t FCR;
1207 };
1208 __IOM uint32_t LCR;
1210 __IM uint32_t RESERVED;
1211 __IM uint32_t LSR;
1213 __IM uint32_t RESERVED1;
1214 __IOM uint32_t SCR;
1216 __IOM uint32_t ACR;
1218 __IM uint32_t RESERVED2;
1219 __IOM uint32_t FDR;
1221 __IM uint32_t RESERVED3;
1222 __IOM uint32_t TER;
1224 __IM uint32_t RESERVED4[6];
1225 __IOM uint32_t RS485CTRL;
1228 __IOM uint32_t RS485ADRMATCH;
1230 __IOM uint32_t RS485DLY;
1231} LPC_UART3_Type;
1235/* =========================================================================================================================== */
1236/* ================ I2S ================ */
1237/* =========================================================================================================================== */
1238
1239
1244typedef struct {
1245 __IOM uint32_t DAO;
1247 __IOM uint32_t DAI;
1249 __OM uint32_t TXFIFO;
1251 __IM uint32_t RXFIFO;
1253 __IM uint32_t STATE;
1255 __IOM uint32_t DMA1;
1257 __IOM uint32_t DMA2;
1259 __IOM uint32_t IRQ;
1262 __IOM uint32_t TXRATE;
1265 __IOM uint32_t RXRATE;
1268 __IOM uint32_t TXBITRATE;
1272 __IOM uint32_t RXBITRATE;
1276 __IOM uint32_t TXMODE;
1277 __IOM uint32_t RXMODE;
1278} LPC_I2S_Type;
1282/* =========================================================================================================================== */
1283/* ================ RITIMER ================ */
1284/* =========================================================================================================================== */
1285
1286
1291typedef struct {
1292 __IOM uint32_t COMPVAL;
1293 __IOM uint32_t MASK;
1297 __IOM uint32_t CTRL;
1298 __IOM uint32_t COUNTER;
1299} LPC_RITIMER_Type;
1303/* =========================================================================================================================== */
1304/* ================ MCPWM ================ */
1305/* =========================================================================================================================== */
1306
1307
1312typedef struct {
1313 __IM uint32_t CON;
1314 __OM uint32_t CON_SET;
1315 __OM uint32_t CON_CLR;
1316 __IM uint32_t CAPCON;
1317 __OM uint32_t CAPCON_SET;
1318 __OM uint32_t CAPCON_CLR;
1319 __IOM uint32_t TC[3];
1320 __IOM uint32_t LIM[3];
1321 __IOM uint32_t MAT[3];
1322 __IOM uint32_t DT;
1323 __IOM uint32_t CP;
1324 __IM uint32_t CAP[3];
1325 __IM uint32_t INTEN;
1326 __OM uint32_t INTEN_SET;
1327 __OM uint32_t INTEN_CLR;
1328 __IM uint32_t CNTCON;
1329 __OM uint32_t CNTCON_SET;
1330 __OM uint32_t CNTCON_CLR;
1331 __IM uint32_t INTF;
1332 __OM uint32_t INTF_SET;
1333 __OM uint32_t INTF_CLR;
1334 __OM uint32_t CAP_CLR;
1335} LPC_MCPWM_Type;
1339/* =========================================================================================================================== */
1340/* ================ QEI ================ */
1341/* =========================================================================================================================== */
1342
1343
1348typedef struct {
1349 __OM uint32_t CON;
1350 __IM uint32_t STAT;
1351 __IOM uint32_t CONF;
1352 __IM uint32_t POS;
1353 __IOM uint32_t MAXPOS;
1354 __IOM uint32_t CMPOS0;
1355 __IOM uint32_t CMPOS1;
1356 __IOM uint32_t CMPOS2;
1357 __IM uint32_t INXCNT;
1358 __IOM uint32_t INXCMP0;
1359 __IOM uint32_t LOAD;
1360 __IM uint32_t TIME;
1361 __IM uint32_t VEL;
1362 __IM uint32_t CAP;
1363 __IOM uint32_t VELCOMP;
1364 __IOM uint32_t FILTER;
1365 __IM uint32_t RESERVED[998];
1366 __OM uint32_t IEC;
1367 __OM uint32_t IES;
1368 __IM uint32_t INTSTAT;
1369 __IM uint32_t IE;
1370 __OM uint32_t CLR;
1371 __OM uint32_t SET;
1372} LPC_QEI_Type;
1376/* =========================================================================================================================== */
1377/* ================ SYSCON ================ */
1378/* =========================================================================================================================== */
1379
1380
1385typedef struct {
1386 __IOM uint32_t FLASHCFG;
1388 __IM uint32_t RESERVED[31];
1389 __IOM uint32_t PLL0CON;
1390 __IOM uint32_t PLL0CFG;
1391 __IM uint32_t PLL0STAT;
1392 __OM uint32_t PLL0FEED;
1393 __IM uint32_t RESERVED1[4];
1394 __IOM uint32_t PLL1CON;
1395 __IOM uint32_t PLL1CFG;
1396 __IM uint32_t PLL1STAT;
1397 __OM uint32_t PLL1FEED;
1398 __IM uint32_t RESERVED2[4];
1399 __IOM uint32_t PCON;
1400 __IOM uint32_t PCONP;
1401 __IM uint32_t RESERVED3[15];
1402 __IOM uint32_t CCLKCFG;
1403 __IOM uint32_t USBCLKCFG;
1404 __IOM uint32_t CLKSRCSEL;
1405 __IOM uint32_t CANSLEEPCLR;
1407 __IOM uint32_t CANWAKEFLAGS;
1408 __IM uint32_t RESERVED4[10];
1409 __IOM uint32_t EXTINT;
1410 __IM uint32_t RESERVED5;
1411 __IOM uint32_t EXTMODE;
1412 __IOM uint32_t EXTPOLAR;
1413 __IM uint32_t RESERVED6[12];
1414 __IOM uint32_t RSID;
1415 __IM uint32_t RESERVED7[7];
1416 __IOM uint32_t SCS;
1417 __IM uint32_t RESERVED8;
1418 __IOM uint32_t PCLKSEL0;
1419 __IOM uint32_t PCLKSEL1;
1420 __IM uint32_t RESERVED9[4];
1421 __IOM uint32_t USBINTST;
1422 __IOM uint32_t DMACREQSEL;
1424 __IOM uint32_t CLKOUTCFG;
1425} LPC_SYSCON_Type;
1429/* =========================================================================================================================== */
1430/* ================ EMAC ================ */
1431/* =========================================================================================================================== */
1432
1433
1438typedef struct {
1439 __IOM uint32_t MAC1;
1440 __IOM uint32_t MAC2;
1441 __IOM uint32_t IPGT;
1442 __IOM uint32_t IPGR;
1443 __IOM uint32_t CLRT;
1444 __IOM uint32_t MAXF;
1445 __IOM uint32_t SUPP;
1446 __IOM uint32_t TEST;
1447 __IOM uint32_t MCFG;
1448 __IOM uint32_t MCMD;
1449 __IOM uint32_t MADR;
1450 __OM uint32_t MWTD;
1451 __IM uint32_t MRDD;
1452 __IM uint32_t MIND;
1453 __IM uint32_t RESERVED[2];
1454 __IOM uint32_t SA0;
1455 __IOM uint32_t SA1;
1456 __IOM uint32_t SA2;
1457 __IM uint32_t RESERVED1[45];
1458 __IOM uint32_t COMMAND;
1459 __IM uint32_t STATUS;
1460 __IOM uint32_t RXDESCRIPTOR;
1461 __IOM uint32_t RXSTATUS;
1462 __IOM uint32_t RXDESCRIPTORNUMBER;
1463 __IM uint32_t RXPRODUCEINDEX;
1464 __IOM uint32_t RXCONSUMEINDEX;
1465 __IOM uint32_t TXDESCRIPTOR;
1466 __IOM uint32_t TXSTATUS;
1467 __IOM uint32_t TXDESCRIPTORNUMBER;
1468 __IOM uint32_t TXPRODUCEINDEX;
1469 __IM uint32_t TXCONSUMEINDEX;
1470 __IM uint32_t RESERVED2[10];
1471 __IM uint32_t TSV0;
1472 __IM uint32_t TSV1;
1473 __IM uint32_t RSV;
1474 __IM uint32_t RESERVED3[3];
1475 __IOM uint32_t FLOWCONTROLCOUNTER;
1476 __IM uint32_t FLOWCONTROLSTATUS;
1477 __IM uint32_t RESERVED4[34];
1478 __IOM uint32_t RXFILTERCTRL;
1479 __IM uint32_t RXFILTERWOLSTATUS;
1480 __OM uint32_t RXFILTERWOLCLEAR;
1481 __IM uint32_t RESERVED5;
1482 __IOM uint32_t HASHFILTERL;
1483 __IOM uint32_t HASHFILTERH;
1484 __IM uint32_t RESERVED6[882];
1485 __IM uint32_t INTSTATUS;
1486 __IOM uint32_t INTENABLE;
1487 __OM uint32_t INTCLEAR;
1488 __OM uint32_t INTSET;
1489 __IM uint32_t RESERVED7;
1490 __IOM uint32_t POWERDOWN;
1491} LPC_EMAC_Type;
1495/* =========================================================================================================================== */
1496/* ================ GPDMA ================ */
1497/* =========================================================================================================================== */
1498
1499
1504typedef struct {
1505 __IM uint32_t INTSTAT;
1506 __IM uint32_t INTTCSTAT;
1507 __OM uint32_t INTTCCLEAR;
1508 __IM uint32_t INTERRSTAT;
1509 __OM uint32_t INTERRCLR;
1510 __IM uint32_t RAWINTTCSTAT;
1511 __IM uint32_t RAWINTERRSTAT;
1512 __IM uint32_t ENBLDCHNS;
1513 __IOM uint32_t SOFTBREQ;
1514 __IOM uint32_t SOFTSREQ;
1515 __IOM uint32_t SOFTLBREQ;
1516 __IOM uint32_t SOFTLSREQ;
1517 __IOM uint32_t CONFIG;
1518 __IOM uint32_t SYNC;
1519 __IM uint32_t RESERVED[50];
1520 __IOM uint32_t SRCADDR0;
1521 __IOM uint32_t DESTADDR0;
1522 __IOM uint32_t LLI0;
1523 __IOM uint32_t CONTROL0;
1524 __IOM uint32_t CONFIG0;
1525 __IM uint32_t RESERVED1[3];
1526 __IOM uint32_t SRCADDR1;
1527 __IOM uint32_t DESTADDR1;
1528 __IOM uint32_t LLI1;
1529 __IOM uint32_t CONTROL1;
1530 __IOM uint32_t CONFIG1;
1531 __IM uint32_t RESERVED2[3];
1532 __IOM uint32_t SRCADDR2;
1533 __IOM uint32_t DESTADDR2;
1534 __IOM uint32_t LLI2;
1535 __IOM uint32_t CONTROL2;
1536 __IOM uint32_t CONFIG2;
1537 __IM uint32_t RESERVED3[3];
1538 __IOM uint32_t SRCADDR3;
1539 __IOM uint32_t DESTADDR3;
1540 __IOM uint32_t LLI3;
1541 __IOM uint32_t CONTROL3;
1542 __IOM uint32_t CONFIG3;
1543 __IM uint32_t RESERVED4[3];
1544 __IOM uint32_t SRCADDR4;
1545 __IOM uint32_t DESTADDR4;
1546 __IOM uint32_t LLI4;
1547 __IOM uint32_t CONTROL4;
1548 __IOM uint32_t CONFIG4;
1549 __IM uint32_t RESERVED5[3];
1550 __IOM uint32_t SRCADDR5;
1551 __IOM uint32_t DESTADDR5;
1552 __IOM uint32_t LLI5;
1553 __IOM uint32_t CONTROL5;
1554 __IOM uint32_t CONFIG5;
1555 __IM uint32_t RESERVED6[3];
1556 __IOM uint32_t SRCADDR6;
1557 __IOM uint32_t DESTADDR6;
1558 __IOM uint32_t LLI6;
1559 __IOM uint32_t CONTROL6;
1560 __IOM uint32_t CONFIG6;
1561 __IM uint32_t RESERVED7[3];
1562 __IOM uint32_t SRCADDR7;
1563 __IOM uint32_t DESTADDR7;
1564 __IOM uint32_t LLI7;
1565 __IOM uint32_t CONTROL7;
1566 __IOM uint32_t CONFIG7;
1567} LPC_GPDMA_Type;
1571/* =========================================================================================================================== */
1572/* ================ USB ================ */
1573/* =========================================================================================================================== */
1574
1575
1580typedef struct {
1581 __IM uint32_t RESERVED[55];
1582 __IM uint32_t RXPLEN;
1583 __IM uint32_t RESERVED1[8];
1584 __IM uint32_t INTST;
1585 __IOM uint32_t INTEN;
1586 __OM uint32_t INTSET;
1587 __OM uint32_t INTCLR;
1588 __IOM uint32_t STCTRL;
1589 __IOM uint32_t TMR;
1590 __IM uint32_t RESERVED2[58];
1591 __IM uint32_t DEVINTST;
1592 __IOM uint32_t DEVINTEN;
1593 __OM uint32_t DEVINTCLR;
1594 __OM uint32_t DEVINTSET;
1595 __OM uint32_t CMDCODE;
1596 __IM uint32_t CMDDATA;
1597 __IM uint32_t RXDATA;
1598 __OM uint32_t TXDATA;
1599 __IM uint32_t RESERVED3;
1600 __OM uint32_t TXPLEN;
1601 __IOM uint32_t CTRL;
1602 __OM uint32_t DEVINTPRI;
1603 __IM uint32_t EPINTST;
1604 __IOM uint32_t EPINTEN;
1605 __OM uint32_t EPINTCLR;
1606 __OM uint32_t EPINTSET;
1607 __OM uint32_t EPINTPRI;
1608 __IOM uint32_t REEP;
1609 __OM uint32_t EPIND;
1610 __IOM uint32_t MAXPSIZE;
1611 __IM uint32_t DMARST;
1612 __OM uint32_t DMARCLR;
1613 __OM uint32_t DMARSET;
1614 __IM uint32_t RESERVED4[9];
1615 __IOM uint32_t UDCAH;
1616 __IM uint32_t EPDMAST;
1617 __OM uint32_t EPDMAEN;
1618 __OM uint32_t EPDMADIS;
1619 __IM uint32_t DMAINTST;
1620 __IOM uint32_t DMAINTEN;
1621 __IM uint32_t RESERVED5[2];
1622 __IM uint32_t EOTINTST;
1623 __OM uint32_t EOTINTCLR;
1624 __OM uint32_t EOTINTSET;
1625 __IM uint32_t NDDRINTST;
1626 __OM uint32_t NDDRINTCLR;
1627 __OM uint32_t NDDRINTSET;
1628 __IM uint32_t SYSERRINTST;
1629 __OM uint32_t SYSERRINTCLR;
1630 __OM uint32_t SYSERRINTSET;
1631 __IM uint32_t RESERVED6[15];
1632
1633 union {
1634 __IM uint32_t I2C_RX;
1635 __OM uint32_t I2C_WO;
1636 };
1637 __IM uint32_t I2C_STS;
1638 __IOM uint32_t I2C_CTL;
1639 __IOM uint32_t I2C_CLKHI;
1640 __OM uint32_t I2C_CLKLO;
1641 __IM uint32_t RESERVED7[824];
1642
1643 union {
1644 __IOM uint32_t USBCLKCTRL;
1645 __IOM uint32_t OTGCLKCTRL;
1646 };
1647
1648 union {
1649 __IM uint32_t USBCLKST;
1650 __IM uint32_t OTGCLKST;
1651 };
1652} LPC_USB_Type;
1656/* =========================================================================================================================== */
1657/* ================ GPIO ================ */
1658/* =========================================================================================================================== */
1659
1660
1665typedef struct {
1666 __IOM uint32_t DIR0;
1667 __IM uint32_t RESERVED[3];
1668 __IOM uint32_t MASK0;
1669 __IOM uint32_t PIN0;
1670 __IOM uint32_t SET0;
1671 __OM uint32_t CLR0;
1672 __IOM uint32_t DIR1;
1673 __IM uint32_t RESERVED1[3];
1674 __IOM uint32_t MASK1;
1675 __IOM uint32_t PIN1;
1676 __IOM uint32_t SET1;
1677 __OM uint32_t CLR1;
1678 __IOM uint32_t DIR2;
1679 __IM uint32_t RESERVED2[3];
1680 __IOM uint32_t MASK2;
1681 __IOM uint32_t PIN2;
1682 __IOM uint32_t SET2;
1683 __OM uint32_t CLR2;
1684 __IOM uint32_t DIR3;
1685 __IM uint32_t RESERVED3[3];
1686 __IOM uint32_t MASK3;
1687 __IOM uint32_t PIN3;
1688 __IOM uint32_t SET3;
1689 __OM uint32_t CLR3;
1690 __IOM uint32_t DIR4;
1691 __IM uint32_t RESERVED4[3];
1692 __IOM uint32_t MASK4;
1693 __IOM uint32_t PIN4;
1694 __IOM uint32_t SET4;
1695 __OM uint32_t CLR4;
1696} LPC_GPIO_Type;
1699 /* End of group Device_Peripheral_peripherals */
1700
1701
1702/* =========================================================================================================================== */
1703/* ================ Device Specific Peripheral Address Map ================ */
1704/* =========================================================================================================================== */
1705
1706
1711#define LPC_WDT_BASE 0x40000000UL
1712#define LPC_TIMER0_BASE 0x40004000UL
1713#define LPC_TIMER1_BASE 0x40008000UL
1714#define LPC_UART0_BASE 0x4000C000UL
1715#define LPC_UART1_BASE 0x40010000UL
1716#define LPC_PWM1_BASE 0x40018000UL
1717#define LPC_I2C0_BASE 0x4001C000UL
1718#define LPC_SPI_BASE 0x40020000UL
1719#define LPC_RTC_BASE 0x40024000UL
1720#define LPC_GPIOINT_BASE 0x40028080UL
1721#define LPC_PINCONNECT_BASE 0x4002C000UL
1722#define LPC_SSP1_BASE 0x40030000UL
1723#define LPC_ADC_BASE 0x40034000UL
1724#define LPC_CANAFRAM_BASE 0x40038000UL
1725#define LPC_CANAF_BASE 0x4003C000UL
1726#define LPC_CCAN_BASE 0x40040000UL
1727#define LPC_CAN1_BASE 0x40044000UL
1728#define LPC_CAN2_BASE 0x40048000UL
1729#define LPC_I2C1_BASE 0x4005C000UL
1730#define LPC_SSP0_BASE 0x40088000UL
1731#define LPC_DAC_BASE 0x4008C000UL
1732#define LPC_TIMER2_BASE 0x40090000UL
1733#define LPC_TIMER3_BASE 0x40094000UL
1734#define LPC_UART2_BASE 0x40098000UL
1735#define LPC_UART3_BASE 0x4009C000UL
1736#define LPC_I2C2_BASE 0x400A0000UL
1737#define LPC_I2S_BASE 0x400A8000UL
1738#define LPC_RITIMER_BASE 0x400B0000UL
1739#define LPC_MCPWM_BASE 0x400B8000UL
1740#define LPC_QEI_BASE 0x400BC000UL
1741#define LPC_SYSCON_BASE 0x400FC000UL
1742#define LPC_EMAC_BASE 0x50000000UL
1743#define LPC_GPDMA_BASE 0x50004000UL
1744#define LPC_USB_BASE 0x50008000UL
1745#define LPC_GPIO_BASE 0x2009C000UL
1746
1747 /* End of group Device_Peripheral_peripheralAddr */
1748
1749
1750/* =========================================================================================================================== */
1751/* ================ Peripheral declaration ================ */
1752/* =========================================================================================================================== */
1753
1754
1759#define LPC_WDT ((LPC_WDT_Type*) LPC_WDT_BASE)
1760#define LPC_TIMER0 ((LPC_TIMER0_Type*) LPC_TIMER0_BASE)
1761#define LPC_TIMER1 ((LPC_TIMER1_Type*) LPC_TIMER1_BASE)
1762#define LPC_UART0 ((LPC_UART0_Type*) LPC_UART0_BASE)
1763#define LPC_UART1 ((LPC_UART1_Type*) LPC_UART1_BASE)
1764#define LPC_PWM1 ((LPC_PWM1_Type*) LPC_PWM1_BASE)
1765#define LPC_I2C0 ((LPC_I2C0_Type*) LPC_I2C0_BASE)
1766#define LPC_SPI ((LPC_SPI_Type*) LPC_SPI_BASE)
1767#define LPC_RTC ((LPC_RTC_Type*) LPC_RTC_BASE)
1768#define LPC_GPIOINT ((LPC_GPIOINT_Type*) LPC_GPIOINT_BASE)
1769#define LPC_PINCONNECT ((LPC_PINCONNECT_Type*) LPC_PINCONNECT_BASE)
1770#define LPC_SSP1 ((LPC_SSP1_Type*) LPC_SSP1_BASE)
1771#define LPC_ADC ((LPC_ADC_Type*) LPC_ADC_BASE)
1772#define LPC_CANAFRAM ((LPC_CANAFRAM_Type*) LPC_CANAFRAM_BASE)
1773#define LPC_CANAF ((LPC_CANAF_Type*) LPC_CANAF_BASE)
1774#define LPC_CCAN ((LPC_CCAN_Type*) LPC_CCAN_BASE)
1775#define LPC_CAN1 ((LPC_CAN1_Type*) LPC_CAN1_BASE)
1776#define LPC_CAN2 ((LPC_CAN2_Type*) LPC_CAN2_BASE)
1777#define LPC_I2C1 ((LPC_I2C0_Type*) LPC_I2C1_BASE)
1778#define LPC_SSP0 ((LPC_SSP0_Type*) LPC_SSP0_BASE)
1779#define LPC_DAC ((LPC_DAC_Type*) LPC_DAC_BASE)
1780#define LPC_TIMER2 ((LPC_TIMER2_Type*) LPC_TIMER2_BASE)
1781#define LPC_TIMER3 ((LPC_TIMER3_Type*) LPC_TIMER3_BASE)
1782#define LPC_UART2 ((LPC_UART2_Type*) LPC_UART2_BASE)
1783#define LPC_UART3 ((LPC_UART3_Type*) LPC_UART3_BASE)
1784#define LPC_I2C2 ((LPC_I2C0_Type*) LPC_I2C2_BASE)
1785#define LPC_I2S ((LPC_I2S_Type*) LPC_I2S_BASE)
1786#define LPC_RITIMER ((LPC_RITIMER_Type*) LPC_RITIMER_BASE)
1787#define LPC_MCPWM ((LPC_MCPWM_Type*) LPC_MCPWM_BASE)
1788#define LPC_QEI ((LPC_QEI_Type*) LPC_QEI_BASE)
1789#define LPC_SYSCON ((LPC_SYSCON_Type*) LPC_SYSCON_BASE)
1790#define LPC_EMAC ((LPC_EMAC_Type*) LPC_EMAC_BASE)
1791#define LPC_GPDMA ((LPC_GPDMA_Type*) LPC_GPDMA_BASE)
1792#define LPC_USB ((LPC_USB_Type*) LPC_USB_BASE)
1793#define LPC_GPIO ((LPC_GPIO_Type*) LPC_GPIO_BASE)
1794
1795 /* End of group Device_Peripheral_declaration */
1796
1797
1798/* ========================================= End of section using anonymous unions ========================================= */
1799#if defined (__CC_ARM)
1800 #pragma pop
1801#elif defined (__ICCARM__)
1802 /* leave anonymous unions enabled */
1803#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
1804 #pragma clang diagnostic pop
1805#elif defined (__GNUC__)
1806 /* anonymous unions are enabled by default */
1807#elif defined (__TMS470__)
1808 /* anonymous unions are enabled by default */
1809#elif defined (__TASKING__)
1810 #pragma warning restore
1811#elif defined (__CSMC__)
1812 /* anonymous unions are enabled by default */
1813#endif
1814
1815
1816/* =========================================================================================================================== */
1817/* ================ Pos/Mask Peripheral Section ================ */
1818/* =========================================================================================================================== */
1819
1820
1827/* =========================================================================================================================== */
1828/* ================ LPC_WDT ================ */
1829/* =========================================================================================================================== */
1830
1831/* ========================================================== MOD ========================================================== */
1832#define WDT_MOD_WDEN_Pos (0UL)
1833#define WDT_MOD_WDEN_Msk (0x1UL)
1834#define WDT_MOD_WDRESET_Pos (1UL)
1835#define WDT_MOD_WDRESET_Msk (0x2UL)
1836#define WDT_MOD_WDTOF_Pos (2UL)
1837#define WDT_MOD_WDTOF_Msk (0x4UL)
1838#define WDT_MOD_WDINT_Pos (3UL)
1839#define WDT_MOD_WDINT_Msk (0x8UL)
1840/* ========================================================== TC =========================================================== */
1841#define WDT_TC_Count_Pos (0UL)
1842#define WDT_TC_Count_Msk (0xffffffffUL)
1843/* ========================================================= FEED ========================================================== */
1844#define WDT_FEED_Feed_Pos (0UL)
1845#define WDT_FEED_Feed_Msk (0xffUL)
1846/* ========================================================== TV =========================================================== */
1847#define WDT_TV_Count_Pos (0UL)
1848#define WDT_TV_Count_Msk (0xffffffffUL)
1849/* ======================================================== CLKSEL ========================================================= */
1850#define WDT_CLKSEL_CLKSEL_Pos (0UL)
1851#define WDT_CLKSEL_CLKSEL_Msk (0x3UL)
1852#define WDT_CLKSEL_LOCK_Pos (31UL)
1853#define WDT_CLKSEL_LOCK_Msk (0x80000000UL)
1856/* =========================================================================================================================== */
1857/* ================ LPC_TIMER0 ================ */
1858/* =========================================================================================================================== */
1859
1860/* ========================================================== IR =========================================================== */
1861#define TIMER0_IR_MR0INT_Pos (0UL)
1862#define TIMER0_IR_MR0INT_Msk (0x1UL)
1863#define TIMER0_IR_MR1INT_Pos (1UL)
1864#define TIMER0_IR_MR1INT_Msk (0x2UL)
1865#define TIMER0_IR_MR2INT_Pos (2UL)
1866#define TIMER0_IR_MR2INT_Msk (0x4UL)
1867#define TIMER0_IR_MR3INT_Pos (3UL)
1868#define TIMER0_IR_MR3INT_Msk (0x8UL)
1869#define TIMER0_IR_CR0INT_Pos (4UL)
1870#define TIMER0_IR_CR0INT_Msk (0x10UL)
1871#define TIMER0_IR_CR1INT_Pos (5UL)
1872#define TIMER0_IR_CR1INT_Msk (0x20UL)
1873/* ========================================================== TCR ========================================================== */
1874#define TIMER0_TCR_CEN_Pos (0UL)
1875#define TIMER0_TCR_CEN_Msk (0x1UL)
1876#define TIMER0_TCR_CRST_Pos (1UL)
1877#define TIMER0_TCR_CRST_Msk (0x2UL)
1878/* ========================================================== TC =========================================================== */
1879#define TIMER0_TC_TC_Pos (0UL)
1880#define TIMER0_TC_TC_Msk (0xffffffffUL)
1881/* ========================================================== PR =========================================================== */
1882#define TIMER0_PR_PM_Pos (0UL)
1883#define TIMER0_PR_PM_Msk (0xffffffffUL)
1884/* ========================================================== PC =========================================================== */
1885#define TIMER0_PC_PC_Pos (0UL)
1886#define TIMER0_PC_PC_Msk (0xffffffffUL)
1887/* ========================================================== MCR ========================================================== */
1888#define TIMER0_MCR_MR0I_Pos (0UL)
1889#define TIMER0_MCR_MR0I_Msk (0x1UL)
1890#define TIMER0_MCR_MR0R_Pos (1UL)
1891#define TIMER0_MCR_MR0R_Msk (0x2UL)
1892#define TIMER0_MCR_MR0S_Pos (2UL)
1893#define TIMER0_MCR_MR0S_Msk (0x4UL)
1894#define TIMER0_MCR_MR1I_Pos (3UL)
1895#define TIMER0_MCR_MR1I_Msk (0x8UL)
1896#define TIMER0_MCR_MR1R_Pos (4UL)
1897#define TIMER0_MCR_MR1R_Msk (0x10UL)
1898#define TIMER0_MCR_MR1S_Pos (5UL)
1899#define TIMER0_MCR_MR1S_Msk (0x20UL)
1900#define TIMER0_MCR_MR2I_Pos (6UL)
1901#define TIMER0_MCR_MR2I_Msk (0x40UL)
1902#define TIMER0_MCR_MR2R_Pos (7UL)
1903#define TIMER0_MCR_MR2R_Msk (0x80UL)
1904#define TIMER0_MCR_MR2S_Pos (8UL)
1905#define TIMER0_MCR_MR2S_Msk (0x100UL)
1906#define TIMER0_MCR_MR3I_Pos (9UL)
1907#define TIMER0_MCR_MR3I_Msk (0x200UL)
1908#define TIMER0_MCR_MR3R_Pos (10UL)
1909#define TIMER0_MCR_MR3R_Msk (0x400UL)
1910#define TIMER0_MCR_MR3S_Pos (11UL)
1911#define TIMER0_MCR_MR3S_Msk (0x800UL)
1912/* ========================================================== CCR ========================================================== */
1913#define TIMER0_CCR_CAP0RE_Pos (0UL)
1914#define TIMER0_CCR_CAP0RE_Msk (0x1UL)
1915#define TIMER0_CCR_CAP0FE_Pos (1UL)
1916#define TIMER0_CCR_CAP0FE_Msk (0x2UL)
1917#define TIMER0_CCR_CAP0I_Pos (2UL)
1918#define TIMER0_CCR_CAP0I_Msk (0x4UL)
1919#define TIMER0_CCR_CAP1RE_Pos (3UL)
1920#define TIMER0_CCR_CAP1RE_Msk (0x8UL)
1921#define TIMER0_CCR_CAP1FE_Pos (4UL)
1922#define TIMER0_CCR_CAP1FE_Msk (0x10UL)
1923#define TIMER0_CCR_CAP1I_Pos (5UL)
1924#define TIMER0_CCR_CAP1I_Msk (0x20UL)
1925/* ========================================================== EMR ========================================================== */
1926#define TIMER0_EMR_EM0_Pos (0UL)
1927#define TIMER0_EMR_EM0_Msk (0x1UL)
1928#define TIMER0_EMR_EM1_Pos (1UL)
1929#define TIMER0_EMR_EM1_Msk (0x2UL)
1930#define TIMER0_EMR_EM2_Pos (2UL)
1931#define TIMER0_EMR_EM2_Msk (0x4UL)
1932#define TIMER0_EMR_EM3_Pos (3UL)
1933#define TIMER0_EMR_EM3_Msk (0x8UL)
1934#define TIMER0_EMR_EMC0_Pos (4UL)
1935#define TIMER0_EMR_EMC0_Msk (0x30UL)
1936#define TIMER0_EMR_EMC1_Pos (6UL)
1937#define TIMER0_EMR_EMC1_Msk (0xc0UL)
1938#define TIMER0_EMR_EMC2_Pos (8UL)
1939#define TIMER0_EMR_EMC2_Msk (0x300UL)
1940#define TIMER0_EMR_EMC3_Pos (10UL)
1941#define TIMER0_EMR_EMC3_Msk (0xc00UL)
1942/* ========================================================= CTCR ========================================================== */
1943#define TIMER0_CTCR_CTMODE_Pos (0UL)
1944#define TIMER0_CTCR_CTMODE_Msk (0x3UL)
1945#define TIMER0_CTCR_CINSEL_Pos (2UL)
1946#define TIMER0_CTCR_CINSEL_Msk (0xcUL)
1949/* =========================================================================================================================== */
1950/* ================ LPC_TIMER1 ================ */
1951/* =========================================================================================================================== */
1952
1953/* ========================================================== IR =========================================================== */
1954#define TIMER1_IR_MR0INT_Pos (0UL)
1955#define TIMER1_IR_MR0INT_Msk (0x1UL)
1956#define TIMER1_IR_MR1INT_Pos (1UL)
1957#define TIMER1_IR_MR1INT_Msk (0x2UL)
1958#define TIMER1_IR_MR2INT_Pos (2UL)
1959#define TIMER1_IR_MR2INT_Msk (0x4UL)
1960#define TIMER1_IR_MR3INT_Pos (3UL)
1961#define TIMER1_IR_MR3INT_Msk (0x8UL)
1962#define TIMER1_IR_CR0INT_Pos (4UL)
1963#define TIMER1_IR_CR0INT_Msk (0x10UL)
1964#define TIMER1_IR_CR1INT_Pos (5UL)
1965#define TIMER1_IR_CR1INT_Msk (0x20UL)
1966/* ========================================================== TCR ========================================================== */
1967#define TIMER1_TCR_CEN_Pos (0UL)
1968#define TIMER1_TCR_CEN_Msk (0x1UL)
1969#define TIMER1_TCR_CRST_Pos (1UL)
1970#define TIMER1_TCR_CRST_Msk (0x2UL)
1971/* ========================================================== TC =========================================================== */
1972#define TIMER1_TC_TC_Pos (0UL)
1973#define TIMER1_TC_TC_Msk (0xffffffffUL)
1974/* ========================================================== PR =========================================================== */
1975#define TIMER1_PR_PM_Pos (0UL)
1976#define TIMER1_PR_PM_Msk (0xffffffffUL)
1977/* ========================================================== PC =========================================================== */
1978#define TIMER1_PC_PC_Pos (0UL)
1979#define TIMER1_PC_PC_Msk (0xffffffffUL)
1980/* ========================================================== MCR ========================================================== */
1981#define TIMER1_MCR_MR0I_Pos (0UL)
1982#define TIMER1_MCR_MR0I_Msk (0x1UL)
1983#define TIMER1_MCR_MR0R_Pos (1UL)
1984#define TIMER1_MCR_MR0R_Msk (0x2UL)
1985#define TIMER1_MCR_MR0S_Pos (2UL)
1986#define TIMER1_MCR_MR0S_Msk (0x4UL)
1987#define TIMER1_MCR_MR1I_Pos (3UL)
1988#define TIMER1_MCR_MR1I_Msk (0x8UL)
1989#define TIMER1_MCR_MR1R_Pos (4UL)
1990#define TIMER1_MCR_MR1R_Msk (0x10UL)
1991#define TIMER1_MCR_MR1S_Pos (5UL)
1992#define TIMER1_MCR_MR1S_Msk (0x20UL)
1993#define TIMER1_MCR_MR2I_Pos (6UL)
1994#define TIMER1_MCR_MR2I_Msk (0x40UL)
1995#define TIMER1_MCR_MR2R_Pos (7UL)
1996#define TIMER1_MCR_MR2R_Msk (0x80UL)
1997#define TIMER1_MCR_MR2S_Pos (8UL)
1998#define TIMER1_MCR_MR2S_Msk (0x100UL)
1999#define TIMER1_MCR_MR3I_Pos (9UL)
2000#define TIMER1_MCR_MR3I_Msk (0x200UL)
2001#define TIMER1_MCR_MR3R_Pos (10UL)
2002#define TIMER1_MCR_MR3R_Msk (0x400UL)
2003#define TIMER1_MCR_MR3S_Pos (11UL)
2004#define TIMER1_MCR_MR3S_Msk (0x800UL)
2005/* ========================================================== CCR ========================================================== */
2006#define TIMER1_CCR_CAP0RE_Pos (0UL)
2007#define TIMER1_CCR_CAP0RE_Msk (0x1UL)
2008#define TIMER1_CCR_CAP0FE_Pos (1UL)
2009#define TIMER1_CCR_CAP0FE_Msk (0x2UL)
2010#define TIMER1_CCR_CAP0I_Pos (2UL)
2011#define TIMER1_CCR_CAP0I_Msk (0x4UL)
2012#define TIMER1_CCR_CAP1RE_Pos (3UL)
2013#define TIMER1_CCR_CAP1RE_Msk (0x8UL)
2014#define TIMER1_CCR_CAP1FE_Pos (4UL)
2015#define TIMER1_CCR_CAP1FE_Msk (0x10UL)
2016#define TIMER1_CCR_CAP1I_Pos (5UL)
2017#define TIMER1_CCR_CAP1I_Msk (0x20UL)
2018/* ========================================================== EMR ========================================================== */
2019#define TIMER1_EMR_EM0_Pos (0UL)
2020#define TIMER1_EMR_EM0_Msk (0x1UL)
2021#define TIMER1_EMR_EM1_Pos (1UL)
2022#define TIMER1_EMR_EM1_Msk (0x2UL)
2023#define TIMER1_EMR_EM2_Pos (2UL)
2024#define TIMER1_EMR_EM2_Msk (0x4UL)
2025#define TIMER1_EMR_EM3_Pos (3UL)
2026#define TIMER1_EMR_EM3_Msk (0x8UL)
2027#define TIMER1_EMR_EMC0_Pos (4UL)
2028#define TIMER1_EMR_EMC0_Msk (0x30UL)
2029#define TIMER1_EMR_EMC1_Pos (6UL)
2030#define TIMER1_EMR_EMC1_Msk (0xc0UL)
2031#define TIMER1_EMR_EMC2_Pos (8UL)
2032#define TIMER1_EMR_EMC2_Msk (0x300UL)
2033#define TIMER1_EMR_EMC3_Pos (10UL)
2034#define TIMER1_EMR_EMC3_Msk (0xc00UL)
2035/* ========================================================= CTCR ========================================================== */
2036#define TIMER1_CTCR_CTMODE_Pos (0UL)
2037#define TIMER1_CTCR_CTMODE_Msk (0x3UL)
2038#define TIMER1_CTCR_CINSEL_Pos (2UL)
2039#define TIMER1_CTCR_CINSEL_Msk (0xcUL)
2042/* =========================================================================================================================== */
2043/* ================ LPC_UART0 ================ */
2044/* =========================================================================================================================== */
2045
2046/* ========================================================== RBR ========================================================== */
2047#define UART0_RBR_RBR_Pos (0UL)
2048#define UART0_RBR_RBR_Msk (0xffUL)
2049/* ========================================================== THR ========================================================== */
2050#define UART0_THR_THR_Pos (0UL)
2051#define UART0_THR_THR_Msk (0xffUL)
2052/* ========================================================== DLL ========================================================== */
2053#define UART0_DLL_DLLSB_Pos (0UL)
2054#define UART0_DLL_DLLSB_Msk (0xffUL)
2055/* ========================================================== DLM ========================================================== */
2056#define UART0_DLM_DLMSB_Pos (0UL)
2057#define UART0_DLM_DLMSB_Msk (0xffUL)
2058/* ========================================================== IER ========================================================== */
2059#define UART0_IER_RBRIE_Pos (0UL)
2060#define UART0_IER_RBRIE_Msk (0x1UL)
2061#define UART0_IER_THREIE_Pos (1UL)
2062#define UART0_IER_THREIE_Msk (0x2UL)
2063#define UART0_IER_RXIE_Pos (2UL)
2064#define UART0_IER_RXIE_Msk (0x4UL)
2065#define UART0_IER_ABEOINTEN_Pos (8UL)
2066#define UART0_IER_ABEOINTEN_Msk (0x100UL)
2067#define UART0_IER_ABTOINTEN_Pos (9UL)
2068#define UART0_IER_ABTOINTEN_Msk (0x200UL)
2069/* ========================================================== IIR ========================================================== */
2070#define UART0_IIR_INTSTATUS_Pos (0UL)
2071#define UART0_IIR_INTSTATUS_Msk (0x1UL)
2072#define UART0_IIR_INTID_Pos (1UL)
2073#define UART0_IIR_INTID_Msk (0xeUL)
2074#define UART0_IIR_FIFOENABLE_Pos (6UL)
2075#define UART0_IIR_FIFOENABLE_Msk (0xc0UL)
2076#define UART0_IIR_ABEOINT_Pos (8UL)
2077#define UART0_IIR_ABEOINT_Msk (0x100UL)
2078#define UART0_IIR_ABTOINT_Pos (9UL)
2079#define UART0_IIR_ABTOINT_Msk (0x200UL)
2080/* ========================================================== FCR ========================================================== */
2081#define UART0_FCR_FIFOEN_Pos (0UL)
2082#define UART0_FCR_FIFOEN_Msk (0x1UL)
2083#define UART0_FCR_RXFIFORES_Pos (1UL)
2084#define UART0_FCR_RXFIFORES_Msk (0x2UL)
2085#define UART0_FCR_TXFIFORES_Pos (2UL)
2086#define UART0_FCR_TXFIFORES_Msk (0x4UL)
2087#define UART0_FCR_DMAMODE_Pos (3UL)
2088#define UART0_FCR_DMAMODE_Msk (0x8UL)
2089#define UART0_FCR_RXTRIGLVL_Pos (6UL)
2090#define UART0_FCR_RXTRIGLVL_Msk (0xc0UL)
2091/* ========================================================== LCR ========================================================== */
2092#define UART0_LCR_WLS_Pos (0UL)
2093#define UART0_LCR_WLS_Msk (0x3UL)
2094#define UART0_LCR_SBS_Pos (2UL)
2095#define UART0_LCR_SBS_Msk (0x4UL)
2096#define UART0_LCR_PE_Pos (3UL)
2097#define UART0_LCR_PE_Msk (0x8UL)
2098#define UART0_LCR_PS_Pos (4UL)
2099#define UART0_LCR_PS_Msk (0x30UL)
2100#define UART0_LCR_BC_Pos (6UL)
2101#define UART0_LCR_BC_Msk (0x40UL)
2102#define UART0_LCR_DLAB_Pos (7UL)
2103#define UART0_LCR_DLAB_Msk (0x80UL)
2104/* ========================================================== LSR ========================================================== */
2105#define UART0_LSR_RDR_Pos (0UL)
2106#define UART0_LSR_RDR_Msk (0x1UL)
2107#define UART0_LSR_OE_Pos (1UL)
2108#define UART0_LSR_OE_Msk (0x2UL)
2109#define UART0_LSR_PE_Pos (2UL)
2110#define UART0_LSR_PE_Msk (0x4UL)
2111#define UART0_LSR_FE_Pos (3UL)
2112#define UART0_LSR_FE_Msk (0x8UL)
2113#define UART0_LSR_BI_Pos (4UL)
2114#define UART0_LSR_BI_Msk (0x10UL)
2115#define UART0_LSR_THRE_Pos (5UL)
2116#define UART0_LSR_THRE_Msk (0x20UL)
2117#define UART0_LSR_TEMT_Pos (6UL)
2118#define UART0_LSR_TEMT_Msk (0x40UL)
2119#define UART0_LSR_RXFE_Pos (7UL)
2120#define UART0_LSR_RXFE_Msk (0x80UL)
2121/* ========================================================== SCR ========================================================== */
2122#define UART0_SCR_PAD_Pos (0UL)
2123#define UART0_SCR_PAD_Msk (0xffUL)
2124/* ========================================================== ACR ========================================================== */
2125#define UART0_ACR_START_Pos (0UL)
2126#define UART0_ACR_START_Msk (0x1UL)
2127#define UART0_ACR_MODE_Pos (1UL)
2128#define UART0_ACR_MODE_Msk (0x2UL)
2129#define UART0_ACR_AUTORESTART_Pos (2UL)
2130#define UART0_ACR_AUTORESTART_Msk (0x4UL)
2131#define UART0_ACR_ABEOINTCLR_Pos (8UL)
2132#define UART0_ACR_ABEOINTCLR_Msk (0x100UL)
2133#define UART0_ACR_ABTOINTCLR_Pos (9UL)
2134#define UART0_ACR_ABTOINTCLR_Msk (0x200UL)
2135/* ========================================================== FDR ========================================================== */
2136#define UART0_FDR_DIVADDVAL_Pos (0UL)
2137#define UART0_FDR_DIVADDVAL_Msk (0xfUL)
2138#define UART0_FDR_MULVAL_Pos (4UL)
2139#define UART0_FDR_MULVAL_Msk (0xf0UL)
2140/* ========================================================== TER ========================================================== */
2141#define UART0_TER_TXEN_Pos (7UL)
2142#define UART0_TER_TXEN_Msk (0x80UL)
2143/* ======================================================= RS485CTRL ======================================================= */
2144#define UART0_RS485CTRL_NMMEN_Pos (0UL)
2145#define UART0_RS485CTRL_NMMEN_Msk (0x1UL)
2146#define UART0_RS485CTRL_RXDIS_Pos (1UL)
2147#define UART0_RS485CTRL_RXDIS_Msk (0x2UL)
2148#define UART0_RS485CTRL_AADEN_Pos (2UL)
2149#define UART0_RS485CTRL_AADEN_Msk (0x4UL)
2150#define UART0_RS485CTRL_DCTRL_Pos (4UL)
2151#define UART0_RS485CTRL_DCTRL_Msk (0x10UL)
2152#define UART0_RS485CTRL_OINV_Pos (5UL)
2153#define UART0_RS485CTRL_OINV_Msk (0x20UL)
2154/* ===================================================== RS485ADRMATCH ===================================================== */
2155#define UART0_RS485ADRMATCH_ADRMATCH_Pos (0UL)
2156#define UART0_RS485ADRMATCH_ADRMATCH_Msk (0xffUL)
2157/* ======================================================= RS485DLY ======================================================== */
2158#define UART0_RS485DLY_DLY_Pos (0UL)
2159#define UART0_RS485DLY_DLY_Msk (0xffUL)
2162/* =========================================================================================================================== */
2163/* ================ LPC_UART1 ================ */
2164/* =========================================================================================================================== */
2165
2166/* ========================================================== RBR ========================================================== */
2167#define UART1_RBR_RBR_Pos (0UL)
2168#define UART1_RBR_RBR_Msk (0xffUL)
2169/* ========================================================== THR ========================================================== */
2170#define UART1_THR_THR_Pos (0UL)
2171#define UART1_THR_THR_Msk (0xffUL)
2172/* ========================================================== DLL ========================================================== */
2173#define UART1_DLL_DLLSB_Pos (0UL)
2174#define UART1_DLL_DLLSB_Msk (0xffUL)
2175/* ========================================================== DLM ========================================================== */
2176#define UART1_DLM_DLMSB_Pos (0UL)
2177#define UART1_DLM_DLMSB_Msk (0xffUL)
2178/* ========================================================== IER ========================================================== */
2179#define UART1_IER_RBRIE_Pos (0UL)
2180#define UART1_IER_RBRIE_Msk (0x1UL)
2181#define UART1_IER_THREIE_Pos (1UL)
2182#define UART1_IER_THREIE_Msk (0x2UL)
2183#define UART1_IER_RXIE_Pos (2UL)
2184#define UART1_IER_RXIE_Msk (0x4UL)
2185#define UART1_IER_MSIE_Pos (3UL)
2186#define UART1_IER_MSIE_Msk (0x8UL)
2187#define UART1_IER_CTSIE_Pos (7UL)
2188#define UART1_IER_CTSIE_Msk (0x80UL)
2189#define UART1_IER_ABEOIE_Pos (8UL)
2190#define UART1_IER_ABEOIE_Msk (0x100UL)
2191#define UART1_IER_ABTOIE_Pos (9UL)
2192#define UART1_IER_ABTOIE_Msk (0x200UL)
2193/* ========================================================== IIR ========================================================== */
2194#define UART1_IIR_INTSTATUS_Pos (0UL)
2195#define UART1_IIR_INTSTATUS_Msk (0x1UL)
2196#define UART1_IIR_INTID_Pos (1UL)
2197#define UART1_IIR_INTID_Msk (0xeUL)
2198#define UART1_IIR_FIFOENABLE_Pos (6UL)
2199#define UART1_IIR_FIFOENABLE_Msk (0xc0UL)
2200#define UART1_IIR_ABEOINT_Pos (8UL)
2201#define UART1_IIR_ABEOINT_Msk (0x100UL)
2202#define UART1_IIR_ABTOINT_Pos (9UL)
2203#define UART1_IIR_ABTOINT_Msk (0x200UL)
2204/* ========================================================== FCR ========================================================== */
2205#define UART1_FCR_FIFOEN_Pos (0UL)
2206#define UART1_FCR_FIFOEN_Msk (0x1UL)
2207#define UART1_FCR_RXFIFORES_Pos (1UL)
2208#define UART1_FCR_RXFIFORES_Msk (0x2UL)
2209#define UART1_FCR_TXFIFORES_Pos (2UL)
2210#define UART1_FCR_TXFIFORES_Msk (0x4UL)
2211#define UART1_FCR_DMAMODE_Pos (3UL)
2212#define UART1_FCR_DMAMODE_Msk (0x8UL)
2213#define UART1_FCR_RXTRIGLVL_Pos (6UL)
2214#define UART1_FCR_RXTRIGLVL_Msk (0xc0UL)
2215/* ========================================================== LCR ========================================================== */
2216#define UART1_LCR_WLS_Pos (0UL)
2217#define UART1_LCR_WLS_Msk (0x3UL)
2218#define UART1_LCR_SBS_Pos (2UL)
2219#define UART1_LCR_SBS_Msk (0x4UL)
2220#define UART1_LCR_PE_Pos (3UL)
2221#define UART1_LCR_PE_Msk (0x8UL)
2222#define UART1_LCR_PS_Pos (4UL)
2223#define UART1_LCR_PS_Msk (0x30UL)
2224#define UART1_LCR_BC_Pos (6UL)
2225#define UART1_LCR_BC_Msk (0x40UL)
2226#define UART1_LCR_DLAB_Pos (7UL)
2227#define UART1_LCR_DLAB_Msk (0x80UL)
2228/* ========================================================== MCR ========================================================== */
2229#define UART1_MCR_DTRCTRL_Pos (0UL)
2230#define UART1_MCR_DTRCTRL_Msk (0x1UL)
2231#define UART1_MCR_RTSCTRL_Pos (1UL)
2232#define UART1_MCR_RTSCTRL_Msk (0x2UL)
2233#define UART1_MCR_LMS_Pos (4UL)
2234#define UART1_MCR_LMS_Msk (0x10UL)
2235#define UART1_MCR_RTSEN_Pos (6UL)
2236#define UART1_MCR_RTSEN_Msk (0x40UL)
2237#define UART1_MCR_CTSEN_Pos (7UL)
2238#define UART1_MCR_CTSEN_Msk (0x80UL)
2239/* ========================================================== LSR ========================================================== */
2240#define UART1_LSR_RDR_Pos (0UL)
2241#define UART1_LSR_RDR_Msk (0x1UL)
2242#define UART1_LSR_OE_Pos (1UL)
2243#define UART1_LSR_OE_Msk (0x2UL)
2244#define UART1_LSR_PE_Pos (2UL)
2245#define UART1_LSR_PE_Msk (0x4UL)
2246#define UART1_LSR_FE_Pos (3UL)
2247#define UART1_LSR_FE_Msk (0x8UL)
2248#define UART1_LSR_BI_Pos (4UL)
2249#define UART1_LSR_BI_Msk (0x10UL)
2250#define UART1_LSR_THRE_Pos (5UL)
2251#define UART1_LSR_THRE_Msk (0x20UL)
2252#define UART1_LSR_TEMT_Pos (6UL)
2253#define UART1_LSR_TEMT_Msk (0x40UL)
2254#define UART1_LSR_RXFE_Pos (7UL)
2255#define UART1_LSR_RXFE_Msk (0x80UL)
2256/* ========================================================== MSR ========================================================== */
2257#define UART1_MSR_DCTS_Pos (0UL)
2258#define UART1_MSR_DCTS_Msk (0x1UL)
2259#define UART1_MSR_DDSR_Pos (1UL)
2260#define UART1_MSR_DDSR_Msk (0x2UL)
2261#define UART1_MSR_TERI_Pos (2UL)
2262#define UART1_MSR_TERI_Msk (0x4UL)
2263#define UART1_MSR_DDCD_Pos (3UL)
2264#define UART1_MSR_DDCD_Msk (0x8UL)
2265#define UART1_MSR_CTS_Pos (4UL)
2266#define UART1_MSR_CTS_Msk (0x10UL)
2267#define UART1_MSR_DSR_Pos (5UL)
2268#define UART1_MSR_DSR_Msk (0x20UL)
2269#define UART1_MSR_RI_Pos (6UL)
2270#define UART1_MSR_RI_Msk (0x40UL)
2271#define UART1_MSR_DCD_Pos (7UL)
2272#define UART1_MSR_DCD_Msk (0x80UL)
2273/* ========================================================== SCR ========================================================== */
2274#define UART1_SCR_Pad_Pos (0UL)
2275#define UART1_SCR_Pad_Msk (0xffUL)
2276/* ========================================================== ACR ========================================================== */
2277#define UART1_ACR_START_Pos (0UL)
2278#define UART1_ACR_START_Msk (0x1UL)
2279#define UART1_ACR_MODE_Pos (1UL)
2280#define UART1_ACR_MODE_Msk (0x2UL)
2281#define UART1_ACR_AUTORESTART_Pos (2UL)
2282#define UART1_ACR_AUTORESTART_Msk (0x4UL)
2283#define UART1_ACR_ABEOINTCLR_Pos (8UL)
2284#define UART1_ACR_ABEOINTCLR_Msk (0x100UL)
2285#define UART1_ACR_ABTOINTCLR_Pos (9UL)
2286#define UART1_ACR_ABTOINTCLR_Msk (0x200UL)
2287/* ========================================================== FDR ========================================================== */
2288#define UART1_FDR_DIVADDVAL_Pos (0UL)
2289#define UART1_FDR_DIVADDVAL_Msk (0xfUL)
2290#define UART1_FDR_MULVAL_Pos (4UL)
2291#define UART1_FDR_MULVAL_Msk (0xf0UL)
2292/* ========================================================== TER ========================================================== */
2293#define UART1_TER_TXEN_Pos (7UL)
2294#define UART1_TER_TXEN_Msk (0x80UL)
2295/* ======================================================= RS485CTRL ======================================================= */
2296#define UART1_RS485CTRL_NMMEN_Pos (0UL)
2297#define UART1_RS485CTRL_NMMEN_Msk (0x1UL)
2298#define UART1_RS485CTRL_RXDIS_Pos (1UL)
2299#define UART1_RS485CTRL_RXDIS_Msk (0x2UL)
2300#define UART1_RS485CTRL_AADEN_Pos (2UL)
2301#define UART1_RS485CTRL_AADEN_Msk (0x4UL)
2302#define UART1_RS485CTRL_SEL_Pos (3UL)
2303#define UART1_RS485CTRL_SEL_Msk (0x8UL)
2304#define UART1_RS485CTRL_DCTRL_Pos (4UL)
2305#define UART1_RS485CTRL_DCTRL_Msk (0x10UL)
2306#define UART1_RS485CTRL_OINV_Pos (5UL)
2307#define UART1_RS485CTRL_OINV_Msk (0x20UL)
2308/* ===================================================== RS485ADRMATCH ===================================================== */
2309#define UART1_RS485ADRMATCH_ADRMATCH_Pos (0UL)
2310#define UART1_RS485ADRMATCH_ADRMATCH_Msk (0xffUL)
2311/* ======================================================= RS485DLY ======================================================== */
2312#define UART1_RS485DLY_DLY_Pos (0UL)
2313#define UART1_RS485DLY_DLY_Msk (0xffUL)
2316/* =========================================================================================================================== */
2317/* ================ LPC_PWM1 ================ */
2318/* =========================================================================================================================== */
2319
2320/* ========================================================== IR =========================================================== */
2321#define PWM1_IR_PWMMR0INT_Pos (0UL)
2322#define PWM1_IR_PWMMR0INT_Msk (0x1UL)
2323#define PWM1_IR_PWMMR1INT_Pos (1UL)
2324#define PWM1_IR_PWMMR1INT_Msk (0x2UL)
2325#define PWM1_IR_PWMMR2INT_Pos (2UL)
2326#define PWM1_IR_PWMMR2INT_Msk (0x4UL)
2327#define PWM1_IR_PWMMR3INT_Pos (3UL)
2328#define PWM1_IR_PWMMR3INT_Msk (0x8UL)
2329#define PWM1_IR_PWMCAP0INT_Pos (4UL)
2330#define PWM1_IR_PWMCAP0INT_Msk (0x10UL)
2331#define PWM1_IR_PWMCAP1INT_Pos (5UL)
2332#define PWM1_IR_PWMCAP1INT_Msk (0x20UL)
2333#define PWM1_IR_PWMMR4INT_Pos (8UL)
2334#define PWM1_IR_PWMMR4INT_Msk (0x100UL)
2335#define PWM1_IR_PWMMR5INT_Pos (9UL)
2336#define PWM1_IR_PWMMR5INT_Msk (0x200UL)
2337#define PWM1_IR_PWMMR6INT_Pos (10UL)
2338#define PWM1_IR_PWMMR6INT_Msk (0x400UL)
2339/* ========================================================== TCR ========================================================== */
2340#define PWM1_TCR_CE_Pos (0UL)
2341#define PWM1_TCR_CE_Msk (0x1UL)
2342#define PWM1_TCR_CR_Pos (1UL)
2343#define PWM1_TCR_CR_Msk (0x2UL)
2344#define PWM1_TCR_PWMEN_Pos (3UL)
2345#define PWM1_TCR_PWMEN_Msk (0x8UL)
2346#define PWM1_TCR_MDIS_Pos (4UL)
2347#define PWM1_TCR_MDIS_Msk (0x10UL)
2348/* ========================================================== TC =========================================================== */
2349#define PWM1_TC_TC_Pos (0UL)
2350#define PWM1_TC_TC_Msk (0xffffffffUL)
2351/* ========================================================== PR =========================================================== */
2352#define PWM1_PR_PM_Pos (0UL)
2353#define PWM1_PR_PM_Msk (0xffffffffUL)
2354/* ========================================================== PC =========================================================== */
2355#define PWM1_PC_PC_Pos (0UL)
2356#define PWM1_PC_PC_Msk (0xffffffffUL)
2357/* ========================================================== MCR ========================================================== */
2358#define PWM1_MCR_PWMMR0I_Pos (0UL)
2359#define PWM1_MCR_PWMMR0I_Msk (0x1UL)
2360#define PWM1_MCR_PWMMR0R_Pos (1UL)
2361#define PWM1_MCR_PWMMR0R_Msk (0x2UL)
2362#define PWM1_MCR_PWMMR0S_Pos (2UL)
2363#define PWM1_MCR_PWMMR0S_Msk (0x4UL)
2364#define PWM1_MCR_PWMMR1I_Pos (3UL)
2365#define PWM1_MCR_PWMMR1I_Msk (0x8UL)
2366#define PWM1_MCR_PWMMR1R_Pos (4UL)
2367#define PWM1_MCR_PWMMR1R_Msk (0x10UL)
2368#define PWM1_MCR_PWMMR1S_Pos (5UL)
2369#define PWM1_MCR_PWMMR1S_Msk (0x20UL)
2370#define PWM1_MCR_PWMMR2I_Pos (6UL)
2371#define PWM1_MCR_PWMMR2I_Msk (0x40UL)
2372#define PWM1_MCR_PWMMR2R_Pos (7UL)
2373#define PWM1_MCR_PWMMR2R_Msk (0x80UL)
2374#define PWM1_MCR_PWMMR2S_Pos (8UL)
2375#define PWM1_MCR_PWMMR2S_Msk (0x100UL)
2376#define PWM1_MCR_PWMMR3I_Pos (9UL)
2377#define PWM1_MCR_PWMMR3I_Msk (0x200UL)
2378#define PWM1_MCR_PWMMR3R_Pos (10UL)
2379#define PWM1_MCR_PWMMR3R_Msk (0x400UL)
2380#define PWM1_MCR_PWMMR3S_Pos (11UL)
2381#define PWM1_MCR_PWMMR3S_Msk (0x800UL)
2382#define PWM1_MCR_PWMMR4I_Pos (12UL)
2383#define PWM1_MCR_PWMMR4I_Msk (0x1000UL)
2384#define PWM1_MCR_PWMMR4R_Pos (13UL)
2385#define PWM1_MCR_PWMMR4R_Msk (0x2000UL)
2386#define PWM1_MCR_PWMMR4S_Pos (14UL)
2387#define PWM1_MCR_PWMMR4S_Msk (0x4000UL)
2388#define PWM1_MCR_PWMMR5I_Pos (15UL)
2389#define PWM1_MCR_PWMMR5I_Msk (0x8000UL)
2390#define PWM1_MCR_PWMMR5R_Pos (16UL)
2391#define PWM1_MCR_PWMMR5R_Msk (0x10000UL)
2392#define PWM1_MCR_PWMMR5S_Pos (17UL)
2393#define PWM1_MCR_PWMMR5S_Msk (0x20000UL)
2394#define PWM1_MCR_PWMMR6I_Pos (18UL)
2395#define PWM1_MCR_PWMMR6I_Msk (0x40000UL)
2396#define PWM1_MCR_PWMMR6R_Pos (19UL)
2397#define PWM1_MCR_PWMMR6R_Msk (0x80000UL)
2398#define PWM1_MCR_PWMMR6S_Pos (20UL)
2399#define PWM1_MCR_PWMMR6S_Msk (0x100000UL)
2400/* ========================================================== MR0 ========================================================== */
2401#define PWM1_MR0_MATCH_Pos (0UL)
2402#define PWM1_MR0_MATCH_Msk (0xffffffffUL)
2403/* ========================================================== MR1 ========================================================== */
2404#define PWM1_MR1_MATCH_Pos (0UL)
2405#define PWM1_MR1_MATCH_Msk (0xffffffffUL)
2406/* ========================================================== MR2 ========================================================== */
2407#define PWM1_MR2_MATCH_Pos (0UL)
2408#define PWM1_MR2_MATCH_Msk (0xffffffffUL)
2409/* ========================================================== MR3 ========================================================== */
2410#define PWM1_MR3_MATCH_Pos (0UL)
2411#define PWM1_MR3_MATCH_Msk (0xffffffffUL)
2412/* ========================================================== CCR ========================================================== */
2413#define PWM1_CCR_CAP0_R_Pos (0UL)
2414#define PWM1_CCR_CAP0_R_Msk (0x1UL)
2415#define PWM1_CCR_CAP0_F_Pos (1UL)
2416#define PWM1_CCR_CAP0_F_Msk (0x2UL)
2417#define PWM1_CCR_CAP0_I_Pos (2UL)
2418#define PWM1_CCR_CAP0_I_Msk (0x4UL)
2419#define PWM1_CCR_CAP1_R_Pos (3UL)
2420#define PWM1_CCR_CAP1_R_Msk (0x8UL)
2421#define PWM1_CCR_CAP1_F_Pos (4UL)
2422#define PWM1_CCR_CAP1_F_Msk (0x10UL)
2423#define PWM1_CCR_CAP1_I_Pos (5UL)
2424#define PWM1_CCR_CAP1_I_Msk (0x20UL)
2425/* ========================================================== MR4 ========================================================== */
2426#define PWM1_MR4_MATCH_Pos (0UL)
2427#define PWM1_MR4_MATCH_Msk (0xffffffffUL)
2428/* ========================================================== MR5 ========================================================== */
2429#define PWM1_MR5_MATCH_Pos (0UL)
2430#define PWM1_MR5_MATCH_Msk (0xffffffffUL)
2431/* ========================================================== MR6 ========================================================== */
2432#define PWM1_MR6_MATCH_Pos (0UL)
2433#define PWM1_MR6_MATCH_Msk (0xffffffffUL)
2434/* ========================================================== PCR ========================================================== */
2435#define PWM1_PCR_PWMSEL2_Pos (2UL)
2436#define PWM1_PCR_PWMSEL2_Msk (0x4UL)
2437#define PWM1_PCR_PWMSEL3_Pos (3UL)
2438#define PWM1_PCR_PWMSEL3_Msk (0x8UL)
2439#define PWM1_PCR_PWMSEL4_Pos (4UL)
2440#define PWM1_PCR_PWMSEL4_Msk (0x10UL)
2441#define PWM1_PCR_PWMSEL5_Pos (5UL)
2442#define PWM1_PCR_PWMSEL5_Msk (0x20UL)
2443#define PWM1_PCR_PWMSEL6_Pos (6UL)
2444#define PWM1_PCR_PWMSEL6_Msk (0x40UL)
2445#define PWM1_PCR_PWMENA1_Pos (9UL)
2446#define PWM1_PCR_PWMENA1_Msk (0x200UL)
2447#define PWM1_PCR_PWMENA2_Pos (10UL)
2448#define PWM1_PCR_PWMENA2_Msk (0x400UL)
2449#define PWM1_PCR_PWMENA3_Pos (11UL)
2450#define PWM1_PCR_PWMENA3_Msk (0x800UL)
2451#define PWM1_PCR_PWMENA4_Pos (12UL)
2452#define PWM1_PCR_PWMENA4_Msk (0x1000UL)
2453#define PWM1_PCR_PWMENA5_Pos (13UL)
2454#define PWM1_PCR_PWMENA5_Msk (0x2000UL)
2455#define PWM1_PCR_PWMENA6_Pos (14UL)
2456#define PWM1_PCR_PWMENA6_Msk (0x4000UL)
2457/* ========================================================== LER ========================================================== */
2458#define PWM1_LER_MAT0LATCHEN_Pos (0UL)
2459#define PWM1_LER_MAT0LATCHEN_Msk (0x1UL)
2460#define PWM1_LER_MAT1LATCHEN_Pos (1UL)
2461#define PWM1_LER_MAT1LATCHEN_Msk (0x2UL)
2462#define PWM1_LER_MAT2LATCHEN_Pos (2UL)
2463#define PWM1_LER_MAT2LATCHEN_Msk (0x4UL)
2464#define PWM1_LER_MAT3LATCHEN_Pos (3UL)
2465#define PWM1_LER_MAT3LATCHEN_Msk (0x8UL)
2466#define PWM1_LER_MAT4LATCHEN_Pos (4UL)
2467#define PWM1_LER_MAT4LATCHEN_Msk (0x10UL)
2468#define PWM1_LER_MAT5LATCHEN_Pos (5UL)
2469#define PWM1_LER_MAT5LATCHEN_Msk (0x20UL)
2470#define PWM1_LER_MAT6LATCHEN_Pos (6UL)
2471#define PWM1_LER_MAT6LATCHEN_Msk (0x40UL)
2472/* ========================================================= CTCR ========================================================== */
2473#define PWM1_CTCR_MOD_Pos (0UL)
2474#define PWM1_CTCR_MOD_Msk (0x3UL)
2475#define PWM1_CTCR_CIS_Pos (2UL)
2476#define PWM1_CTCR_CIS_Msk (0xcUL)
2479/* =========================================================================================================================== */
2480/* ================ LPC_I2C0 ================ */
2481/* =========================================================================================================================== */
2482
2483/* ======================================================== CONSET ========================================================= */
2484#define I2C0_CONSET_AA_Pos (2UL)
2485#define I2C0_CONSET_AA_Msk (0x4UL)
2486#define I2C0_CONSET_SI_Pos (3UL)
2487#define I2C0_CONSET_SI_Msk (0x8UL)
2488#define I2C0_CONSET_STO_Pos (4UL)
2489#define I2C0_CONSET_STO_Msk (0x10UL)
2490#define I2C0_CONSET_STA_Pos (5UL)
2491#define I2C0_CONSET_STA_Msk (0x20UL)
2492#define I2C0_CONSET_I2EN_Pos (6UL)
2493#define I2C0_CONSET_I2EN_Msk (0x40UL)
2494/* ========================================================= STAT ========================================================== */
2495#define I2C0_STAT_Status_Pos (3UL)
2496#define I2C0_STAT_Status_Msk (0xf8UL)
2497/* ========================================================== DAT ========================================================== */
2498#define I2C0_DAT_Data_Pos (0UL)
2499#define I2C0_DAT_Data_Msk (0xffUL)
2500/* ========================================================= ADR0 ========================================================== */
2501#define I2C0_ADR0_GC_Pos (0UL)
2502#define I2C0_ADR0_GC_Msk (0x1UL)
2503#define I2C0_ADR0_Address_Pos (1UL)
2504#define I2C0_ADR0_Address_Msk (0xfeUL)
2505/* ========================================================= SCLH ========================================================== */
2506#define I2C0_SCLH_SCLH_Pos (0UL)
2507#define I2C0_SCLH_SCLH_Msk (0xffffUL)
2508/* ========================================================= SCLL ========================================================== */
2509#define I2C0_SCLL_SCLL_Pos (0UL)
2510#define I2C0_SCLL_SCLL_Msk (0xffffUL)
2511/* ======================================================== CONCLR ========================================================= */
2512#define I2C0_CONCLR_AAC_Pos (2UL)
2513#define I2C0_CONCLR_AAC_Msk (0x4UL)
2514#define I2C0_CONCLR_SIC_Pos (3UL)
2515#define I2C0_CONCLR_SIC_Msk (0x8UL)
2516#define I2C0_CONCLR_STAC_Pos (5UL)
2517#define I2C0_CONCLR_STAC_Msk (0x20UL)
2518#define I2C0_CONCLR_I2ENC_Pos (6UL)
2519#define I2C0_CONCLR_I2ENC_Msk (0x40UL)
2520/* ======================================================== MMCTRL ========================================================= */
2521#define I2C0_MMCTRL_MM_ENA_Pos (0UL)
2522#define I2C0_MMCTRL_MM_ENA_Msk (0x1UL)
2523#define I2C0_MMCTRL_ENA_SCL_Pos (1UL)
2524#define I2C0_MMCTRL_ENA_SCL_Msk (0x2UL)
2525#define I2C0_MMCTRL_MATCH_ALL_Pos (2UL)
2526#define I2C0_MMCTRL_MATCH_ALL_Msk (0x4UL)
2527/* ========================================================= ADR1 ========================================================== */
2528#define I2C0_ADR1_GC_Pos (0UL)
2529#define I2C0_ADR1_GC_Msk (0x1UL)
2530#define I2C0_ADR1_Address_Pos (1UL)
2531#define I2C0_ADR1_Address_Msk (0xfeUL)
2532/* ========================================================= ADR2 ========================================================== */
2533#define I2C0_ADR2_GC_Pos (0UL)
2534#define I2C0_ADR2_GC_Msk (0x1UL)
2535#define I2C0_ADR2_Address_Pos (1UL)
2536#define I2C0_ADR2_Address_Msk (0xfeUL)
2537/* ========================================================= ADR3 ========================================================== */
2538#define I2C0_ADR3_GC_Pos (0UL)
2539#define I2C0_ADR3_GC_Msk (0x1UL)
2540#define I2C0_ADR3_Address_Pos (1UL)
2541#define I2C0_ADR3_Address_Msk (0xfeUL)
2542/* ====================================================== DATA_BUFFER ====================================================== */
2543#define I2C0_DATA_BUFFER_Data_Pos (0UL)
2544#define I2C0_DATA_BUFFER_Data_Msk (0xffUL)
2547/* =========================================================================================================================== */
2548/* ================ LPC_SPI ================ */
2549/* =========================================================================================================================== */
2550
2551/* ========================================================== CR =========================================================== */
2552#define SPI_CR_BITENABLE_Pos (2UL)
2553#define SPI_CR_BITENABLE_Msk (0x4UL)
2554#define SPI_CR_CPHA_Pos (3UL)
2555#define SPI_CR_CPHA_Msk (0x8UL)
2556#define SPI_CR_CPOL_Pos (4UL)
2557#define SPI_CR_CPOL_Msk (0x10UL)
2558#define SPI_CR_MSTR_Pos (5UL)
2559#define SPI_CR_MSTR_Msk (0x20UL)
2560#define SPI_CR_LSBF_Pos (6UL)
2561#define SPI_CR_LSBF_Msk (0x40UL)
2562#define SPI_CR_SPIE_Pos (7UL)
2563#define SPI_CR_SPIE_Msk (0x80UL)
2564#define SPI_CR_BITS_Pos (8UL)
2565#define SPI_CR_BITS_Msk (0xf00UL)
2566/* ========================================================== SR =========================================================== */
2567#define SPI_SR_ABRT_Pos (3UL)
2568#define SPI_SR_ABRT_Msk (0x8UL)
2569#define SPI_SR_MODF_Pos (4UL)
2570#define SPI_SR_MODF_Msk (0x10UL)
2571#define SPI_SR_ROVR_Pos (5UL)
2572#define SPI_SR_ROVR_Msk (0x20UL)
2573#define SPI_SR_WCOL_Pos (6UL)
2574#define SPI_SR_WCOL_Msk (0x40UL)
2575#define SPI_SR_SPIF_Pos (7UL)
2576#define SPI_SR_SPIF_Msk (0x80UL)
2577/* ========================================================== DR =========================================================== */
2578#define SPI_DR_DATALOW_Pos (0UL)
2579#define SPI_DR_DATALOW_Msk (0xffUL)
2580#define SPI_DR_DATAHIGH_Pos (8UL)
2581#define SPI_DR_DATAHIGH_Msk (0xff00UL)
2582/* ========================================================== CCR ========================================================== */
2583#define SPI_CCR_COUNTER_Pos (0UL)
2584#define SPI_CCR_COUNTER_Msk (0xffUL)
2585/* ========================================================== INT ========================================================== */
2586#define SPI_INT_SPIF_Pos (0UL)
2587#define SPI_INT_SPIF_Msk (0x1UL)
2590/* =========================================================================================================================== */
2591/* ================ LPC_RTC ================ */
2592/* =========================================================================================================================== */
2593
2594/* ========================================================== ILR ========================================================== */
2595#define RTC_ILR_RTCCIF_Pos (0UL)
2596#define RTC_ILR_RTCCIF_Msk (0x1UL)
2597#define RTC_ILR_RTCALF_Pos (1UL)
2598#define RTC_ILR_RTCALF_Msk (0x2UL)
2599/* ========================================================== CCR ========================================================== */
2600#define RTC_CCR_CLKEN_Pos (0UL)
2601#define RTC_CCR_CLKEN_Msk (0x1UL)
2602#define RTC_CCR_CTCRST_Pos (1UL)
2603#define RTC_CCR_CTCRST_Msk (0x2UL)
2604#define RTC_CCR_CCALEN_Pos (4UL)
2605#define RTC_CCR_CCALEN_Msk (0x10UL)
2606/* ========================================================= CIIR ========================================================== */
2607#define RTC_CIIR_IMSEC_Pos (0UL)
2608#define RTC_CIIR_IMSEC_Msk (0x1UL)
2609#define RTC_CIIR_IMMIN_Pos (1UL)
2610#define RTC_CIIR_IMMIN_Msk (0x2UL)
2611#define RTC_CIIR_IMHOUR_Pos (2UL)
2612#define RTC_CIIR_IMHOUR_Msk (0x4UL)
2613#define RTC_CIIR_IMDOM_Pos (3UL)
2614#define RTC_CIIR_IMDOM_Msk (0x8UL)
2615#define RTC_CIIR_IMDOW_Pos (4UL)
2616#define RTC_CIIR_IMDOW_Msk (0x10UL)
2617#define RTC_CIIR_IMDOY_Pos (5UL)
2618#define RTC_CIIR_IMDOY_Msk (0x20UL)
2619#define RTC_CIIR_IMMON_Pos (6UL)
2620#define RTC_CIIR_IMMON_Msk (0x40UL)
2621#define RTC_CIIR_IMYEAR_Pos (7UL)
2622#define RTC_CIIR_IMYEAR_Msk (0x80UL)
2623/* ========================================================== AMR ========================================================== */
2624#define RTC_AMR_AMRSEC_Pos (0UL)
2625#define RTC_AMR_AMRSEC_Msk (0x1UL)
2626#define RTC_AMR_AMRMIN_Pos (1UL)
2627#define RTC_AMR_AMRMIN_Msk (0x2UL)
2628#define RTC_AMR_AMRHOUR_Pos (2UL)
2629#define RTC_AMR_AMRHOUR_Msk (0x4UL)
2630#define RTC_AMR_AMRDOM_Pos (3UL)
2631#define RTC_AMR_AMRDOM_Msk (0x8UL)
2632#define RTC_AMR_AMRDOW_Pos (4UL)
2633#define RTC_AMR_AMRDOW_Msk (0x10UL)
2634#define RTC_AMR_AMRDOY_Pos (5UL)
2635#define RTC_AMR_AMRDOY_Msk (0x20UL)
2636#define RTC_AMR_AMRMON_Pos (6UL)
2637#define RTC_AMR_AMRMON_Msk (0x40UL)
2638#define RTC_AMR_AMRYEAR_Pos (7UL)
2639#define RTC_AMR_AMRYEAR_Msk (0x80UL)
2640/* ======================================================== CTIME0 ========================================================= */
2641#define RTC_CTIME0_SECONDS_Pos (0UL)
2642#define RTC_CTIME0_SECONDS_Msk (0x3fUL)
2643#define RTC_CTIME0_MINUTES_Pos (8UL)
2644#define RTC_CTIME0_MINUTES_Msk (0x3f00UL)
2645#define RTC_CTIME0_HOURS_Pos (16UL)
2646#define RTC_CTIME0_HOURS_Msk (0x1f0000UL)
2647#define RTC_CTIME0_DOW_Pos (24UL)
2648#define RTC_CTIME0_DOW_Msk (0x7000000UL)
2649/* ======================================================== CTIME1 ========================================================= */
2650#define RTC_CTIME1_DOM_Pos (0UL)
2651#define RTC_CTIME1_DOM_Msk (0x1fUL)
2652#define RTC_CTIME1_MONTH_Pos (8UL)
2653#define RTC_CTIME1_MONTH_Msk (0xf00UL)
2654#define RTC_CTIME1_YEAR_Pos (16UL)
2655#define RTC_CTIME1_YEAR_Msk (0xfff0000UL)
2656/* ======================================================== CTIME2 ========================================================= */
2657#define RTC_CTIME2_DOY_Pos (0UL)
2658#define RTC_CTIME2_DOY_Msk (0xfffUL)
2659/* ========================================================== SEC ========================================================== */
2660#define RTC_SEC_SECONDS_Pos (0UL)
2661#define RTC_SEC_SECONDS_Msk (0x3fUL)
2662/* ========================================================== MIN ========================================================== */
2663#define RTC_MIN_MINUTES_Pos (0UL)
2664#define RTC_MIN_MINUTES_Msk (0x3fUL)
2665/* ========================================================== HRS ========================================================== */
2666#define RTC_HRS_HOURS_Pos (0UL)
2667#define RTC_HRS_HOURS_Msk (0x1fUL)
2668/* ========================================================== DOM ========================================================== */
2669#define RTC_DOM_DOM_Pos (0UL)
2670#define RTC_DOM_DOM_Msk (0x1fUL)
2671/* ========================================================== DOW ========================================================== */
2672#define RTC_DOW_DOW_Pos (0UL)
2673#define RTC_DOW_DOW_Msk (0x7UL)
2674/* ========================================================== DOY ========================================================== */
2675#define RTC_DOY_DOY_Pos (0UL)
2676#define RTC_DOY_DOY_Msk (0x1ffUL)
2677/* ========================================================= MONTH ========================================================= */
2678#define RTC_MONTH_MONTH_Pos (0UL)
2679#define RTC_MONTH_MONTH_Msk (0xfUL)
2680/* ========================================================= YEAR ========================================================== */
2681#define RTC_YEAR_YEAR_Pos (0UL)
2682#define RTC_YEAR_YEAR_Msk (0xfffUL)
2683/* ====================================================== CALIBRATION ====================================================== */
2684#define RTC_CALIBRATION_CALVAL_Pos (0UL)
2685#define RTC_CALIBRATION_CALVAL_Msk (0x1ffffUL)
2686#define RTC_CALIBRATION_CALDIR_Pos (17UL)
2687#define RTC_CALIBRATION_CALDIR_Msk (0x20000UL)
2688/* ======================================================== GPREG0 ========================================================= */
2689#define RTC_GPREG0_GP_Pos (0UL)
2690#define RTC_GPREG0_GP_Msk (0xffffffffUL)
2691/* ======================================================== GPREG1 ========================================================= */
2692#define RTC_GPREG1_GP_Pos (0UL)
2693#define RTC_GPREG1_GP_Msk (0xffffffffUL)
2694/* ======================================================== GPREG2 ========================================================= */
2695#define RTC_GPREG2_GP_Pos (0UL)
2696#define RTC_GPREG2_GP_Msk (0xffffffffUL)
2697/* ======================================================== GPREG3 ========================================================= */
2698#define RTC_GPREG3_GP_Pos (0UL)
2699#define RTC_GPREG3_GP_Msk (0xffffffffUL)
2700/* ======================================================== GPREG4 ========================================================= */
2701#define RTC_GPREG4_GP_Pos (0UL)
2702#define RTC_GPREG4_GP_Msk (0xffffffffUL)
2703/* ======================================================== RTC_AUX ======================================================== */
2704#define RTC_RTC_AUX_RTC_OSCF_Pos (4UL)
2705#define RTC_RTC_AUX_RTC_OSCF_Msk (0x10UL)
2706#define RTC_RTC_AUX_RTC_PDOUT_Pos (6UL)
2707#define RTC_RTC_AUX_RTC_PDOUT_Msk (0x40UL)
2708/* ======================================================= RTC_AUXEN ======================================================= */
2709#define RTC_RTC_AUXEN_RTC_OSCFEN_Pos (4UL)
2710#define RTC_RTC_AUXEN_RTC_OSCFEN_Msk (0x10UL)
2711/* ========================================================= ASEC ========================================================== */
2712#define RTC_ASEC_SECONDS_Pos (0UL)
2713#define RTC_ASEC_SECONDS_Msk (0x3fUL)
2714/* ========================================================= AMIN ========================================================== */
2715#define RTC_AMIN_MINUTES_Pos (0UL)
2716#define RTC_AMIN_MINUTES_Msk (0x3fUL)
2717/* ========================================================= AHRS ========================================================== */
2718#define RTC_AHRS_HOURS_Pos (0UL)
2719#define RTC_AHRS_HOURS_Msk (0x1fUL)
2720/* ========================================================= ADOM ========================================================== */
2721#define RTC_ADOM_DOM_Pos (0UL)
2722#define RTC_ADOM_DOM_Msk (0x1fUL)
2723/* ========================================================= ADOW ========================================================== */
2724#define RTC_ADOW_DOW_Pos (0UL)
2725#define RTC_ADOW_DOW_Msk (0x7UL)
2726/* ========================================================= ADOY ========================================================== */
2727#define RTC_ADOY_DOY_Pos (0UL)
2728#define RTC_ADOY_DOY_Msk (0x1ffUL)
2729/* ========================================================= AMON ========================================================== */
2730#define RTC_AMON_MONTH_Pos (0UL)
2731#define RTC_AMON_MONTH_Msk (0xfUL)
2732/* ========================================================= AYRS ========================================================== */
2733#define RTC_AYRS_YEAR_Pos (0UL)
2734#define RTC_AYRS_YEAR_Msk (0xfffUL)
2737/* =========================================================================================================================== */
2738/* ================ LPC_GPIOINT ================ */
2739/* =========================================================================================================================== */
2740
2741/* ======================================================== STATUS ========================================================= */
2742#define GPIOINT_STATUS_P0INT_Pos (0UL)
2743#define GPIOINT_STATUS_P0INT_Msk (0x1UL)
2744#define GPIOINT_STATUS_P2INT_Pos (2UL)
2745#define GPIOINT_STATUS_P2INT_Msk (0x4UL)
2746/* ======================================================== STATR0 ========================================================= */
2747#define GPIOINT_STATR0_P0_0REI_Pos (0UL)
2748#define GPIOINT_STATR0_P0_0REI_Msk (0x1UL)
2749#define GPIOINT_STATR0_P0_1REI_Pos (1UL)
2750#define GPIOINT_STATR0_P0_1REI_Msk (0x2UL)
2751#define GPIOINT_STATR0_P0_2REI_Pos (2UL)
2752#define GPIOINT_STATR0_P0_2REI_Msk (0x4UL)
2753#define GPIOINT_STATR0_P0_3REI_Pos (3UL)
2754#define GPIOINT_STATR0_P0_3REI_Msk (0x8UL)
2755#define GPIOINT_STATR0_P0_4REI_Pos (4UL)
2756#define GPIOINT_STATR0_P0_4REI_Msk (0x10UL)
2757#define GPIOINT_STATR0_P0_5REI_Pos (5UL)
2758#define GPIOINT_STATR0_P0_5REI_Msk (0x20UL)
2759#define GPIOINT_STATR0_P0_6REI_Pos (6UL)
2760#define GPIOINT_STATR0_P0_6REI_Msk (0x40UL)
2761#define GPIOINT_STATR0_P0_7REI_Pos (7UL)
2762#define GPIOINT_STATR0_P0_7REI_Msk (0x80UL)
2763#define GPIOINT_STATR0_P0_8REI_Pos (8UL)
2764#define GPIOINT_STATR0_P0_8REI_Msk (0x100UL)
2765#define GPIOINT_STATR0_P0_9REI_Pos (9UL)
2766#define GPIOINT_STATR0_P0_9REI_Msk (0x200UL)
2767#define GPIOINT_STATR0_P0_10REI_Pos (10UL)
2768#define GPIOINT_STATR0_P0_10REI_Msk (0x400UL)
2769#define GPIOINT_STATR0_P0_11REI_Pos (11UL)
2770#define GPIOINT_STATR0_P0_11REI_Msk (0x800UL)
2771#define GPIOINT_STATR0_P0_12REI_Pos (12UL)
2772#define GPIOINT_STATR0_P0_12REI_Msk (0x1000UL)
2773#define GPIOINT_STATR0_P0_13REI_Pos (13UL)
2774#define GPIOINT_STATR0_P0_13REI_Msk (0x2000UL)
2775#define GPIOINT_STATR0_P0_14REI_Pos (14UL)
2776#define GPIOINT_STATR0_P0_14REI_Msk (0x4000UL)
2777#define GPIOINT_STATR0_P0_15REI_Pos (15UL)
2778#define GPIOINT_STATR0_P0_15REI_Msk (0x8000UL)
2779#define GPIOINT_STATR0_P0_16REI_Pos (16UL)
2780#define GPIOINT_STATR0_P0_16REI_Msk (0x10000UL)
2781#define GPIOINT_STATR0_P0_17REI_Pos (17UL)
2782#define GPIOINT_STATR0_P0_17REI_Msk (0x20000UL)
2783#define GPIOINT_STATR0_P0_18REI_Pos (18UL)
2784#define GPIOINT_STATR0_P0_18REI_Msk (0x40000UL)
2785#define GPIOINT_STATR0_P0_19REI_Pos (19UL)
2786#define GPIOINT_STATR0_P0_19REI_Msk (0x80000UL)
2787#define GPIOINT_STATR0_P0_20REI_Pos (20UL)
2788#define GPIOINT_STATR0_P0_20REI_Msk (0x100000UL)
2789#define GPIOINT_STATR0_P0_21REI_Pos (21UL)
2790#define GPIOINT_STATR0_P0_21REI_Msk (0x200000UL)
2791#define GPIOINT_STATR0_P0_22REI_Pos (22UL)
2792#define GPIOINT_STATR0_P0_22REI_Msk (0x400000UL)
2793#define GPIOINT_STATR0_P0_23REI_Pos (23UL)
2794#define GPIOINT_STATR0_P0_23REI_Msk (0x800000UL)
2795#define GPIOINT_STATR0_P0_24REI_Pos (24UL)
2796#define GPIOINT_STATR0_P0_24REI_Msk (0x1000000UL)
2797#define GPIOINT_STATR0_P0_25REI_Pos (25UL)
2798#define GPIOINT_STATR0_P0_25REI_Msk (0x2000000UL)
2799#define GPIOINT_STATR0_P0_26REI_Pos (26UL)
2800#define GPIOINT_STATR0_P0_26REI_Msk (0x4000000UL)
2801#define GPIOINT_STATR0_P0_27REI_Pos (27UL)
2802#define GPIOINT_STATR0_P0_27REI_Msk (0x8000000UL)
2803#define GPIOINT_STATR0_P0_28REI_Pos (28UL)
2804#define GPIOINT_STATR0_P0_28REI_Msk (0x10000000UL)
2805#define GPIOINT_STATR0_P0_29REI_Pos (29UL)
2806#define GPIOINT_STATR0_P0_29REI_Msk (0x20000000UL)
2807#define GPIOINT_STATR0_P0_30REI_Pos (30UL)
2808#define GPIOINT_STATR0_P0_30REI_Msk (0x40000000UL)
2809/* ======================================================== STATF0 ========================================================= */
2810#define GPIOINT_STATF0_P0_0FEI_Pos (0UL)
2811#define GPIOINT_STATF0_P0_0FEI_Msk (0x1UL)
2812#define GPIOINT_STATF0_P0_1FEI_Pos (1UL)
2813#define GPIOINT_STATF0_P0_1FEI_Msk (0x2UL)
2814#define GPIOINT_STATF0_P0_2FEI_Pos (2UL)
2815#define GPIOINT_STATF0_P0_2FEI_Msk (0x4UL)
2816#define GPIOINT_STATF0_P0_3FEI_Pos (3UL)
2817#define GPIOINT_STATF0_P0_3FEI_Msk (0x8UL)
2818#define GPIOINT_STATF0_P0_4FEI_Pos (4UL)
2819#define GPIOINT_STATF0_P0_4FEI_Msk (0x10UL)
2820#define GPIOINT_STATF0_P0_5FEI_Pos (5UL)
2821#define GPIOINT_STATF0_P0_5FEI_Msk (0x20UL)
2822#define GPIOINT_STATF0_P0_6FEI_Pos (6UL)
2823#define GPIOINT_STATF0_P0_6FEI_Msk (0x40UL)
2824#define GPIOINT_STATF0_P0_7FEI_Pos (7UL)
2825#define GPIOINT_STATF0_P0_7FEI_Msk (0x80UL)
2826#define GPIOINT_STATF0_P0_8FEI_Pos (8UL)
2827#define GPIOINT_STATF0_P0_8FEI_Msk (0x100UL)
2828#define GPIOINT_STATF0_P0_9FEI_Pos (9UL)
2829#define GPIOINT_STATF0_P0_9FEI_Msk (0x200UL)
2830#define GPIOINT_STATF0_P0_10FEI_Pos (10UL)
2831#define GPIOINT_STATF0_P0_10FEI_Msk (0x400UL)
2832#define GPIOINT_STATF0_P0_11FEI_Pos (11UL)
2833#define GPIOINT_STATF0_P0_11FEI_Msk (0x800UL)
2834#define GPIOINT_STATF0_P0_12FEI_Pos (12UL)
2835#define GPIOINT_STATF0_P0_12FEI_Msk (0x1000UL)
2836#define GPIOINT_STATF0_P0_13FEI_Pos (13UL)
2837#define GPIOINT_STATF0_P0_13FEI_Msk (0x2000UL)
2838#define GPIOINT_STATF0_P0_14FEI_Pos (14UL)
2839#define GPIOINT_STATF0_P0_14FEI_Msk (0x4000UL)
2840#define GPIOINT_STATF0_P0_15FEI_Pos (15UL)
2841#define GPIOINT_STATF0_P0_15FEI_Msk (0x8000UL)
2842#define GPIOINT_STATF0_P0_16FEI_Pos (16UL)
2843#define GPIOINT_STATF0_P0_16FEI_Msk (0x10000UL)
2844#define GPIOINT_STATF0_P0_17FEI_Pos (17UL)
2845#define GPIOINT_STATF0_P0_17FEI_Msk (0x20000UL)
2846#define GPIOINT_STATF0_P0_18FEI_Pos (18UL)
2847#define GPIOINT_STATF0_P0_18FEI_Msk (0x40000UL)
2848#define GPIOINT_STATF0_P0_19FEI_Pos (19UL)
2849#define GPIOINT_STATF0_P0_19FEI_Msk (0x80000UL)
2850#define GPIOINT_STATF0_P0_20FEI_Pos (20UL)
2851#define GPIOINT_STATF0_P0_20FEI_Msk (0x100000UL)
2852#define GPIOINT_STATF0_P0_21FEI_Pos (21UL)
2853#define GPIOINT_STATF0_P0_21FEI_Msk (0x200000UL)
2854#define GPIOINT_STATF0_P0_22FEI_Pos (22UL)
2855#define GPIOINT_STATF0_P0_22FEI_Msk (0x400000UL)
2856#define GPIOINT_STATF0_P0_23FEI_Pos (23UL)
2857#define GPIOINT_STATF0_P0_23FEI_Msk (0x800000UL)
2858#define GPIOINT_STATF0_P0_24FEI_Pos (24UL)
2859#define GPIOINT_STATF0_P0_24FEI_Msk (0x1000000UL)
2860#define GPIOINT_STATF0_P0_25FEI_Pos (25UL)
2861#define GPIOINT_STATF0_P0_25FEI_Msk (0x2000000UL)
2862#define GPIOINT_STATF0_P0_26FEI_Pos (26UL)
2863#define GPIOINT_STATF0_P0_26FEI_Msk (0x4000000UL)
2864#define GPIOINT_STATF0_P0_27FEI_Pos (27UL)
2865#define GPIOINT_STATF0_P0_27FEI_Msk (0x8000000UL)
2866#define GPIOINT_STATF0_P0_28FEI_Pos (28UL)
2867#define GPIOINT_STATF0_P0_28FEI_Msk (0x10000000UL)
2868#define GPIOINT_STATF0_P0_29FEI_Pos (29UL)
2869#define GPIOINT_STATF0_P0_29FEI_Msk (0x20000000UL)
2870#define GPIOINT_STATF0_P0_30FEI_Pos (30UL)
2871#define GPIOINT_STATF0_P0_30FEI_Msk (0x40000000UL)
2872/* ========================================================= CLR0 ========================================================== */
2873#define GPIOINT_CLR0_P0_0CI_Pos (0UL)
2874#define GPIOINT_CLR0_P0_0CI_Msk (0x1UL)
2875#define GPIOINT_CLR0_P0_1CI_Pos (1UL)
2876#define GPIOINT_CLR0_P0_1CI_Msk (0x2UL)
2877#define GPIOINT_CLR0_P0_2CI_Pos (2UL)
2878#define GPIOINT_CLR0_P0_2CI_Msk (0x4UL)
2879#define GPIOINT_CLR0_P0_3CI_Pos (3UL)
2880#define GPIOINT_CLR0_P0_3CI_Msk (0x8UL)
2881#define GPIOINT_CLR0_P0_4CI_Pos (4UL)
2882#define GPIOINT_CLR0_P0_4CI_Msk (0x10UL)
2883#define GPIOINT_CLR0_P0_5CI_Pos (5UL)
2884#define GPIOINT_CLR0_P0_5CI_Msk (0x20UL)
2885#define GPIOINT_CLR0_P0_6CI_Pos (6UL)
2886#define GPIOINT_CLR0_P0_6CI_Msk (0x40UL)
2887#define GPIOINT_CLR0_P0_7CI_Pos (7UL)
2888#define GPIOINT_CLR0_P0_7CI_Msk (0x80UL)
2889#define GPIOINT_CLR0_P0_8CI_Pos (8UL)
2890#define GPIOINT_CLR0_P0_8CI_Msk (0x100UL)
2891#define GPIOINT_CLR0_P0_9CI_Pos (9UL)
2892#define GPIOINT_CLR0_P0_9CI_Msk (0x200UL)
2893#define GPIOINT_CLR0_P0_10CI_Pos (10UL)
2894#define GPIOINT_CLR0_P0_10CI_Msk (0x400UL)
2895#define GPIOINT_CLR0_P0_11CI_Pos (11UL)
2896#define GPIOINT_CLR0_P0_11CI_Msk (0x800UL)
2897#define GPIOINT_CLR0_P0_12CI_Pos (12UL)
2898#define GPIOINT_CLR0_P0_12CI_Msk (0x1000UL)
2899#define GPIOINT_CLR0_P0_13CI_Pos (13UL)
2900#define GPIOINT_CLR0_P0_13CI_Msk (0x2000UL)
2901#define GPIOINT_CLR0_P0_14CI_Pos (14UL)
2902#define GPIOINT_CLR0_P0_14CI_Msk (0x4000UL)
2903#define GPIOINT_CLR0_P0_15CI_Pos (15UL)
2904#define GPIOINT_CLR0_P0_15CI_Msk (0x8000UL)
2905#define GPIOINT_CLR0_P0_16CI_Pos (16UL)
2906#define GPIOINT_CLR0_P0_16CI_Msk (0x10000UL)
2907#define GPIOINT_CLR0_P0_17CI_Pos (17UL)
2908#define GPIOINT_CLR0_P0_17CI_Msk (0x20000UL)
2909#define GPIOINT_CLR0_P0_18CI_Pos (18UL)
2910#define GPIOINT_CLR0_P0_18CI_Msk (0x40000UL)
2911#define GPIOINT_CLR0_P0_19CI_Pos (19UL)
2912#define GPIOINT_CLR0_P0_19CI_Msk (0x80000UL)
2913#define GPIOINT_CLR0_P0_20CI_Pos (20UL)
2914#define GPIOINT_CLR0_P0_20CI_Msk (0x100000UL)
2915#define GPIOINT_CLR0_P0_21CI_Pos (21UL)
2916#define GPIOINT_CLR0_P0_21CI_Msk (0x200000UL)
2917#define GPIOINT_CLR0_P0_22CI_Pos (22UL)
2918#define GPIOINT_CLR0_P0_22CI_Msk (0x400000UL)
2919#define GPIOINT_CLR0_P0_23CI_Pos (23UL)
2920#define GPIOINT_CLR0_P0_23CI_Msk (0x800000UL)
2921#define GPIOINT_CLR0_P0_24CI_Pos (24UL)
2922#define GPIOINT_CLR0_P0_24CI_Msk (0x1000000UL)
2923#define GPIOINT_CLR0_P0_25CI_Pos (25UL)
2924#define GPIOINT_CLR0_P0_25CI_Msk (0x2000000UL)
2925#define GPIOINT_CLR0_P0_26CI_Pos (26UL)
2926#define GPIOINT_CLR0_P0_26CI_Msk (0x4000000UL)
2927#define GPIOINT_CLR0_P0_27CI_Pos (27UL)
2928#define GPIOINT_CLR0_P0_27CI_Msk (0x8000000UL)
2929#define GPIOINT_CLR0_P0_28CI_Pos (28UL)
2930#define GPIOINT_CLR0_P0_28CI_Msk (0x10000000UL)
2931#define GPIOINT_CLR0_P0_29CI_Pos (29UL)
2932#define GPIOINT_CLR0_P0_29CI_Msk (0x20000000UL)
2933#define GPIOINT_CLR0_P0_30CI_Pos (30UL)
2934#define GPIOINT_CLR0_P0_30CI_Msk (0x40000000UL)
2935/* ========================================================= ENR0 ========================================================== */
2936#define GPIOINT_ENR0_P0_0ER_Pos (0UL)
2937#define GPIOINT_ENR0_P0_0ER_Msk (0x1UL)
2938#define GPIOINT_ENR0_P0_1ER_Pos (1UL)
2939#define GPIOINT_ENR0_P0_1ER_Msk (0x2UL)
2940#define GPIOINT_ENR0_P0_2ER_Pos (2UL)
2941#define GPIOINT_ENR0_P0_2ER_Msk (0x4UL)
2942#define GPIOINT_ENR0_P0_3ER_Pos (3UL)
2943#define GPIOINT_ENR0_P0_3ER_Msk (0x8UL)
2944#define GPIOINT_ENR0_P0_4ER_Pos (4UL)
2945#define GPIOINT_ENR0_P0_4ER_Msk (0x10UL)
2946#define GPIOINT_ENR0_P0_5ER_Pos (5UL)
2947#define GPIOINT_ENR0_P0_5ER_Msk (0x20UL)
2948#define GPIOINT_ENR0_P0_6ER_Pos (6UL)
2949#define GPIOINT_ENR0_P0_6ER_Msk (0x40UL)
2950#define GPIOINT_ENR0_P0_7ER_Pos (7UL)
2951#define GPIOINT_ENR0_P0_7ER_Msk (0x80UL)
2952#define GPIOINT_ENR0_P0_8ER_Pos (8UL)
2953#define GPIOINT_ENR0_P0_8ER_Msk (0x100UL)
2954#define GPIOINT_ENR0_P0_9ER_Pos (9UL)
2955#define GPIOINT_ENR0_P0_9ER_Msk (0x200UL)
2956#define GPIOINT_ENR0_P0_10ER_Pos (10UL)
2957#define GPIOINT_ENR0_P0_10ER_Msk (0x400UL)
2958#define GPIOINT_ENR0_P0_11ER_Pos (11UL)
2959#define GPIOINT_ENR0_P0_11ER_Msk (0x800UL)
2960#define GPIOINT_ENR0_P0_12ER_Pos (12UL)
2961#define GPIOINT_ENR0_P0_12ER_Msk (0x1000UL)
2962#define GPIOINT_ENR0_P0_13ER_Pos (13UL)
2963#define GPIOINT_ENR0_P0_13ER_Msk (0x2000UL)
2964#define GPIOINT_ENR0_P0_14ER_Pos (14UL)
2965#define GPIOINT_ENR0_P0_14ER_Msk (0x4000UL)
2966#define GPIOINT_ENR0_P0_15ER_Pos (15UL)
2967#define GPIOINT_ENR0_P0_15ER_Msk (0x8000UL)
2968#define GPIOINT_ENR0_P0_16ER_Pos (16UL)
2969#define GPIOINT_ENR0_P0_16ER_Msk (0x10000UL)
2970#define GPIOINT_ENR0_P0_17ER_Pos (17UL)
2971#define GPIOINT_ENR0_P0_17ER_Msk (0x20000UL)
2972#define GPIOINT_ENR0_P0_18ER_Pos (18UL)
2973#define GPIOINT_ENR0_P0_18ER_Msk (0x40000UL)
2974#define GPIOINT_ENR0_P0_19ER_Pos (19UL)
2975#define GPIOINT_ENR0_P0_19ER_Msk (0x80000UL)
2976#define GPIOINT_ENR0_P0_20ER_Pos (20UL)
2977#define GPIOINT_ENR0_P0_20ER_Msk (0x100000UL)
2978#define GPIOINT_ENR0_P0_21ER_Pos (21UL)
2979#define GPIOINT_ENR0_P0_21ER_Msk (0x200000UL)
2980#define GPIOINT_ENR0_P0_22ER_Pos (22UL)
2981#define GPIOINT_ENR0_P0_22ER_Msk (0x400000UL)
2982#define GPIOINT_ENR0_P0_23ER_Pos (23UL)
2983#define GPIOINT_ENR0_P0_23ER_Msk (0x800000UL)
2984#define GPIOINT_ENR0_P0_24ER_Pos (24UL)
2985#define GPIOINT_ENR0_P0_24ER_Msk (0x1000000UL)
2986#define GPIOINT_ENR0_P0_25ER_Pos (25UL)
2987#define GPIOINT_ENR0_P0_25ER_Msk (0x2000000UL)
2988#define GPIOINT_ENR0_P0_26ER_Pos (26UL)
2989#define GPIOINT_ENR0_P0_26ER_Msk (0x4000000UL)
2990#define GPIOINT_ENR0_P0_27ER_Pos (27UL)
2991#define GPIOINT_ENR0_P0_27ER_Msk (0x8000000UL)
2992#define GPIOINT_ENR0_P0_28ER_Pos (28UL)
2993#define GPIOINT_ENR0_P0_28ER_Msk (0x10000000UL)
2994#define GPIOINT_ENR0_P0_29ER_Pos (29UL)
2995#define GPIOINT_ENR0_P0_29ER_Msk (0x20000000UL)
2996#define GPIOINT_ENR0_P0_30ER_Pos (30UL)
2997#define GPIOINT_ENR0_P0_30ER_Msk (0x40000000UL)
2998/* ========================================================= ENF0 ========================================================== */
2999#define GPIOINT_ENF0_P0_0EF_Pos (0UL)
3000#define GPIOINT_ENF0_P0_0EF_Msk (0x1UL)
3001#define GPIOINT_ENF0_P0_1EF_Pos (1UL)
3002#define GPIOINT_ENF0_P0_1EF_Msk (0x2UL)
3003#define GPIOINT_ENF0_P0_2EF_Pos (2UL)
3004#define GPIOINT_ENF0_P0_2EF_Msk (0x4UL)
3005#define GPIOINT_ENF0_P0_3EF_Pos (3UL)
3006#define GPIOINT_ENF0_P0_3EF_Msk (0x8UL)
3007#define GPIOINT_ENF0_P0_4EF_Pos (4UL)
3008#define GPIOINT_ENF0_P0_4EF_Msk (0x10UL)
3009#define GPIOINT_ENF0_P0_5EF_Pos (5UL)
3010#define GPIOINT_ENF0_P0_5EF_Msk (0x20UL)
3011#define GPIOINT_ENF0_P0_6EF_Pos (6UL)
3012#define GPIOINT_ENF0_P0_6EF_Msk (0x40UL)
3013#define GPIOINT_ENF0_P0_7EF_Pos (7UL)
3014#define GPIOINT_ENF0_P0_7EF_Msk (0x80UL)
3015#define GPIOINT_ENF0_P0_8EF_Pos (8UL)
3016#define GPIOINT_ENF0_P0_8EF_Msk (0x100UL)
3017#define GPIOINT_ENF0_P0_9EF_Pos (9UL)
3018#define GPIOINT_ENF0_P0_9EF_Msk (0x200UL)
3019#define GPIOINT_ENF0_P0_10EF_Pos (10UL)
3020#define GPIOINT_ENF0_P0_10EF_Msk (0x400UL)
3021#define GPIOINT_ENF0_P0_11EF_Pos (11UL)
3022#define GPIOINT_ENF0_P0_11EF_Msk (0x800UL)
3023#define GPIOINT_ENF0_P0_12EF_Pos (12UL)
3024#define GPIOINT_ENF0_P0_12EF_Msk (0x1000UL)
3025#define GPIOINT_ENF0_P0_13EF_Pos (13UL)
3026#define GPIOINT_ENF0_P0_13EF_Msk (0x2000UL)
3027#define GPIOINT_ENF0_P0_14EF_Pos (14UL)
3028#define GPIOINT_ENF0_P0_14EF_Msk (0x4000UL)
3029#define GPIOINT_ENF0_P0_15EF_Pos (15UL)
3030#define GPIOINT_ENF0_P0_15EF_Msk (0x8000UL)
3031#define GPIOINT_ENF0_P0_16EF_Pos (16UL)
3032#define GPIOINT_ENF0_P0_16EF_Msk (0x10000UL)
3033#define GPIOINT_ENF0_P0_17EF_Pos (17UL)
3034#define GPIOINT_ENF0_P0_17EF_Msk (0x20000UL)
3035#define GPIOINT_ENF0_P0_18EF_Pos (18UL)
3036#define GPIOINT_ENF0_P0_18EF_Msk (0x40000UL)
3037#define GPIOINT_ENF0_P0_19EF_Pos (19UL)
3038#define GPIOINT_ENF0_P0_19EF_Msk (0x80000UL)
3039#define GPIOINT_ENF0_P0_20EF_Pos (20UL)
3040#define GPIOINT_ENF0_P0_20EF_Msk (0x100000UL)
3041#define GPIOINT_ENF0_P0_21EF_Pos (21UL)
3042#define GPIOINT_ENF0_P0_21EF_Msk (0x200000UL)
3043#define GPIOINT_ENF0_P0_22EF_Pos (22UL)
3044#define GPIOINT_ENF0_P0_22EF_Msk (0x400000UL)
3045#define GPIOINT_ENF0_P0_23EF_Pos (23UL)
3046#define GPIOINT_ENF0_P0_23EF_Msk (0x800000UL)
3047#define GPIOINT_ENF0_P0_24EF_Pos (24UL)
3048#define GPIOINT_ENF0_P0_24EF_Msk (0x1000000UL)
3049#define GPIOINT_ENF0_P0_25EF_Pos (25UL)
3050#define GPIOINT_ENF0_P0_25EF_Msk (0x2000000UL)
3051#define GPIOINT_ENF0_P0_26EF_Pos (26UL)
3052#define GPIOINT_ENF0_P0_26EF_Msk (0x4000000UL)
3053#define GPIOINT_ENF0_P0_27EF_Pos (27UL)
3054#define GPIOINT_ENF0_P0_27EF_Msk (0x8000000UL)
3055#define GPIOINT_ENF0_P0_28EF_Pos (28UL)
3056#define GPIOINT_ENF0_P0_28EF_Msk (0x10000000UL)
3057#define GPIOINT_ENF0_P0_29EF_Pos (29UL)
3058#define GPIOINT_ENF0_P0_29EF_Msk (0x20000000UL)
3059#define GPIOINT_ENF0_P0_30EF_Pos (30UL)
3060#define GPIOINT_ENF0_P0_30EF_Msk (0x40000000UL)
3061/* ======================================================== STATR2 ========================================================= */
3062#define GPIOINT_STATR2_P2_0REI_Pos (0UL)
3063#define GPIOINT_STATR2_P2_0REI_Msk (0x1UL)
3064#define GPIOINT_STATR2_P2_1REI_Pos (1UL)
3065#define GPIOINT_STATR2_P2_1REI_Msk (0x2UL)
3066#define GPIOINT_STATR2_P2_2REI_Pos (2UL)
3067#define GPIOINT_STATR2_P2_2REI_Msk (0x4UL)
3068#define GPIOINT_STATR2_P2_3REI_Pos (3UL)
3069#define GPIOINT_STATR2_P2_3REI_Msk (0x8UL)
3070#define GPIOINT_STATR2_P2_4REI_Pos (4UL)
3071#define GPIOINT_STATR2_P2_4REI_Msk (0x10UL)
3072#define GPIOINT_STATR2_P2_5REI_Pos (5UL)
3073#define GPIOINT_STATR2_P2_5REI_Msk (0x20UL)
3074#define GPIOINT_STATR2_P2_6REI_Pos (6UL)
3075#define GPIOINT_STATR2_P2_6REI_Msk (0x40UL)
3076#define GPIOINT_STATR2_P2_7REI_Pos (7UL)
3077#define GPIOINT_STATR2_P2_7REI_Msk (0x80UL)
3078#define GPIOINT_STATR2_P2_8REI_Pos (8UL)
3079#define GPIOINT_STATR2_P2_8REI_Msk (0x100UL)
3080#define GPIOINT_STATR2_P2_9REI_Pos (9UL)
3081#define GPIOINT_STATR2_P2_9REI_Msk (0x200UL)
3082#define GPIOINT_STATR2_P2_10REI_Pos (10UL)
3083#define GPIOINT_STATR2_P2_10REI_Msk (0x400UL)
3084#define GPIOINT_STATR2_P2_11REI_Pos (11UL)
3085#define GPIOINT_STATR2_P2_11REI_Msk (0x800UL)
3086#define GPIOINT_STATR2_P2_12REI_Pos (12UL)
3087#define GPIOINT_STATR2_P2_12REI_Msk (0x1000UL)
3088#define GPIOINT_STATR2_P2_13REI_Pos (13UL)
3089#define GPIOINT_STATR2_P2_13REI_Msk (0x2000UL)
3090/* ======================================================== STATF2 ========================================================= */
3091#define GPIOINT_STATF2_P2_0FEI_Pos (0UL)
3092#define GPIOINT_STATF2_P2_0FEI_Msk (0x1UL)
3093#define GPIOINT_STATF2_P2_1FEI_Pos (1UL)
3094#define GPIOINT_STATF2_P2_1FEI_Msk (0x2UL)
3095#define GPIOINT_STATF2_P2_2FEI_Pos (2UL)
3096#define GPIOINT_STATF2_P2_2FEI_Msk (0x4UL)
3097#define GPIOINT_STATF2_P2_3FEI_Pos (3UL)
3098#define GPIOINT_STATF2_P2_3FEI_Msk (0x8UL)
3099#define GPIOINT_STATF2_P2_4FEI_Pos (4UL)
3100#define GPIOINT_STATF2_P2_4FEI_Msk (0x10UL)
3101#define GPIOINT_STATF2_P2_5FEI_Pos (5UL)
3102#define GPIOINT_STATF2_P2_5FEI_Msk (0x20UL)
3103#define GPIOINT_STATF2_P2_6FEI_Pos (6UL)
3104#define GPIOINT_STATF2_P2_6FEI_Msk (0x40UL)
3105#define GPIOINT_STATF2_P2_7FEI_Pos (7UL)
3106#define GPIOINT_STATF2_P2_7FEI_Msk (0x80UL)
3107#define GPIOINT_STATF2_P2_8FEI_Pos (8UL)
3108#define GPIOINT_STATF2_P2_8FEI_Msk (0x100UL)
3109#define GPIOINT_STATF2_P2_9FEI_Pos (9UL)
3110#define GPIOINT_STATF2_P2_9FEI_Msk (0x200UL)
3111#define GPIOINT_STATF2_P2_10FEI_Pos (10UL)
3112#define GPIOINT_STATF2_P2_10FEI_Msk (0x400UL)
3113#define GPIOINT_STATF2_P2_11FEI_Pos (11UL)
3114#define GPIOINT_STATF2_P2_11FEI_Msk (0x800UL)
3115#define GPIOINT_STATF2_P2_12FEI_Pos (12UL)
3116#define GPIOINT_STATF2_P2_12FEI_Msk (0x1000UL)
3117#define GPIOINT_STATF2_P2_13FEI_Pos (13UL)
3118#define GPIOINT_STATF2_P2_13FEI_Msk (0x2000UL)
3119/* ========================================================= CLR2 ========================================================== */
3120#define GPIOINT_CLR2_P2_0CI_Pos (0UL)
3121#define GPIOINT_CLR2_P2_0CI_Msk (0x1UL)
3122#define GPIOINT_CLR2_P2_1CI_Pos (1UL)
3123#define GPIOINT_CLR2_P2_1CI_Msk (0x2UL)
3124#define GPIOINT_CLR2_P2_2CI_Pos (2UL)
3125#define GPIOINT_CLR2_P2_2CI_Msk (0x4UL)
3126#define GPIOINT_CLR2_P2_3CI_Pos (3UL)
3127#define GPIOINT_CLR2_P2_3CI_Msk (0x8UL)
3128#define GPIOINT_CLR2_P2_4CI_Pos (4UL)
3129#define GPIOINT_CLR2_P2_4CI_Msk (0x10UL)
3130#define GPIOINT_CLR2_P2_5CI_Pos (5UL)
3131#define GPIOINT_CLR2_P2_5CI_Msk (0x20UL)
3132#define GPIOINT_CLR2_P2_6CI_Pos (6UL)
3133#define GPIOINT_CLR2_P2_6CI_Msk (0x40UL)
3134#define GPIOINT_CLR2_P2_7CI_Pos (7UL)
3135#define GPIOINT_CLR2_P2_7CI_Msk (0x80UL)
3136#define GPIOINT_CLR2_P2_8CI_Pos (8UL)
3137#define GPIOINT_CLR2_P2_8CI_Msk (0x100UL)
3138#define GPIOINT_CLR2_P2_9CI_Pos (9UL)
3139#define GPIOINT_CLR2_P2_9CI_Msk (0x200UL)
3140#define GPIOINT_CLR2_P2_10CI_Pos (10UL)
3141#define GPIOINT_CLR2_P2_10CI_Msk (0x400UL)
3142#define GPIOINT_CLR2_P2_11CI_Pos (11UL)
3143#define GPIOINT_CLR2_P2_11CI_Msk (0x800UL)
3144#define GPIOINT_CLR2_P2_12CI_Pos (12UL)
3145#define GPIOINT_CLR2_P2_12CI_Msk (0x1000UL)
3146#define GPIOINT_CLR2_P2_13CI_Pos (13UL)
3147#define GPIOINT_CLR2_P2_13CI_Msk (0x2000UL)
3148/* ========================================================= ENR2 ========================================================== */
3149#define GPIOINT_ENR2_P2_0ER_Pos (0UL)
3150#define GPIOINT_ENR2_P2_0ER_Msk (0x1UL)
3151#define GPIOINT_ENR2_P2_1ER_Pos (1UL)
3152#define GPIOINT_ENR2_P2_1ER_Msk (0x2UL)
3153#define GPIOINT_ENR2_P2_2ER_Pos (2UL)
3154#define GPIOINT_ENR2_P2_2ER_Msk (0x4UL)
3155#define GPIOINT_ENR2_P2_3ER_Pos (3UL)
3156#define GPIOINT_ENR2_P2_3ER_Msk (0x8UL)
3157#define GPIOINT_ENR2_P2_4ER_Pos (4UL)
3158#define GPIOINT_ENR2_P2_4ER_Msk (0x10UL)
3159#define GPIOINT_ENR2_P2_5ER_Pos (5UL)
3160#define GPIOINT_ENR2_P2_5ER_Msk (0x20UL)
3161#define GPIOINT_ENR2_P2_6ER_Pos (6UL)
3162#define GPIOINT_ENR2_P2_6ER_Msk (0x40UL)
3163#define GPIOINT_ENR2_P2_7ER_Pos (7UL)
3164#define GPIOINT_ENR2_P2_7ER_Msk (0x80UL)
3165#define GPIOINT_ENR2_P2_8ER_Pos (8UL)
3166#define GPIOINT_ENR2_P2_8ER_Msk (0x100UL)
3167#define GPIOINT_ENR2_P2_9ER_Pos (9UL)
3168#define GPIOINT_ENR2_P2_9ER_Msk (0x200UL)
3169#define GPIOINT_ENR2_P2_10ER_Pos (10UL)
3170#define GPIOINT_ENR2_P2_10ER_Msk (0x400UL)
3171#define GPIOINT_ENR2_P2_11ER_Pos (11UL)
3172#define GPIOINT_ENR2_P2_11ER_Msk (0x800UL)
3173#define GPIOINT_ENR2_P2_12ER_Pos (12UL)
3174#define GPIOINT_ENR2_P2_12ER_Msk (0x1000UL)
3175#define GPIOINT_ENR2_P2_13ER_Pos (13UL)
3176#define GPIOINT_ENR2_P2_13ER_Msk (0x2000UL)
3177/* ========================================================= ENF2 ========================================================== */
3178#define GPIOINT_ENF2_P2_0EF_Pos (0UL)
3179#define GPIOINT_ENF2_P2_0EF_Msk (0x1UL)
3180#define GPIOINT_ENF2_P2_1EF_Pos (1UL)
3181#define GPIOINT_ENF2_P2_1EF_Msk (0x2UL)
3182#define GPIOINT_ENF2_P2_2EF_Pos (2UL)
3183#define GPIOINT_ENF2_P2_2EF_Msk (0x4UL)
3184#define GPIOINT_ENF2_P2_3EF_Pos (3UL)
3185#define GPIOINT_ENF2_P2_3EF_Msk (0x8UL)
3186#define GPIOINT_ENF2_P2_4EF_Pos (4UL)
3187#define GPIOINT_ENF2_P2_4EF_Msk (0x10UL)
3188#define GPIOINT_ENF2_P2_5EF_Pos (5UL)
3189#define GPIOINT_ENF2_P2_5EF_Msk (0x20UL)
3190#define GPIOINT_ENF2_P2_6EF_Pos (6UL)
3191#define GPIOINT_ENF2_P2_6EF_Msk (0x40UL)
3192#define GPIOINT_ENF2_P2_7EF_Pos (7UL)
3193#define GPIOINT_ENF2_P2_7EF_Msk (0x80UL)
3194#define GPIOINT_ENF2_P2_8EF_Pos (8UL)
3195#define GPIOINT_ENF2_P2_8EF_Msk (0x100UL)
3196#define GPIOINT_ENF2_P2_9EF_Pos (9UL)
3197#define GPIOINT_ENF2_P2_9EF_Msk (0x200UL)
3198#define GPIOINT_ENF2_P2_10EF_Pos (10UL)
3199#define GPIOINT_ENF2_P2_10EF_Msk (0x400UL)
3200#define GPIOINT_ENF2_P2_11EF_Pos (11UL)
3201#define GPIOINT_ENF2_P2_11EF_Msk (0x800UL)
3202#define GPIOINT_ENF2_P2_12EF_Pos (12UL)
3203#define GPIOINT_ENF2_P2_12EF_Msk (0x1000UL)
3204#define GPIOINT_ENF2_P2_13EF_Pos (13UL)
3205#define GPIOINT_ENF2_P2_13EF_Msk (0x2000UL)
3208/* =========================================================================================================================== */
3209/* ================ LPC_PINCONNECT ================ */
3210/* =========================================================================================================================== */
3211
3212/* ======================================================== PINSEL0 ======================================================== */
3213#define PINCONNECT_PINSEL0_P0_0_Pos (0UL)
3214#define PINCONNECT_PINSEL0_P0_0_Msk (0x3UL)
3215#define PINCONNECT_PINSEL0_P0_1_Pos (2UL)
3216#define PINCONNECT_PINSEL0_P0_1_Msk (0xcUL)
3217#define PINCONNECT_PINSEL0_P0_2_Pos (4UL)
3218#define PINCONNECT_PINSEL0_P0_2_Msk (0x30UL)
3219#define PINCONNECT_PINSEL0_P0_3_Pos (6UL)
3220#define PINCONNECT_PINSEL0_P0_3_Msk (0xc0UL)
3221#define PINCONNECT_PINSEL0_P0_4_Pos (8UL)
3222#define PINCONNECT_PINSEL0_P0_4_Msk (0x300UL)
3223#define PINCONNECT_PINSEL0_P0_5_Pos (10UL)
3224#define PINCONNECT_PINSEL0_P0_5_Msk (0xc00UL)
3225#define PINCONNECT_PINSEL0_P0_6_Pos (12UL)
3226#define PINCONNECT_PINSEL0_P0_6_Msk (0x3000UL)
3227#define PINCONNECT_PINSEL0_P0_7_Pos (14UL)
3228#define PINCONNECT_PINSEL0_P0_7_Msk (0xc000UL)
3229#define PINCONNECT_PINSEL0_P0_8_Pos (16UL)
3230#define PINCONNECT_PINSEL0_P0_8_Msk (0x30000UL)
3231#define PINCONNECT_PINSEL0_P0_9_Pos (18UL)
3232#define PINCONNECT_PINSEL0_P0_9_Msk (0xc0000UL)
3233#define PINCONNECT_PINSEL0_P0_10_Pos (20UL)
3234#define PINCONNECT_PINSEL0_P0_10_Msk (0x300000UL)
3235#define PINCONNECT_PINSEL0_P0_11_Pos (22UL)
3236#define PINCONNECT_PINSEL0_P0_11_Msk (0xc00000UL)
3237#define PINCONNECT_PINSEL0_P0_15_Pos (30UL)
3238#define PINCONNECT_PINSEL0_P0_15_Msk (0xc0000000UL)
3239/* ======================================================== PINSEL1 ======================================================== */
3240#define PINCONNECT_PINSEL1_P0_16_Pos (0UL)
3241#define PINCONNECT_PINSEL1_P0_16_Msk (0x3UL)
3242#define PINCONNECT_PINSEL1_P0_17_Pos (2UL)
3243#define PINCONNECT_PINSEL1_P0_17_Msk (0xcUL)
3244#define PINCONNECT_PINSEL1_P0_18_Pos (4UL)
3245#define PINCONNECT_PINSEL1_P0_18_Msk (0x30UL)
3246#define PINCONNECT_PINSEL1_P0_19_Pos (6UL)
3247#define PINCONNECT_PINSEL1_P0_19_Msk (0xc0UL)
3248#define PINCONNECT_PINSEL1_P0_20_Pos (8UL)
3249#define PINCONNECT_PINSEL1_P0_20_Msk (0x300UL)
3250#define PINCONNECT_PINSEL1_P0_21_Pos (10UL)
3251#define PINCONNECT_PINSEL1_P0_21_Msk (0xc00UL)
3252#define PINCONNECT_PINSEL1_P0_22_Pos (12UL)
3253#define PINCONNECT_PINSEL1_P0_22_Msk (0x3000UL)
3254#define PINCONNECT_PINSEL1_P0_23_Pos (14UL)
3255#define PINCONNECT_PINSEL1_P0_23_Msk (0xc000UL)
3256#define PINCONNECT_PINSEL1_P0_24_Pos (16UL)
3257#define PINCONNECT_PINSEL1_P0_24_Msk (0x30000UL)
3258#define PINCONNECT_PINSEL1_P0_25_Pos (18UL)
3259#define PINCONNECT_PINSEL1_P0_25_Msk (0xc0000UL)
3260#define PINCONNECT_PINSEL1_P0_26_Pos (20UL)
3261#define PINCONNECT_PINSEL1_P0_26_Msk (0x300000UL)
3262#define PINCONNECT_PINSEL1_P0_27_Pos (22UL)
3263#define PINCONNECT_PINSEL1_P0_27_Msk (0xc00000UL)
3264#define PINCONNECT_PINSEL1_P0_28_Pos (24UL)
3265#define PINCONNECT_PINSEL1_P0_28_Msk (0x3000000UL)
3266#define PINCONNECT_PINSEL1_P0_29_Pos (26UL)
3267#define PINCONNECT_PINSEL1_P0_29_Msk (0xc000000UL)
3268#define PINCONNECT_PINSEL1_P0_30_Pos (28UL)
3269#define PINCONNECT_PINSEL1_P0_30_Msk (0x30000000UL)
3270/* ======================================================== PINSEL2 ======================================================== */
3271#define PINCONNECT_PINSEL2_P1_0_Pos (0UL)
3272#define PINCONNECT_PINSEL2_P1_0_Msk (0x3UL)
3273#define PINCONNECT_PINSEL2_P1_1_Pos (2UL)
3274#define PINCONNECT_PINSEL2_P1_1_Msk (0xcUL)
3275#define PINCONNECT_PINSEL2_P1_4_Pos (8UL)
3276#define PINCONNECT_PINSEL2_P1_4_Msk (0x300UL)
3277#define PINCONNECT_PINSEL2_P1_8_Pos (16UL)
3278#define PINCONNECT_PINSEL2_P1_8_Msk (0x30000UL)
3279#define PINCONNECT_PINSEL2_P1_9_Pos (18UL)
3280#define PINCONNECT_PINSEL2_P1_9_Msk (0xc0000UL)
3281#define PINCONNECT_PINSEL2_P1_10_Pos (20UL)
3282#define PINCONNECT_PINSEL2_P1_10_Msk (0x300000UL)
3283#define PINCONNECT_PINSEL2_P1_14_Pos (22UL)
3284#define PINCONNECT_PINSEL2_P1_14_Msk (0xc00000UL)
3285#define PINCONNECT_PINSEL2_P1_15_Pos (30UL)
3286#define PINCONNECT_PINSEL2_P1_15_Msk (0xc0000000UL)
3287/* ======================================================== PINSEL3 ======================================================== */
3288#define PINCONNECT_PINSEL3_P1_16_Pos (0UL)
3289#define PINCONNECT_PINSEL3_P1_16_Msk (0x3UL)
3290#define PINCONNECT_PINSEL3_P1_17_Pos (2UL)
3291#define PINCONNECT_PINSEL3_P1_17_Msk (0xcUL)
3292#define PINCONNECT_PINSEL3_P1_18_Pos (4UL)
3293#define PINCONNECT_PINSEL3_P1_18_Msk (0x30UL)
3294#define PINCONNECT_PINSEL3_P1_19_Pos (6UL)
3295#define PINCONNECT_PINSEL3_P1_19_Msk (0xc0UL)
3296#define PINCONNECT_PINSEL3_P1_20_Pos (8UL)
3297#define PINCONNECT_PINSEL3_P1_20_Msk (0x300UL)
3298#define PINCONNECT_PINSEL3_P1_21_Pos (10UL)
3299#define PINCONNECT_PINSEL3_P1_21_Msk (0xc00UL)
3300#define PINCONNECT_PINSEL3_P1_22_Pos (12UL)
3301#define PINCONNECT_PINSEL3_P1_22_Msk (0x3000UL)
3302#define PINCONNECT_PINSEL3_P1_23_Pos (14UL)
3303#define PINCONNECT_PINSEL3_P1_23_Msk (0xc000UL)
3304#define PINCONNECT_PINSEL3_P1_24_Pos (16UL)
3305#define PINCONNECT_PINSEL3_P1_24_Msk (0x30000UL)
3306#define PINCONNECT_PINSEL3_P1_25_Pos (18UL)
3307#define PINCONNECT_PINSEL3_P1_25_Msk (0xc0000UL)
3308#define PINCONNECT_PINSEL3_P1_26_Pos (20UL)
3309#define PINCONNECT_PINSEL3_P1_26_Msk (0x300000UL)
3310#define PINCONNECT_PINSEL3_P1_27_Pos (22UL)
3311#define PINCONNECT_PINSEL3_P1_27_Msk (0xc00000UL)
3312#define PINCONNECT_PINSEL3_P1_28_Pos (24UL)
3313#define PINCONNECT_PINSEL3_P1_28_Msk (0x3000000UL)
3314#define PINCONNECT_PINSEL3_P1_29_Pos (26UL)
3315#define PINCONNECT_PINSEL3_P1_29_Msk (0xc000000UL)
3316#define PINCONNECT_PINSEL3_P1_30_Pos (28UL)
3317#define PINCONNECT_PINSEL3_P1_30_Msk (0x30000000UL)
3318#define PINCONNECT_PINSEL3_P1_31_Pos (30UL)
3319#define PINCONNECT_PINSEL3_P1_31_Msk (0xc0000000UL)
3320/* ======================================================== PINSEL4 ======================================================== */
3321#define PINCONNECT_PINSEL4_P2_0_Pos (0UL)
3322#define PINCONNECT_PINSEL4_P2_0_Msk (0x3UL)
3323#define PINCONNECT_PINSEL4_P2_1_Pos (2UL)
3324#define PINCONNECT_PINSEL4_P2_1_Msk (0xcUL)
3325#define PINCONNECT_PINSEL4_P2_2_Pos (4UL)
3326#define PINCONNECT_PINSEL4_P2_2_Msk (0x30UL)
3327#define PINCONNECT_PINSEL4_P2_3_Pos (6UL)
3328#define PINCONNECT_PINSEL4_P2_3_Msk (0xc0UL)
3329#define PINCONNECT_PINSEL4_P2_4_Pos (8UL)
3330#define PINCONNECT_PINSEL4_P2_4_Msk (0x300UL)
3331#define PINCONNECT_PINSEL4_P2_5_Pos (10UL)
3332#define PINCONNECT_PINSEL4_P2_5_Msk (0xc00UL)
3333#define PINCONNECT_PINSEL4_P2_6_Pos (12UL)
3334#define PINCONNECT_PINSEL4_P2_6_Msk (0x3000UL)
3335#define PINCONNECT_PINSEL4_P2_7_Pos (14UL)
3336#define PINCONNECT_PINSEL4_P2_7_Msk (0xc000UL)
3337#define PINCONNECT_PINSEL4_P2_8_Pos (16UL)
3338#define PINCONNECT_PINSEL4_P2_8_Msk (0x30000UL)
3339#define PINCONNECT_PINSEL4_P2_9_Pos (18UL)
3340#define PINCONNECT_PINSEL4_P2_9_Msk (0xc0000UL)
3341#define PINCONNECT_PINSEL4_P2_10_Pos (20UL)
3342#define PINCONNECT_PINSEL4_P2_10_Msk (0x300000UL)
3343#define PINCONNECT_PINSEL4_P2_11_Pos (22UL)
3344#define PINCONNECT_PINSEL4_P2_11_Msk (0xc00000UL)
3345#define PINCONNECT_PINSEL4_P2_12_Pos (24UL)
3346#define PINCONNECT_PINSEL4_P2_12_Msk (0x3000000UL)
3347#define PINCONNECT_PINSEL4_P2_13_Pos (26UL)
3348#define PINCONNECT_PINSEL4_P2_13_Msk (0xc000000UL)
3349/* ======================================================== PINSEL7 ======================================================== */
3350#define PINCONNECT_PINSEL7_P3_25_Pos (18UL)
3351#define PINCONNECT_PINSEL7_P3_25_Msk (0xc0000UL)
3352#define PINCONNECT_PINSEL7_P3_26_Pos (20UL)
3353#define PINCONNECT_PINSEL7_P3_26_Msk (0x300000UL)
3354/* ======================================================== PINSEL9 ======================================================== */
3355#define PINCONNECT_PINSEL9_P4_28_Pos (24UL)
3356#define PINCONNECT_PINSEL9_P4_28_Msk (0x3000000UL)
3357#define PINCONNECT_PINSEL9_P4_29_Pos (26UL)
3358#define PINCONNECT_PINSEL9_P4_29_Msk (0xc000000UL)
3359/* ======================================================= PINSEL10 ======================================================== */
3360#define PINCONNECT_PINSEL10_TPIUCTRL_Pos (3UL)
3361#define PINCONNECT_PINSEL10_TPIUCTRL_Msk (0x8UL)
3362/* ======================================================= PINMODE0 ======================================================== */
3363#define PINCONNECT_PINMODE0_P0_00MODE_Pos (0UL)
3364#define PINCONNECT_PINMODE0_P0_00MODE_Msk (0x3UL)
3365#define PINCONNECT_PINMODE0_P0_01MODE_Pos (2UL)
3366#define PINCONNECT_PINMODE0_P0_01MODE_Msk (0xcUL)
3367#define PINCONNECT_PINMODE0_P0_02MODE_Pos (4UL)
3368#define PINCONNECT_PINMODE0_P0_02MODE_Msk (0x30UL)
3369#define PINCONNECT_PINMODE0_P0_03MODE_Pos (6UL)
3370#define PINCONNECT_PINMODE0_P0_03MODE_Msk (0xc0UL)
3371#define PINCONNECT_PINMODE0_P0_04MODE_Pos (8UL)
3372#define PINCONNECT_PINMODE0_P0_04MODE_Msk (0x300UL)
3373#define PINCONNECT_PINMODE0_P0_05MODE_Pos (10UL)
3374#define PINCONNECT_PINMODE0_P0_05MODE_Msk (0xc00UL)
3375#define PINCONNECT_PINMODE0_P0_06MODE_Pos (12UL)
3376#define PINCONNECT_PINMODE0_P0_06MODE_Msk (0x3000UL)
3377#define PINCONNECT_PINMODE0_P0_07MODE_Pos (14UL)
3378#define PINCONNECT_PINMODE0_P0_07MODE_Msk (0xc000UL)
3379#define PINCONNECT_PINMODE0_P0_08MODE_Pos (16UL)
3380#define PINCONNECT_PINMODE0_P0_08MODE_Msk (0x30000UL)
3381#define PINCONNECT_PINMODE0_P0_09MODE_Pos (18UL)
3382#define PINCONNECT_PINMODE0_P0_09MODE_Msk (0xc0000UL)
3383#define PINCONNECT_PINMODE0_P0_10MODE_Pos (20UL)
3384#define PINCONNECT_PINMODE0_P0_10MODE_Msk (0x300000UL)
3385#define PINCONNECT_PINMODE0_P0_11MODE_Pos (22UL)
3386#define PINCONNECT_PINMODE0_P0_11MODE_Msk (0xc00000UL)
3387#define PINCONNECT_PINMODE0_P0_15MODE_Pos (30UL)
3388#define PINCONNECT_PINMODE0_P0_15MODE_Msk (0xc0000000UL)
3389/* ======================================================= PINMODE1 ======================================================== */
3390#define PINCONNECT_PINMODE1_P0_16MODE_Pos (0UL)
3391#define PINCONNECT_PINMODE1_P0_16MODE_Msk (0x3UL)
3392#define PINCONNECT_PINMODE1_P0_17MODE_Pos (2UL)
3393#define PINCONNECT_PINMODE1_P0_17MODE_Msk (0xcUL)
3394#define PINCONNECT_PINMODE1_P0_18MODE_Pos (4UL)
3395#define PINCONNECT_PINMODE1_P0_18MODE_Msk (0x30UL)
3396#define PINCONNECT_PINMODE1_P0_19MODE_Pos (6UL)
3397#define PINCONNECT_PINMODE1_P0_19MODE_Msk (0xc0UL)
3398#define PINCONNECT_PINMODE1_P0_20MODE_Pos (8UL)
3399#define PINCONNECT_PINMODE1_P0_20MODE_Msk (0x300UL)
3400#define PINCONNECT_PINMODE1_P0_21MODE_Pos (10UL)
3401#define PINCONNECT_PINMODE1_P0_21MODE_Msk (0xc00UL)
3402#define PINCONNECT_PINMODE1_P0_22MODE_Pos (12UL)
3403#define PINCONNECT_PINMODE1_P0_22MODE_Msk (0x3000UL)
3404#define PINCONNECT_PINMODE1_P0_23MODE_Pos (14UL)
3405#define PINCONNECT_PINMODE1_P0_23MODE_Msk (0xc000UL)
3406#define PINCONNECT_PINMODE1_P0_24MODE_Pos (16UL)
3407#define PINCONNECT_PINMODE1_P0_24MODE_Msk (0x30000UL)
3408#define PINCONNECT_PINMODE1_P0_25MODE_Pos (18UL)
3409#define PINCONNECT_PINMODE1_P0_25MODE_Msk (0xc0000UL)
3410#define PINCONNECT_PINMODE1_P0_26MODE_Pos (20UL)
3411#define PINCONNECT_PINMODE1_P0_26MODE_Msk (0x300000UL)
3412/* ======================================================= PINMODE2 ======================================================== */
3413#define PINCONNECT_PINMODE2_P1_00MODE_Pos (0UL)
3414#define PINCONNECT_PINMODE2_P1_00MODE_Msk (0x3UL)
3415#define PINCONNECT_PINMODE2_P1_01MODE_Pos (2UL)
3416#define PINCONNECT_PINMODE2_P1_01MODE_Msk (0xcUL)
3417#define PINCONNECT_PINMODE2_P1_04MODE_Pos (8UL)
3418#define PINCONNECT_PINMODE2_P1_04MODE_Msk (0x300UL)
3419#define PINCONNECT_PINMODE2_P1_08MODE_Pos (16UL)
3420#define PINCONNECT_PINMODE2_P1_08MODE_Msk (0x30000UL)
3421#define PINCONNECT_PINMODE2_P1_09MODE_Pos (18UL)
3422#define PINCONNECT_PINMODE2_P1_09MODE_Msk (0xc0000UL)
3423#define PINCONNECT_PINMODE2_P1_10MODE_Pos (20UL)
3424#define PINCONNECT_PINMODE2_P1_10MODE_Msk (0x300000UL)
3425#define PINCONNECT_PINMODE2_P1_14MODE_Pos (28UL)
3426#define PINCONNECT_PINMODE2_P1_14MODE_Msk (0x30000000UL)
3427#define PINCONNECT_PINMODE2_P1_15MODE_Pos (30UL)
3428#define PINCONNECT_PINMODE2_P1_15MODE_Msk (0xc0000000UL)
3429/* ======================================================= PINMODE3 ======================================================== */
3430#define PINCONNECT_PINMODE3_P1_16MODE_Pos (0UL)
3431#define PINCONNECT_PINMODE3_P1_16MODE_Msk (0x3UL)
3432#define PINCONNECT_PINMODE3_P1_17MODE_Pos (2UL)
3433#define PINCONNECT_PINMODE3_P1_17MODE_Msk (0xcUL)
3434#define PINCONNECT_PINMODE3_P1_18MODE_Pos (4UL)
3435#define PINCONNECT_PINMODE3_P1_18MODE_Msk (0x30UL)
3436#define PINCONNECT_PINMODE3_P1_19MODE_Pos (6UL)
3437#define PINCONNECT_PINMODE3_P1_19MODE_Msk (0xc0UL)
3438#define PINCONNECT_PINMODE3_P1_20MODE_Pos (8UL)
3439#define PINCONNECT_PINMODE3_P1_20MODE_Msk (0x300UL)
3440#define PINCONNECT_PINMODE3_P1_21MODE_Pos (10UL)
3441#define PINCONNECT_PINMODE3_P1_21MODE_Msk (0xc00UL)
3442#define PINCONNECT_PINMODE3_P1_22MODE_Pos (12UL)
3443#define PINCONNECT_PINMODE3_P1_22MODE_Msk (0x3000UL)
3444#define PINCONNECT_PINMODE3_P1_23MODE_Pos (14UL)
3445#define PINCONNECT_PINMODE3_P1_23MODE_Msk (0xc000UL)
3446#define PINCONNECT_PINMODE3_P1_24MODE_Pos (16UL)
3447#define PINCONNECT_PINMODE3_P1_24MODE_Msk (0x30000UL)
3448#define PINCONNECT_PINMODE3_P1_25MODE_Pos (18UL)
3449#define PINCONNECT_PINMODE3_P1_25MODE_Msk (0xc0000UL)
3450#define PINCONNECT_PINMODE3_P1_26MODE_Pos (20UL)
3451#define PINCONNECT_PINMODE3_P1_26MODE_Msk (0x300000UL)
3452#define PINCONNECT_PINMODE3_P1_27MODE_Pos (22UL)
3453#define PINCONNECT_PINMODE3_P1_27MODE_Msk (0xc00000UL)
3454#define PINCONNECT_PINMODE3_P1_28MODE_Pos (24UL)
3455#define PINCONNECT_PINMODE3_P1_28MODE_Msk (0x3000000UL)
3456#define PINCONNECT_PINMODE3_P1_29MODE_Pos (26UL)
3457#define PINCONNECT_PINMODE3_P1_29MODE_Msk (0xc000000UL)
3458#define PINCONNECT_PINMODE3_P1_30MODE_Pos (28UL)
3459#define PINCONNECT_PINMODE3_P1_30MODE_Msk (0x30000000UL)
3460#define PINCONNECT_PINMODE3_P1_31MODE_Pos (30UL)
3461#define PINCONNECT_PINMODE3_P1_31MODE_Msk (0xc0000000UL)
3462/* ======================================================= PINMODE4 ======================================================== */
3463#define PINCONNECT_PINMODE4_P2_00MODE_Pos (0UL)
3464#define PINCONNECT_PINMODE4_P2_00MODE_Msk (0x3UL)
3465#define PINCONNECT_PINMODE4_P2_01MODE_Pos (2UL)
3466#define PINCONNECT_PINMODE4_P2_01MODE_Msk (0xcUL)
3467#define PINCONNECT_PINMODE4_P2_02MODE_Pos (4UL)
3468#define PINCONNECT_PINMODE4_P2_02MODE_Msk (0x30UL)
3469#define PINCONNECT_PINMODE4_P2_03MODE_Pos (6UL)
3470#define PINCONNECT_PINMODE4_P2_03MODE_Msk (0xc0UL)
3471#define PINCONNECT_PINMODE4_P2_04MODE_Pos (8UL)
3472#define PINCONNECT_PINMODE4_P2_04MODE_Msk (0x300UL)
3473#define PINCONNECT_PINMODE4_P2_05MODE_Pos (10UL)
3474#define PINCONNECT_PINMODE4_P2_05MODE_Msk (0xc00UL)
3475#define PINCONNECT_PINMODE4_P2_06MODE_Pos (12UL)
3476#define PINCONNECT_PINMODE4_P2_06MODE_Msk (0x3000UL)
3477#define PINCONNECT_PINMODE4_P2_07MODE_Pos (14UL)
3478#define PINCONNECT_PINMODE4_P2_07MODE_Msk (0xc000UL)
3479#define PINCONNECT_PINMODE4_P2_08MODE_Pos (16UL)
3480#define PINCONNECT_PINMODE4_P2_08MODE_Msk (0x30000UL)
3481#define PINCONNECT_PINMODE4_P2_09MODE_Pos (18UL)
3482#define PINCONNECT_PINMODE4_P2_09MODE_Msk (0xc0000UL)
3483#define PINCONNECT_PINMODE4_P2_10MODE_Pos (20UL)
3484#define PINCONNECT_PINMODE4_P2_10MODE_Msk (0x300000UL)
3485#define PINCONNECT_PINMODE4_P2_11MODE_Pos (22UL)
3486#define PINCONNECT_PINMODE4_P2_11MODE_Msk (0xc00000UL)
3487#define PINCONNECT_PINMODE4_P2_12MODE_Pos (24UL)
3488#define PINCONNECT_PINMODE4_P2_12MODE_Msk (0x3000000UL)
3489#define PINCONNECT_PINMODE4_P2_13MODE_Pos (26UL)
3490#define PINCONNECT_PINMODE4_P2_13MODE_Msk (0xc000000UL)
3491/* ======================================================= PINMODE7 ======================================================== */
3492#define PINCONNECT_PINMODE7_P3_25MODE_Pos (18UL)
3493#define PINCONNECT_PINMODE7_P3_25MODE_Msk (0xc0000UL)
3494#define PINCONNECT_PINMODE7_P3_26MODE_Pos (20UL)
3495#define PINCONNECT_PINMODE7_P3_26MODE_Msk (0x300000UL)
3496/* ======================================================= PINMODE9 ======================================================== */
3497#define PINCONNECT_PINMODE9_P4_28MODE_Pos (24UL)
3498#define PINCONNECT_PINMODE9_P4_28MODE_Msk (0x3000000UL)
3499#define PINCONNECT_PINMODE9_P4_29MODE_Pos (26UL)
3500#define PINCONNECT_PINMODE9_P4_29MODE_Msk (0xc000000UL)
3501/* ====================================================== PINMODE_OD0 ====================================================== */
3502#define PINCONNECT_PINMODE_OD0_P0_00OD_Pos (0UL)
3503#define PINCONNECT_PINMODE_OD0_P0_00OD_Msk (0x1UL)
3504#define PINCONNECT_PINMODE_OD0_P0_01OD_Pos (1UL)
3505#define PINCONNECT_PINMODE_OD0_P0_01OD_Msk (0x2UL)
3506#define PINCONNECT_PINMODE_OD0_P0_02OD_Pos (2UL)
3507#define PINCONNECT_PINMODE_OD0_P0_02OD_Msk (0x4UL)
3508#define PINCONNECT_PINMODE_OD0_P0_03OD_Pos (3UL)
3509#define PINCONNECT_PINMODE_OD0_P0_03OD_Msk (0x8UL)
3510#define PINCONNECT_PINMODE_OD0_P0_04OD_Pos (4UL)
3511#define PINCONNECT_PINMODE_OD0_P0_04OD_Msk (0x10UL)
3512#define PINCONNECT_PINMODE_OD0_P0_05OD_Pos (5UL)
3513#define PINCONNECT_PINMODE_OD0_P0_05OD_Msk (0x20UL)
3514#define PINCONNECT_PINMODE_OD0_P0_06OD_Pos (6UL)
3515#define PINCONNECT_PINMODE_OD0_P0_06OD_Msk (0x40UL)
3516#define PINCONNECT_PINMODE_OD0_P0_07OD_Pos (7UL)
3517#define PINCONNECT_PINMODE_OD0_P0_07OD_Msk (0x80UL)
3518#define PINCONNECT_PINMODE_OD0_P0_08OD_Pos (8UL)
3519#define PINCONNECT_PINMODE_OD0_P0_08OD_Msk (0x100UL)
3520#define PINCONNECT_PINMODE_OD0_P0_09OD_Pos (9UL)
3521#define PINCONNECT_PINMODE_OD0_P0_09OD_Msk (0x200UL)
3522#define PINCONNECT_PINMODE_OD0_P0_10OD_Pos (10UL)
3523#define PINCONNECT_PINMODE_OD0_P0_10OD_Msk (0x400UL)
3524#define PINCONNECT_PINMODE_OD0_P0_11OD_Pos (11UL)
3525#define PINCONNECT_PINMODE_OD0_P0_11OD_Msk (0x800UL)
3526#define PINCONNECT_PINMODE_OD0_P0_15OD_Pos (15UL)
3527#define PINCONNECT_PINMODE_OD0_P0_15OD_Msk (0x8000UL)
3528#define PINCONNECT_PINMODE_OD0_P0_16OD_Pos (16UL)
3529#define PINCONNECT_PINMODE_OD0_P0_16OD_Msk (0x10000UL)
3530#define PINCONNECT_PINMODE_OD0_P0_17OD_Pos (17UL)
3531#define PINCONNECT_PINMODE_OD0_P0_17OD_Msk (0x20000UL)
3532#define PINCONNECT_PINMODE_OD0_P0_18OD_Pos (18UL)
3533#define PINCONNECT_PINMODE_OD0_P0_18OD_Msk (0x40000UL)
3534#define PINCONNECT_PINMODE_OD0_P0_19OD_Pos (19UL)
3535#define PINCONNECT_PINMODE_OD0_P0_19OD_Msk (0x80000UL)
3536#define PINCONNECT_PINMODE_OD0_P0_20OD_Pos (20UL)
3537#define PINCONNECT_PINMODE_OD0_P0_20OD_Msk (0x100000UL)
3538#define PINCONNECT_PINMODE_OD0_P0_21OD_Pos (21UL)
3539#define PINCONNECT_PINMODE_OD0_P0_21OD_Msk (0x200000UL)
3540#define PINCONNECT_PINMODE_OD0_P0_22OD_Pos (22UL)
3541#define PINCONNECT_PINMODE_OD0_P0_22OD_Msk (0x400000UL)
3542#define PINCONNECT_PINMODE_OD0_P0_23OD_Pos (23UL)
3543#define PINCONNECT_PINMODE_OD0_P0_23OD_Msk (0x800000UL)
3544#define PINCONNECT_PINMODE_OD0_P0_24OD_Pos (24UL)
3545#define PINCONNECT_PINMODE_OD0_P0_24OD_Msk (0x1000000UL)
3546#define PINCONNECT_PINMODE_OD0_P0_25OD_Pos (25UL)
3547#define PINCONNECT_PINMODE_OD0_P0_25OD_Msk (0x2000000UL)
3548#define PINCONNECT_PINMODE_OD0_P0_26OD_Pos (26UL)
3549#define PINCONNECT_PINMODE_OD0_P0_26OD_Msk (0x4000000UL)
3550#define PINCONNECT_PINMODE_OD0_P0_29OD_Pos (29UL)
3551#define PINCONNECT_PINMODE_OD0_P0_29OD_Msk (0x20000000UL)
3552#define PINCONNECT_PINMODE_OD0_P0_30OD_Pos (30UL)
3553#define PINCONNECT_PINMODE_OD0_P0_30OD_Msk (0x40000000UL)
3554/* ====================================================== PINMODE_OD1 ====================================================== */
3555#define PINCONNECT_PINMODE_OD1_P1_00OD_Pos (0UL)
3556#define PINCONNECT_PINMODE_OD1_P1_00OD_Msk (0x1UL)
3557#define PINCONNECT_PINMODE_OD1_P1_01OD_Pos (1UL)
3558#define PINCONNECT_PINMODE_OD1_P1_01OD_Msk (0x2UL)
3559#define PINCONNECT_PINMODE_OD1_P1_04OD_Pos (4UL)
3560#define PINCONNECT_PINMODE_OD1_P1_04OD_Msk (0x10UL)
3561#define PINCONNECT_PINMODE_OD1_P1_08OD_Pos (8UL)
3562#define PINCONNECT_PINMODE_OD1_P1_08OD_Msk (0x100UL)
3563#define PINCONNECT_PINMODE_OD1_P1_09OD_Pos (9UL)
3564#define PINCONNECT_PINMODE_OD1_P1_09OD_Msk (0x200UL)
3565#define PINCONNECT_PINMODE_OD1_P1_10OD_Pos (10UL)
3566#define PINCONNECT_PINMODE_OD1_P1_10OD_Msk (0x400UL)
3567#define PINCONNECT_PINMODE_OD1_P1_14OD_Pos (14UL)
3568#define PINCONNECT_PINMODE_OD1_P1_14OD_Msk (0x4000UL)
3569#define PINCONNECT_PINMODE_OD1_P1_15OD_Pos (15UL)
3570#define PINCONNECT_PINMODE_OD1_P1_15OD_Msk (0x8000UL)
3571#define PINCONNECT_PINMODE_OD1_P1_16OD_Pos (16UL)
3572#define PINCONNECT_PINMODE_OD1_P1_16OD_Msk (0x10000UL)
3573#define PINCONNECT_PINMODE_OD1_P1_17OD_Pos (17UL)
3574#define PINCONNECT_PINMODE_OD1_P1_17OD_Msk (0x20000UL)
3575#define PINCONNECT_PINMODE_OD1_P1_18OD_Pos (18UL)
3576#define PINCONNECT_PINMODE_OD1_P1_18OD_Msk (0x40000UL)
3577#define PINCONNECT_PINMODE_OD1_P1_19OD_Pos (19UL)
3578#define PINCONNECT_PINMODE_OD1_P1_19OD_Msk (0x80000UL)
3579#define PINCONNECT_PINMODE_OD1_P1_20OD_Pos (20UL)
3580#define PINCONNECT_PINMODE_OD1_P1_20OD_Msk (0x100000UL)
3581#define PINCONNECT_PINMODE_OD1_P1_21OD_Pos (21UL)
3582#define PINCONNECT_PINMODE_OD1_P1_21OD_Msk (0x200000UL)
3583#define PINCONNECT_PINMODE_OD1_P1_22OD_Pos (22UL)
3584#define PINCONNECT_PINMODE_OD1_P1_22OD_Msk (0x400000UL)
3585#define PINCONNECT_PINMODE_OD1_P1_23OD_Pos (23UL)
3586#define PINCONNECT_PINMODE_OD1_P1_23OD_Msk (0x800000UL)
3587#define PINCONNECT_PINMODE_OD1_P1_24OD_Pos (24UL)
3588#define PINCONNECT_PINMODE_OD1_P1_24OD_Msk (0x1000000UL)
3589#define PINCONNECT_PINMODE_OD1_P1_25OD_Pos (25UL)
3590#define PINCONNECT_PINMODE_OD1_P1_25OD_Msk (0x2000000UL)
3591#define PINCONNECT_PINMODE_OD1_P1_26OD_Pos (26UL)
3592#define PINCONNECT_PINMODE_OD1_P1_26OD_Msk (0x4000000UL)
3593#define PINCONNECT_PINMODE_OD1_P1_27OD_Pos (27UL)
3594#define PINCONNECT_PINMODE_OD1_P1_27OD_Msk (0x8000000UL)
3595#define PINCONNECT_PINMODE_OD1_P1_28OD_Pos (28UL)
3596#define PINCONNECT_PINMODE_OD1_P1_28OD_Msk (0x10000000UL)
3597#define PINCONNECT_PINMODE_OD1_P1_29OD_Pos (29UL)
3598#define PINCONNECT_PINMODE_OD1_P1_29OD_Msk (0x20000000UL)
3599#define PINCONNECT_PINMODE_OD1_P1_30OD_Pos (30UL)
3600#define PINCONNECT_PINMODE_OD1_P1_30OD_Msk (0x40000000UL)
3601#define PINCONNECT_PINMODE_OD1_P1_31OD_Pos (31UL)
3602#define PINCONNECT_PINMODE_OD1_P1_31OD_Msk (0x80000000UL)
3603/* ====================================================== PINMODE_OD2 ====================================================== */
3604#define PINCONNECT_PINMODE_OD2_P2_00OD_Pos (0UL)
3605#define PINCONNECT_PINMODE_OD2_P2_00OD_Msk (0x1UL)
3606#define PINCONNECT_PINMODE_OD2_P2_01OD_Pos (1UL)
3607#define PINCONNECT_PINMODE_OD2_P2_01OD_Msk (0x2UL)
3608#define PINCONNECT_PINMODE_OD2_P2_02OD_Pos (2UL)
3609#define PINCONNECT_PINMODE_OD2_P2_02OD_Msk (0x4UL)
3610#define PINCONNECT_PINMODE_OD2_P2_03OD_Pos (3UL)
3611#define PINCONNECT_PINMODE_OD2_P2_03OD_Msk (0x8UL)
3612#define PINCONNECT_PINMODE_OD2_P2_04OD_Pos (4UL)
3613#define PINCONNECT_PINMODE_OD2_P2_04OD_Msk (0x10UL)
3614#define PINCONNECT_PINMODE_OD2_P2_05OD_Pos (5UL)
3615#define PINCONNECT_PINMODE_OD2_P2_05OD_Msk (0x20UL)
3616#define PINCONNECT_PINMODE_OD2_P2_06OD_Pos (6UL)
3617#define PINCONNECT_PINMODE_OD2_P2_06OD_Msk (0x40UL)
3618#define PINCONNECT_PINMODE_OD2_P2_07OD_Pos (7UL)
3619#define PINCONNECT_PINMODE_OD2_P2_07OD_Msk (0x80UL)
3620#define PINCONNECT_PINMODE_OD2_P2_08OD_Pos (8UL)
3621#define PINCONNECT_PINMODE_OD2_P2_08OD_Msk (0x100UL)
3622#define PINCONNECT_PINMODE_OD2_P2_09OD_Pos (9UL)
3623#define PINCONNECT_PINMODE_OD2_P2_09OD_Msk (0x200UL)
3624#define PINCONNECT_PINMODE_OD2_P2_10OD_Pos (10UL)
3625#define PINCONNECT_PINMODE_OD2_P2_10OD_Msk (0x400UL)
3626#define PINCONNECT_PINMODE_OD2_P2_11OD_Pos (11UL)
3627#define PINCONNECT_PINMODE_OD2_P2_11OD_Msk (0x800UL)
3628#define PINCONNECT_PINMODE_OD2_P2_12OD_Pos (12UL)
3629#define PINCONNECT_PINMODE_OD2_P2_12OD_Msk (0x1000UL)
3630#define PINCONNECT_PINMODE_OD2_P2_13OD_Pos (13UL)
3631#define PINCONNECT_PINMODE_OD2_P2_13OD_Msk (0x2000UL)
3632/* ====================================================== PINMODE_OD3 ====================================================== */
3633#define PINCONNECT_PINMODE_OD3_P3_25OD_Pos (25UL)
3634#define PINCONNECT_PINMODE_OD3_P3_25OD_Msk (0x2000000UL)
3635#define PINCONNECT_PINMODE_OD3_P3_26OD_Pos (26UL)
3636#define PINCONNECT_PINMODE_OD3_P3_26OD_Msk (0x4000000UL)
3637/* ====================================================== PINMODE_OD4 ====================================================== */
3638#define PINCONNECT_PINMODE_OD4_P4_28OD_Pos (28UL)
3639#define PINCONNECT_PINMODE_OD4_P4_28OD_Msk (0x10000000UL)
3640#define PINCONNECT_PINMODE_OD4_P4_29OD_Pos (29UL)
3641#define PINCONNECT_PINMODE_OD4_P4_29OD_Msk (0x20000000UL)
3642/* ======================================================= I2CPADCFG ======================================================= */
3643#define PINCONNECT_I2CPADCFG_SDADRV0_Pos (0UL)
3644#define PINCONNECT_I2CPADCFG_SDADRV0_Msk (0x1UL)
3645#define PINCONNECT_I2CPADCFG_SDAI2C0_Pos (1UL)
3646#define PINCONNECT_I2CPADCFG_SDAI2C0_Msk (0x2UL)
3647#define PINCONNECT_I2CPADCFG_SCLDRV0_Pos (2UL)
3648#define PINCONNECT_I2CPADCFG_SCLDRV0_Msk (0x4UL)
3649#define PINCONNECT_I2CPADCFG_SCLI2C0_Pos (3UL)
3650#define PINCONNECT_I2CPADCFG_SCLI2C0_Msk (0x8UL)
3653/* =========================================================================================================================== */
3654/* ================ LPC_SSP1 ================ */
3655/* =========================================================================================================================== */
3656
3657/* ========================================================== CR0 ========================================================== */
3658#define SSP1_CR0_DSS_Pos (0UL)
3659#define SSP1_CR0_DSS_Msk (0xfUL)
3660#define SSP1_CR0_FRF_Pos (4UL)
3661#define SSP1_CR0_FRF_Msk (0x30UL)
3662#define SSP1_CR0_CPOL_Pos (6UL)
3663#define SSP1_CR0_CPOL_Msk (0x40UL)
3664#define SSP1_CR0_CPHA_Pos (7UL)
3665#define SSP1_CR0_CPHA_Msk (0x80UL)
3666#define SSP1_CR0_SCR_Pos (8UL)
3667#define SSP1_CR0_SCR_Msk (0xff00UL)
3668/* ========================================================== CR1 ========================================================== */
3669#define SSP1_CR1_LBM_Pos (0UL)
3670#define SSP1_CR1_LBM_Msk (0x1UL)
3671#define SSP1_CR1_SSE_Pos (1UL)
3672#define SSP1_CR1_SSE_Msk (0x2UL)
3673#define SSP1_CR1_MS_Pos (2UL)
3674#define SSP1_CR1_MS_Msk (0x4UL)
3675#define SSP1_CR1_SOD_Pos (3UL)
3676#define SSP1_CR1_SOD_Msk (0x8UL)
3677/* ========================================================== DR =========================================================== */
3678#define SSP1_DR_DATA_Pos (0UL)
3679#define SSP1_DR_DATA_Msk (0xffffUL)
3680/* ========================================================== SR =========================================================== */
3681#define SSP1_SR_TFE_Pos (0UL)
3682#define SSP1_SR_TFE_Msk (0x1UL)
3683#define SSP1_SR_TNF_Pos (1UL)
3684#define SSP1_SR_TNF_Msk (0x2UL)
3685#define SSP1_SR_RNE_Pos (2UL)
3686#define SSP1_SR_RNE_Msk (0x4UL)
3687#define SSP1_SR_RFF_Pos (3UL)
3688#define SSP1_SR_RFF_Msk (0x8UL)
3689#define SSP1_SR_BSY_Pos (4UL)
3690#define SSP1_SR_BSY_Msk (0x10UL)
3691/* ========================================================= CPSR ========================================================== */
3692#define SSP1_CPSR_CPSDVSR_Pos (0UL)
3693#define SSP1_CPSR_CPSDVSR_Msk (0xffUL)
3694/* ========================================================= IMSC ========================================================== */
3695#define SSP1_IMSC_RORIM_Pos (0UL)
3696#define SSP1_IMSC_RORIM_Msk (0x1UL)
3697#define SSP1_IMSC_RTIM_Pos (1UL)
3698#define SSP1_IMSC_RTIM_Msk (0x2UL)
3699#define SSP1_IMSC_RXIM_Pos (2UL)
3700#define SSP1_IMSC_RXIM_Msk (0x4UL)
3701#define SSP1_IMSC_TXIM_Pos (3UL)
3702#define SSP1_IMSC_TXIM_Msk (0x8UL)
3703/* ========================================================== RIS ========================================================== */
3704#define SSP1_RIS_RORRIS_Pos (0UL)
3705#define SSP1_RIS_RORRIS_Msk (0x1UL)
3706#define SSP1_RIS_RTRIS_Pos (1UL)
3707#define SSP1_RIS_RTRIS_Msk (0x2UL)
3708#define SSP1_RIS_RXRIS_Pos (2UL)
3709#define SSP1_RIS_RXRIS_Msk (0x4UL)
3710#define SSP1_RIS_TXRIS_Pos (3UL)
3711#define SSP1_RIS_TXRIS_Msk (0x8UL)
3712/* ========================================================== MIS ========================================================== */
3713#define SSP1_MIS_RORMIS_Pos (0UL)
3714#define SSP1_MIS_RORMIS_Msk (0x1UL)
3715#define SSP1_MIS_RTMIS_Pos (1UL)
3716#define SSP1_MIS_RTMIS_Msk (0x2UL)
3717#define SSP1_MIS_RXMIS_Pos (2UL)
3718#define SSP1_MIS_RXMIS_Msk (0x4UL)
3719#define SSP1_MIS_TXMIS_Pos (3UL)
3720#define SSP1_MIS_TXMIS_Msk (0x8UL)
3721/* ========================================================== ICR ========================================================== */
3722#define SSP1_ICR_RORIC_Pos (0UL)
3723#define SSP1_ICR_RORIC_Msk (0x1UL)
3724#define SSP1_ICR_RTIC_Pos (1UL)
3725#define SSP1_ICR_RTIC_Msk (0x2UL)
3726/* ========================================================= DMACR ========================================================= */
3727#define SSP1_DMACR_RXDMAE_Pos (0UL)
3728#define SSP1_DMACR_RXDMAE_Msk (0x1UL)
3729#define SSP1_DMACR_TXDMAE_Pos (1UL)
3730#define SSP1_DMACR_TXDMAE_Msk (0x2UL)
3733/* =========================================================================================================================== */
3734/* ================ LPC_ADC ================ */
3735/* =========================================================================================================================== */
3736
3737/* ========================================================== CR =========================================================== */
3738#define ADC_CR_SEL_Pos (0UL)
3739#define ADC_CR_SEL_Msk (0xffUL)
3740#define ADC_CR_CLKDIV_Pos (8UL)
3741#define ADC_CR_CLKDIV_Msk (0xff00UL)
3742#define ADC_CR_BURST_Pos (16UL)
3743#define ADC_CR_BURST_Msk (0x10000UL)
3744#define ADC_CR_PDN_Pos (21UL)
3745#define ADC_CR_PDN_Msk (0x200000UL)
3746#define ADC_CR_START_Pos (24UL)
3747#define ADC_CR_START_Msk (0x7000000UL)
3748#define ADC_CR_EDGE_Pos (27UL)
3749#define ADC_CR_EDGE_Msk (0x8000000UL)
3750/* ========================================================== GDR ========================================================== */
3751#define ADC_GDR_RESULT_Pos (4UL)
3752#define ADC_GDR_RESULT_Msk (0xfff0UL)
3753#define ADC_GDR_CHN_Pos (24UL)
3754#define ADC_GDR_CHN_Msk (0x7000000UL)
3755#define ADC_GDR_OVERRUN_Pos (30UL)
3756#define ADC_GDR_OVERRUN_Msk (0x40000000UL)
3757#define ADC_GDR_DONE_Pos (31UL)
3758#define ADC_GDR_DONE_Msk (0x80000000UL)
3759/* ========================================================= INTEN ========================================================= */
3760#define ADC_INTEN_ADINTEN0_Pos (0UL)
3761#define ADC_INTEN_ADINTEN0_Msk (0x1UL)
3762#define ADC_INTEN_ADINTEN1_Pos (1UL)
3763#define ADC_INTEN_ADINTEN1_Msk (0x2UL)
3764#define ADC_INTEN_ADINTEN2_Pos (2UL)
3765#define ADC_INTEN_ADINTEN2_Msk (0x4UL)
3766#define ADC_INTEN_ADINTEN3_Pos (3UL)
3767#define ADC_INTEN_ADINTEN3_Msk (0x8UL)
3768#define ADC_INTEN_ADINTEN4_Pos (4UL)
3769#define ADC_INTEN_ADINTEN4_Msk (0x10UL)
3770#define ADC_INTEN_ADINTEN5_Pos (5UL)
3771#define ADC_INTEN_ADINTEN5_Msk (0x20UL)
3772#define ADC_INTEN_ADINTEN6_Pos (6UL)
3773#define ADC_INTEN_ADINTEN6_Msk (0x40UL)
3774#define ADC_INTEN_ADINTEN7_Pos (7UL)
3775#define ADC_INTEN_ADINTEN7_Msk (0x80UL)
3776#define ADC_INTEN_ADGINTEN_Pos (8UL)
3777#define ADC_INTEN_ADGINTEN_Msk (0x100UL)
3778/* ========================================================= STAT ========================================================== */
3779#define ADC_STAT_DONE0_Pos (0UL)
3780#define ADC_STAT_DONE0_Msk (0x1UL)
3781#define ADC_STAT_DONE1_Pos (1UL)
3782#define ADC_STAT_DONE1_Msk (0x2UL)
3783#define ADC_STAT_DONE2_Pos (2UL)
3784#define ADC_STAT_DONE2_Msk (0x4UL)
3785#define ADC_STAT_DONE3_Pos (3UL)
3786#define ADC_STAT_DONE3_Msk (0x8UL)
3787#define ADC_STAT_DONE4_Pos (4UL)
3788#define ADC_STAT_DONE4_Msk (0x10UL)
3789#define ADC_STAT_DONE5_Pos (5UL)
3790#define ADC_STAT_DONE5_Msk (0x20UL)
3791#define ADC_STAT_DONE6_Pos (6UL)
3792#define ADC_STAT_DONE6_Msk (0x40UL)
3793#define ADC_STAT_DONE7_Pos (7UL)
3794#define ADC_STAT_DONE7_Msk (0x80UL)
3795#define ADC_STAT_OVERRUN0_Pos (8UL)
3796#define ADC_STAT_OVERRUN0_Msk (0x100UL)
3797#define ADC_STAT_OVERRUN1_Pos (9UL)
3798#define ADC_STAT_OVERRUN1_Msk (0x200UL)
3799#define ADC_STAT_OVERRUN2_Pos (10UL)
3800#define ADC_STAT_OVERRUN2_Msk (0x400UL)
3801#define ADC_STAT_OVERRUN3_Pos (11UL)
3802#define ADC_STAT_OVERRUN3_Msk (0x800UL)
3803#define ADC_STAT_OVERRUN4_Pos (12UL)
3804#define ADC_STAT_OVERRUN4_Msk (0x1000UL)
3805#define ADC_STAT_OVERRUN5_Pos (13UL)
3806#define ADC_STAT_OVERRUN5_Msk (0x2000UL)
3807#define ADC_STAT_OVERRUN6_Pos (14UL)
3808#define ADC_STAT_OVERRUN6_Msk (0x4000UL)
3809#define ADC_STAT_OVERRUN7_Pos (15UL)
3810#define ADC_STAT_OVERRUN7_Msk (0x8000UL)
3811#define ADC_STAT_ADINT_Pos (16UL)
3812#define ADC_STAT_ADINT_Msk (0x10000UL)
3813/* ========================================================== TRM ========================================================== */
3814#define ADC_TRM_ADCOFFS_Pos (4UL)
3815#define ADC_TRM_ADCOFFS_Msk (0xf0UL)
3816#define ADC_TRM_TRIM_Pos (8UL)
3817#define ADC_TRM_TRIM_Msk (0xf00UL)
3820/* =========================================================================================================================== */
3821/* ================ LPC_CANAFRAM ================ */
3822/* =========================================================================================================================== */
3823
3824
3825
3826/* =========================================================================================================================== */
3827/* ================ LPC_CANAF ================ */
3828/* =========================================================================================================================== */
3829
3830/* ========================================================= AFMR ========================================================== */
3831#define CANAF_AFMR_ACCOFF_Pos (0UL)
3832#define CANAF_AFMR_ACCOFF_Msk (0x1UL)
3833#define CANAF_AFMR_ACCBP_Pos (1UL)
3834#define CANAF_AFMR_ACCBP_Msk (0x2UL)
3835#define CANAF_AFMR_EFCAN_Pos (2UL)
3836#define CANAF_AFMR_EFCAN_Msk (0x4UL)
3837/* ======================================================== SFF_SA ========================================================= */
3838#define CANAF_SFF_SA_SFF_SA_Pos (2UL)
3839#define CANAF_SFF_SA_SFF_SA_Msk (0x7fcUL)
3840/* ====================================================== SFF_GRP_SA ======================================================= */
3841#define CANAF_SFF_GRP_SA_SFF_GRP_SA_Pos (2UL)
3842#define CANAF_SFF_GRP_SA_SFF_GRP_SA_Msk (0xffcUL)
3843/* ======================================================== EFF_SA ========================================================= */
3844#define CANAF_EFF_SA_EFF_SA_Pos (2UL)
3845#define CANAF_EFF_SA_EFF_SA_Msk (0x7fcUL)
3846/* ====================================================== EFF_GRP_SA ======================================================= */
3847#define CANAF_EFF_GRP_SA_EFF_GRP_SA_Pos (2UL)
3848#define CANAF_EFF_GRP_SA_EFF_GRP_SA_Msk (0xffcUL)
3849/* ====================================================== ENDOFTABLE ======================================================= */
3850#define CANAF_ENDOFTABLE_ENDOFTABLE_Pos (2UL)
3851#define CANAF_ENDOFTABLE_ENDOFTABLE_Msk (0xffcUL)
3852/* ======================================================= LUTERRAD ======================================================== */
3853#define CANAF_LUTERRAD_LUTERRAD_Pos (2UL)
3854#define CANAF_LUTERRAD_LUTERRAD_Msk (0x7fcUL)
3855/* ======================================================== LUTERR ========================================================= */
3856#define CANAF_LUTERR_LUTERR_Pos (0UL)
3857#define CANAF_LUTERR_LUTERR_Msk (0x1UL)
3858/* ======================================================== FCANIE ========================================================= */
3859#define CANAF_FCANIE_FCANIE_Pos (0UL)
3860#define CANAF_FCANIE_FCANIE_Msk (0x1UL)
3861/* ======================================================== FCANIC0 ======================================================== */
3862#define CANAF_FCANIC0_INTPND_Pos (0UL)
3863#define CANAF_FCANIC0_INTPND_Msk (0xffffffffUL)
3864/* ======================================================== FCANIC1 ======================================================== */
3865#define CANAF_FCANIC1_IntPnd32_Pos (0UL)
3866#define CANAF_FCANIC1_IntPnd32_Msk (0xffffffffUL)
3869/* =========================================================================================================================== */
3870/* ================ LPC_CCAN ================ */
3871/* =========================================================================================================================== */
3872
3873/* ========================================================= TXSR ========================================================== */
3874#define CCAN_TXSR_TS1_Pos (0UL)
3875#define CCAN_TXSR_TS1_Msk (0x1UL)
3876#define CCAN_TXSR_TS2_Pos (1UL)
3877#define CCAN_TXSR_TS2_Msk (0x2UL)
3878#define CCAN_TXSR_TBS1_Pos (8UL)
3879#define CCAN_TXSR_TBS1_Msk (0x100UL)
3880#define CCAN_TXSR_TBS2_Pos (9UL)
3881#define CCAN_TXSR_TBS2_Msk (0x200UL)
3882#define CCAN_TXSR_TCS1_Pos (16UL)
3883#define CCAN_TXSR_TCS1_Msk (0x10000UL)
3884#define CCAN_TXSR_TCS2_Pos (17UL)
3885#define CCAN_TXSR_TCS2_Msk (0x20000UL)
3886/* ========================================================= RXSR ========================================================== */
3887#define CCAN_RXSR_RS1_Pos (0UL)
3888#define CCAN_RXSR_RS1_Msk (0x1UL)
3889#define CCAN_RXSR_RS2_Pos (1UL)
3890#define CCAN_RXSR_RS2_Msk (0x2UL)
3891#define CCAN_RXSR_RB1_Pos (8UL)
3892#define CCAN_RXSR_RB1_Msk (0x100UL)
3893#define CCAN_RXSR_RB2_Pos (9UL)
3894#define CCAN_RXSR_RB2_Msk (0x200UL)
3895#define CCAN_RXSR_DOS1_Pos (16UL)
3896#define CCAN_RXSR_DOS1_Msk (0x10000UL)
3897#define CCAN_RXSR_DOS2_Pos (17UL)
3898#define CCAN_RXSR_DOS2_Msk (0x20000UL)
3899/* ========================================================== MSR ========================================================== */
3900#define CCAN_MSR_E1_Pos (0UL)
3901#define CCAN_MSR_E1_Msk (0x1UL)
3902#define CCAN_MSR_E2_Pos (1UL)
3903#define CCAN_MSR_E2_Msk (0x2UL)
3904#define CCAN_MSR_BS1_Pos (8UL)
3905#define CCAN_MSR_BS1_Msk (0x100UL)
3906#define CCAN_MSR_BS2_Pos (9UL)
3907#define CCAN_MSR_BS2_Msk (0x200UL)
3910/* =========================================================================================================================== */
3911/* ================ LPC_CAN1 ================ */
3912/* =========================================================================================================================== */
3913
3914/* ========================================================== MOD ========================================================== */
3915#define CAN1_MOD_RM_Pos (0UL)
3916#define CAN1_MOD_RM_Msk (0x1UL)
3917#define CAN1_MOD_LOM_Pos (1UL)
3918#define CAN1_MOD_LOM_Msk (0x2UL)
3919#define CAN1_MOD_STM_Pos (2UL)
3920#define CAN1_MOD_STM_Msk (0x4UL)
3921#define CAN1_MOD_TPM_Pos (3UL)
3922#define CAN1_MOD_TPM_Msk (0x8UL)
3923#define CAN1_MOD_SM_Pos (4UL)
3924#define CAN1_MOD_SM_Msk (0x10UL)
3925#define CAN1_MOD_RPM_Pos (5UL)
3926#define CAN1_MOD_RPM_Msk (0x20UL)
3927#define CAN1_MOD_TM_Pos (7UL)
3928#define CAN1_MOD_TM_Msk (0x80UL)
3929/* ========================================================== CMR ========================================================== */
3930#define CAN1_CMR_TR_Pos (0UL)
3931#define CAN1_CMR_TR_Msk (0x1UL)
3932#define CAN1_CMR_AT_Pos (1UL)
3933#define CAN1_CMR_AT_Msk (0x2UL)
3934#define CAN1_CMR_RRB_Pos (2UL)
3935#define CAN1_CMR_RRB_Msk (0x4UL)
3936#define CAN1_CMR_CDO_Pos (3UL)
3937#define CAN1_CMR_CDO_Msk (0x8UL)
3938#define CAN1_CMR_SRR_Pos (4UL)
3939#define CAN1_CMR_SRR_Msk (0x10UL)
3940#define CAN1_CMR_STB1_Pos (5UL)
3941#define CAN1_CMR_STB1_Msk (0x20UL)
3942#define CAN1_CMR_STB2_Pos (6UL)
3943#define CAN1_CMR_STB2_Msk (0x40UL)
3944#define CAN1_CMR_STB3_Pos (7UL)
3945#define CAN1_CMR_STB3_Msk (0x80UL)
3946/* ========================================================== GSR ========================================================== */
3947#define CAN1_GSR_RBS_Pos (0UL)
3948#define CAN1_GSR_RBS_Msk (0x1UL)
3949#define CAN1_GSR_DOS_Pos (1UL)
3950#define CAN1_GSR_DOS_Msk (0x2UL)
3951#define CAN1_GSR_TBS_Pos (2UL)
3952#define CAN1_GSR_TBS_Msk (0x4UL)
3953#define CAN1_GSR_TCS_Pos (3UL)
3954#define CAN1_GSR_TCS_Msk (0x8UL)
3955#define CAN1_GSR_RS_Pos (4UL)
3956#define CAN1_GSR_RS_Msk (0x10UL)
3957#define CAN1_GSR_TS_Pos (5UL)
3958#define CAN1_GSR_TS_Msk (0x20UL)
3959#define CAN1_GSR_ES_Pos (6UL)
3960#define CAN1_GSR_ES_Msk (0x40UL)
3961#define CAN1_GSR_BS_Pos (7UL)
3962#define CAN1_GSR_BS_Msk (0x80UL)
3963#define CAN1_GSR_RXERR_Pos (16UL)
3964#define CAN1_GSR_RXERR_Msk (0xff0000UL)
3965#define CAN1_GSR_TXERR_Pos (24UL)
3966#define CAN1_GSR_TXERR_Msk (0xff000000UL)
3967/* ========================================================== ICR ========================================================== */
3968#define CAN1_ICR_RI_Pos (0UL)
3969#define CAN1_ICR_RI_Msk (0x1UL)
3970#define CAN1_ICR_TI1_Pos (1UL)
3971#define CAN1_ICR_TI1_Msk (0x2UL)
3972#define CAN1_ICR_EI_Pos (2UL)
3973#define CAN1_ICR_EI_Msk (0x4UL)
3974#define CAN1_ICR_DOI_Pos (3UL)
3975#define CAN1_ICR_DOI_Msk (0x8UL)
3976#define CAN1_ICR_WUI_Pos (4UL)
3977#define CAN1_ICR_WUI_Msk (0x10UL)
3978#define CAN1_ICR_EPI_Pos (5UL)
3979#define CAN1_ICR_EPI_Msk (0x20UL)
3980#define CAN1_ICR_ALI_Pos (6UL)
3981#define CAN1_ICR_ALI_Msk (0x40UL)
3982#define CAN1_ICR_BEI_Pos (7UL)
3983#define CAN1_ICR_BEI_Msk (0x80UL)
3984#define CAN1_ICR_IDI_Pos (8UL)
3985#define CAN1_ICR_IDI_Msk (0x100UL)
3986#define CAN1_ICR_TI2_Pos (9UL)
3987#define CAN1_ICR_TI2_Msk (0x200UL)
3988#define CAN1_ICR_TI3_Pos (10UL)
3989#define CAN1_ICR_TI3_Msk (0x400UL)
3990#define CAN1_ICR_ERRBIT4_0_Pos (16UL)
3991#define CAN1_ICR_ERRBIT4_0_Msk (0x1f0000UL)
3992#define CAN1_ICR_ERRDIR_Pos (21UL)
3993#define CAN1_ICR_ERRDIR_Msk (0x200000UL)
3994#define CAN1_ICR_ERRC1_0_Pos (22UL)
3995#define CAN1_ICR_ERRC1_0_Msk (0xc00000UL)
3996#define CAN1_ICR_ALCBIT_Pos (24UL)
3997#define CAN1_ICR_ALCBIT_Msk (0xff000000UL)
3998/* ========================================================== IER ========================================================== */
3999#define CAN1_IER_RIE_Pos (0UL)
4000#define CAN1_IER_RIE_Msk (0x1UL)
4001#define CAN1_IER_TIE1_Pos (1UL)
4002#define CAN1_IER_TIE1_Msk (0x2UL)
4003#define CAN1_IER_EIE_Pos (2UL)
4004#define CAN1_IER_EIE_Msk (0x4UL)
4005#define CAN1_IER_DOIE_Pos (3UL)
4006#define CAN1_IER_DOIE_Msk (0x8UL)
4007#define CAN1_IER_WUIE_Pos (4UL)
4008#define CAN1_IER_WUIE_Msk (0x10UL)
4009#define CAN1_IER_EPIE_Pos (5UL)
4010#define CAN1_IER_EPIE_Msk (0x20UL)
4011#define CAN1_IER_ALIE_Pos (6UL)
4012#define CAN1_IER_ALIE_Msk (0x40UL)
4013#define CAN1_IER_BEIE_Pos (7UL)
4014#define CAN1_IER_BEIE_Msk (0x80UL)
4015#define CAN1_IER_IDIE_Pos (8UL)
4016#define CAN1_IER_IDIE_Msk (0x100UL)
4017#define CAN1_IER_TIE2_Pos (9UL)
4018#define CAN1_IER_TIE2_Msk (0x200UL)
4019#define CAN1_IER_TIE3_Pos (10UL)
4020#define CAN1_IER_TIE3_Msk (0x400UL)
4021/* ========================================================== BTR ========================================================== */
4022#define CAN1_BTR_BRP_Pos (0UL)
4023#define CAN1_BTR_BRP_Msk (0x3ffUL)
4024#define CAN1_BTR_SJW_Pos (14UL)
4025#define CAN1_BTR_SJW_Msk (0xc000UL)
4026#define CAN1_BTR_TESG1_Pos (16UL)
4027#define CAN1_BTR_TESG1_Msk (0xf0000UL)
4028#define CAN1_BTR_TESG2_Pos (20UL)
4029#define CAN1_BTR_TESG2_Msk (0x700000UL)
4030#define CAN1_BTR_SAM_Pos (23UL)
4031#define CAN1_BTR_SAM_Msk (0x800000UL)
4032/* ========================================================== EWL ========================================================== */
4033#define CAN1_EWL_EWL_Pos (0UL)
4034#define CAN1_EWL_EWL_Msk (0xffUL)
4035/* ========================================================== SR =========================================================== */
4036#define CAN1_SR_RBS_1_Pos (0UL)
4037#define CAN1_SR_RBS_1_Msk (0x1UL)
4038#define CAN1_SR_DOS_1_Pos (1UL)
4039#define CAN1_SR_DOS_1_Msk (0x2UL)
4040#define CAN1_SR_TBS1_1_Pos (2UL)
4041#define CAN1_SR_TBS1_1_Msk (0x4UL)
4042#define CAN1_SR_TCS1_1_Pos (3UL)
4043#define CAN1_SR_TCS1_1_Msk (0x8UL)
4044#define CAN1_SR_RS_1_Pos (4UL)
4045#define CAN1_SR_RS_1_Msk (0x10UL)
4046#define CAN1_SR_TS1_1_Pos (5UL)
4047#define CAN1_SR_TS1_1_Msk (0x20UL)
4048#define CAN1_SR_ES_1_Pos (6UL)
4049#define CAN1_SR_ES_1_Msk (0x40UL)
4050#define CAN1_SR_BS_1_Pos (7UL)
4051#define CAN1_SR_BS_1_Msk (0x80UL)
4052#define CAN1_SR_RBS_2_Pos (8UL)
4053#define CAN1_SR_RBS_2_Msk (0x100UL)
4054#define CAN1_SR_DOS_2_Pos (9UL)
4055#define CAN1_SR_DOS_2_Msk (0x200UL)
4056#define CAN1_SR_TBS2_2_Pos (10UL)
4057#define CAN1_SR_TBS2_2_Msk (0x400UL)
4058#define CAN1_SR_TCS2_2_Pos (11UL)
4059#define CAN1_SR_TCS2_2_Msk (0x800UL)
4060#define CAN1_SR_RS_2_Pos (12UL)
4061#define CAN1_SR_RS_2_Msk (0x1000UL)
4062#define CAN1_SR_TS2_2_Pos (13UL)
4063#define CAN1_SR_TS2_2_Msk (0x2000UL)
4064#define CAN1_SR_ES_2_Pos (14UL)
4065#define CAN1_SR_ES_2_Msk (0x4000UL)
4066#define CAN1_SR_BS_2_Pos (15UL)
4067#define CAN1_SR_BS_2_Msk (0x8000UL)
4068#define CAN1_SR_RBS_3_Pos (16UL)
4069#define CAN1_SR_RBS_3_Msk (0x10000UL)
4070#define CAN1_SR_DOS_3_Pos (17UL)
4071#define CAN1_SR_DOS_3_Msk (0x20000UL)
4072#define CAN1_SR_TBS3_3_Pos (18UL)
4073#define CAN1_SR_TBS3_3_Msk (0x40000UL)
4074#define CAN1_SR_TCS3_3_Pos (19UL)
4075#define CAN1_SR_TCS3_3_Msk (0x80000UL)
4076#define CAN1_SR_RS_3_Pos (20UL)
4077#define CAN1_SR_RS_3_Msk (0x100000UL)
4078#define CAN1_SR_TS3_3_Pos (21UL)
4079#define CAN1_SR_TS3_3_Msk (0x200000UL)
4080#define CAN1_SR_ES_3_Pos (22UL)
4081#define CAN1_SR_ES_3_Msk (0x400000UL)
4082#define CAN1_SR_BS_3_Pos (23UL)
4083#define CAN1_SR_BS_3_Msk (0x800000UL)
4084/* ========================================================== RFS ========================================================== */
4085#define CAN1_RFS_IDINDEX_Pos (0UL)
4086#define CAN1_RFS_IDINDEX_Msk (0x3ffUL)
4087#define CAN1_RFS_BP_Pos (10UL)
4088#define CAN1_RFS_BP_Msk (0x400UL)
4089#define CAN1_RFS_DLC_Pos (16UL)
4090#define CAN1_RFS_DLC_Msk (0xf0000UL)
4091#define CAN1_RFS_RTR_Pos (30UL)
4092#define CAN1_RFS_RTR_Msk (0x40000000UL)
4093#define CAN1_RFS_FF_Pos (31UL)
4094#define CAN1_RFS_FF_Msk (0x80000000UL)
4095/* ========================================================== RID ========================================================== */
4096#define CAN1_RID_ID_Pos (0UL)
4097#define CAN1_RID_ID_Msk (0x7ffUL)
4098/* ========================================================== RDA ========================================================== */
4099#define CAN1_RDA_DATA1_Pos (0UL)
4100#define CAN1_RDA_DATA1_Msk (0xffUL)
4101#define CAN1_RDA_DATA2_Pos (8UL)
4102#define CAN1_RDA_DATA2_Msk (0xff00UL)
4103#define CAN1_RDA_DATA3_Pos (16UL)
4104#define CAN1_RDA_DATA3_Msk (0xff0000UL)
4105#define CAN1_RDA_DATA4_Pos (24UL)
4106#define CAN1_RDA_DATA4_Msk (0xff000000UL)
4107/* ========================================================== RDB ========================================================== */
4108#define CAN1_RDB_DATA5_Pos (0UL)
4109#define CAN1_RDB_DATA5_Msk (0xffUL)
4110#define CAN1_RDB_DATA6_Pos (8UL)
4111#define CAN1_RDB_DATA6_Msk (0xff00UL)
4112#define CAN1_RDB_DATA7_Pos (16UL)
4113#define CAN1_RDB_DATA7_Msk (0xff0000UL)
4114#define CAN1_RDB_DATA8_Pos (24UL)
4115#define CAN1_RDB_DATA8_Msk (0xff000000UL)
4116/* ========================================================= TFI1 ========================================================== */
4117#define CAN1_TFI1_PRIO_Pos (0UL)
4118#define CAN1_TFI1_PRIO_Msk (0xffUL)
4119#define CAN1_TFI1_DLC_Pos (16UL)
4120#define CAN1_TFI1_DLC_Msk (0xf0000UL)
4121#define CAN1_TFI1_RTR_Pos (30UL)
4122#define CAN1_TFI1_RTR_Msk (0x40000000UL)
4123#define CAN1_TFI1_FF_Pos (31UL)
4124#define CAN1_TFI1_FF_Msk (0x80000000UL)
4125/* ========================================================= TFI2 ========================================================== */
4126#define CAN1_TFI2_PRIO_Pos (0UL)
4127#define CAN1_TFI2_PRIO_Msk (0xffUL)
4128#define CAN1_TFI2_DLC_Pos (16UL)
4129#define CAN1_TFI2_DLC_Msk (0xf0000UL)
4130#define CAN1_TFI2_RTR_Pos (30UL)
4131#define CAN1_TFI2_RTR_Msk (0x40000000UL)
4132#define CAN1_TFI2_FF_Pos (31UL)
4133#define CAN1_TFI2_FF_Msk (0x80000000UL)
4134/* ========================================================= TFI3 ========================================================== */
4135#define CAN1_TFI3_PRIO_Pos (0UL)
4136#define CAN1_TFI3_PRIO_Msk (0xffUL)
4137#define CAN1_TFI3_DLC_Pos (16UL)
4138#define CAN1_TFI3_DLC_Msk (0xf0000UL)
4139#define CAN1_TFI3_RTR_Pos (30UL)
4140#define CAN1_TFI3_RTR_Msk (0x40000000UL)
4141#define CAN1_TFI3_FF_Pos (31UL)
4142#define CAN1_TFI3_FF_Msk (0x80000000UL)
4143/* ========================================================= TID1 ========================================================== */
4144#define CAN1_TID1_ID_Pos (0UL)
4145#define CAN1_TID1_ID_Msk (0x7ffUL)
4146/* ========================================================= TID2 ========================================================== */
4147#define CAN1_TID2_ID_Pos (0UL)
4148#define CAN1_TID2_ID_Msk (0x7ffUL)
4149/* ========================================================= TID3 ========================================================== */
4150#define CAN1_TID3_ID_Pos (0UL)
4151#define CAN1_TID3_ID_Msk (0x7ffUL)
4152/* ========================================================= TDA1 ========================================================== */
4153#define CAN1_TDA1_DATA1_Pos (0UL)
4154#define CAN1_TDA1_DATA1_Msk (0xffUL)
4155#define CAN1_TDA1_DATA2_Pos (8UL)
4156#define CAN1_TDA1_DATA2_Msk (0xff00UL)
4157#define CAN1_TDA1_DATA3_Pos (16UL)
4158#define CAN1_TDA1_DATA3_Msk (0xff0000UL)
4159#define CAN1_TDA1_DATA4_Pos (24UL)
4160#define CAN1_TDA1_DATA4_Msk (0xff000000UL)
4161/* ========================================================= TDA2 ========================================================== */
4162#define CAN1_TDA2_DATA1_Pos (0UL)
4163#define CAN1_TDA2_DATA1_Msk (0xffUL)
4164#define CAN1_TDA2_DATA2_Pos (8UL)
4165#define CAN1_TDA2_DATA2_Msk (0xff00UL)
4166#define CAN1_TDA2_DATA3_Pos (16UL)
4167#define CAN1_TDA2_DATA3_Msk (0xff0000UL)
4168#define CAN1_TDA2_DATA4_Pos (24UL)
4169#define CAN1_TDA2_DATA4_Msk (0xff000000UL)
4170/* ========================================================= TDA3 ========================================================== */
4171#define CAN1_TDA3_DATA1_Pos (0UL)
4172#define CAN1_TDA3_DATA1_Msk (0xffUL)
4173#define CAN1_TDA3_DATA2_Pos (8UL)
4174#define CAN1_TDA3_DATA2_Msk (0xff00UL)
4175#define CAN1_TDA3_DATA3_Pos (16UL)
4176#define CAN1_TDA3_DATA3_Msk (0xff0000UL)
4177#define CAN1_TDA3_DATA4_Pos (24UL)
4178#define CAN1_TDA3_DATA4_Msk (0xff000000UL)
4179/* ========================================================= TDB1 ========================================================== */
4180#define CAN1_TDB1_DATA5_Pos (0UL)
4181#define CAN1_TDB1_DATA5_Msk (0xffUL)
4182#define CAN1_TDB1_DATA6_Pos (8UL)
4183#define CAN1_TDB1_DATA6_Msk (0xff00UL)
4184#define CAN1_TDB1_DATA7_Pos (16UL)
4185#define CAN1_TDB1_DATA7_Msk (0xff0000UL)
4186#define CAN1_TDB1_DATA8_Pos (24UL)
4187#define CAN1_TDB1_DATA8_Msk (0xff000000UL)
4188/* ========================================================= TDB2 ========================================================== */
4189#define CAN1_TDB2_DATA5_Pos (0UL)
4190#define CAN1_TDB2_DATA5_Msk (0xffUL)
4191#define CAN1_TDB2_DATA6_Pos (8UL)
4192#define CAN1_TDB2_DATA6_Msk (0xff00UL)
4193#define CAN1_TDB2_DATA7_Pos (16UL)
4194#define CAN1_TDB2_DATA7_Msk (0xff0000UL)
4195#define CAN1_TDB2_DATA8_Pos (24UL)
4196#define CAN1_TDB2_DATA8_Msk (0xff000000UL)
4197/* ========================================================= TDB3 ========================================================== */
4198#define CAN1_TDB3_DATA5_Pos (0UL)
4199#define CAN1_TDB3_DATA5_Msk (0xffUL)
4200#define CAN1_TDB3_DATA6_Pos (8UL)
4201#define CAN1_TDB3_DATA6_Msk (0xff00UL)
4202#define CAN1_TDB3_DATA7_Pos (16UL)
4203#define CAN1_TDB3_DATA7_Msk (0xff0000UL)
4204#define CAN1_TDB3_DATA8_Pos (24UL)
4205#define CAN1_TDB3_DATA8_Msk (0xff000000UL)
4208/* =========================================================================================================================== */
4209/* ================ LPC_CAN2 ================ */
4210/* =========================================================================================================================== */
4211
4212/* ========================================================== MOD ========================================================== */
4213#define CAN2_MOD_RM_Pos (0UL)
4214#define CAN2_MOD_RM_Msk (0x1UL)
4215#define CAN2_MOD_LOM_Pos (1UL)
4216#define CAN2_MOD_LOM_Msk (0x2UL)
4217#define CAN2_MOD_STM_Pos (2UL)
4218#define CAN2_MOD_STM_Msk (0x4UL)
4219#define CAN2_MOD_TPM_Pos (3UL)
4220#define CAN2_MOD_TPM_Msk (0x8UL)
4221#define CAN2_MOD_SM_Pos (4UL)
4222#define CAN2_MOD_SM_Msk (0x10UL)
4223#define CAN2_MOD_RPM_Pos (5UL)
4224#define CAN2_MOD_RPM_Msk (0x20UL)
4225#define CAN2_MOD_TM_Pos (7UL)
4226#define CAN2_MOD_TM_Msk (0x80UL)
4227/* ========================================================== CMR ========================================================== */
4228#define CAN2_CMR_TR_Pos (0UL)
4229#define CAN2_CMR_TR_Msk (0x1UL)
4230#define CAN2_CMR_AT_Pos (1UL)
4231#define CAN2_CMR_AT_Msk (0x2UL)
4232#define CAN2_CMR_RRB_Pos (2UL)
4233#define CAN2_CMR_RRB_Msk (0x4UL)
4234#define CAN2_CMR_CDO_Pos (3UL)
4235#define CAN2_CMR_CDO_Msk (0x8UL)
4236#define CAN2_CMR_SRR_Pos (4UL)
4237#define CAN2_CMR_SRR_Msk (0x10UL)
4238#define CAN2_CMR_STB1_Pos (5UL)
4239#define CAN2_CMR_STB1_Msk (0x20UL)
4240#define CAN2_CMR_STB2_Pos (6UL)
4241#define CAN2_CMR_STB2_Msk (0x40UL)
4242#define CAN2_CMR_STB3_Pos (7UL)
4243#define CAN2_CMR_STB3_Msk (0x80UL)
4244/* ========================================================== GSR ========================================================== */
4245#define CAN2_GSR_RBS_Pos (0UL)
4246#define CAN2_GSR_RBS_Msk (0x1UL)
4247#define CAN2_GSR_DOS_Pos (1UL)
4248#define CAN2_GSR_DOS_Msk (0x2UL)
4249#define CAN2_GSR_TBS_Pos (2UL)
4250#define CAN2_GSR_TBS_Msk (0x4UL)
4251#define CAN2_GSR_TCS_Pos (3UL)
4252#define CAN2_GSR_TCS_Msk (0x8UL)
4253#define CAN2_GSR_RS_Pos (4UL)
4254#define CAN2_GSR_RS_Msk (0x10UL)
4255#define CAN2_GSR_TS_Pos (5UL)
4256#define CAN2_GSR_TS_Msk (0x20UL)
4257#define CAN2_GSR_ES_Pos (6UL)
4258#define CAN2_GSR_ES_Msk (0x40UL)
4259#define CAN2_GSR_BS_Pos (7UL)
4260#define CAN2_GSR_BS_Msk (0x80UL)
4261#define CAN2_GSR_RXERR_Pos (16UL)
4262#define CAN2_GSR_RXERR_Msk (0xff0000UL)
4263#define CAN2_GSR_TXERR_Pos (24UL)
4264#define CAN2_GSR_TXERR_Msk (0xff000000UL)
4265/* ========================================================== ICR ========================================================== */
4266#define CAN2_ICR_RI_Pos (0UL)
4267#define CAN2_ICR_RI_Msk (0x1UL)
4268#define CAN2_ICR_TI1_Pos (1UL)
4269#define CAN2_ICR_TI1_Msk (0x2UL)
4270#define CAN2_ICR_EI_Pos (2UL)
4271#define CAN2_ICR_EI_Msk (0x4UL)
4272#define CAN2_ICR_DOI_Pos (3UL)
4273#define CAN2_ICR_DOI_Msk (0x8UL)
4274#define CAN2_ICR_WUI_Pos (4UL)
4275#define CAN2_ICR_WUI_Msk (0x10UL)
4276#define CAN2_ICR_EPI_Pos (5UL)
4277#define CAN2_ICR_EPI_Msk (0x20UL)
4278#define CAN2_ICR_ALI_Pos (6UL)
4279#define CAN2_ICR_ALI_Msk (0x40UL)
4280#define CAN2_ICR_BEI_Pos (7UL)
4281#define CAN2_ICR_BEI_Msk (0x80UL)
4282#define CAN2_ICR_IDI_Pos (8UL)
4283#define CAN2_ICR_IDI_Msk (0x100UL)
4284#define CAN2_ICR_TI2_Pos (9UL)
4285#define CAN2_ICR_TI2_Msk (0x200UL)
4286#define CAN2_ICR_TI3_Pos (10UL)
4287#define CAN2_ICR_TI3_Msk (0x400UL)
4288#define CAN2_ICR_ERRBIT4_0_Pos (16UL)
4289#define CAN2_ICR_ERRBIT4_0_Msk (0x1f0000UL)
4290#define CAN2_ICR_ERRDIR_Pos (21UL)
4291#define CAN2_ICR_ERRDIR_Msk (0x200000UL)
4292#define CAN2_ICR_ERRC1_0_Pos (22UL)
4293#define CAN2_ICR_ERRC1_0_Msk (0xc00000UL)
4294#define CAN2_ICR_ALCBIT_Pos (24UL)
4295#define CAN2_ICR_ALCBIT_Msk (0xff000000UL)
4296/* ========================================================== IER ========================================================== */
4297#define CAN2_IER_RIE_Pos (0UL)
4298#define CAN2_IER_RIE_Msk (0x1UL)
4299#define CAN2_IER_TIE1_Pos (1UL)
4300#define CAN2_IER_TIE1_Msk (0x2UL)
4301#define CAN2_IER_EIE_Pos (2UL)
4302#define CAN2_IER_EIE_Msk (0x4UL)
4303#define CAN2_IER_DOIE_Pos (3UL)
4304#define CAN2_IER_DOIE_Msk (0x8UL)
4305#define CAN2_IER_WUIE_Pos (4UL)
4306#define CAN2_IER_WUIE_Msk (0x10UL)
4307#define CAN2_IER_EPIE_Pos (5UL)
4308#define CAN2_IER_EPIE_Msk (0x20UL)
4309#define CAN2_IER_ALIE_Pos (6UL)
4310#define CAN2_IER_ALIE_Msk (0x40UL)
4311#define CAN2_IER_BEIE_Pos (7UL)
4312#define CAN2_IER_BEIE_Msk (0x80UL)
4313#define CAN2_IER_IDIE_Pos (8UL)
4314#define CAN2_IER_IDIE_Msk (0x100UL)
4315#define CAN2_IER_TIE2_Pos (9UL)
4316#define CAN2_IER_TIE2_Msk (0x200UL)
4317#define CAN2_IER_TIE3_Pos (10UL)
4318#define CAN2_IER_TIE3_Msk (0x400UL)
4319/* ========================================================== BTR ========================================================== */
4320#define CAN2_BTR_BRP_Pos (0UL)
4321#define CAN2_BTR_BRP_Msk (0x3ffUL)
4322#define CAN2_BTR_SJW_Pos (14UL)
4323#define CAN2_BTR_SJW_Msk (0xc000UL)
4324#define CAN2_BTR_TESG1_Pos (16UL)
4325#define CAN2_BTR_TESG1_Msk (0xf0000UL)
4326#define CAN2_BTR_TESG2_Pos (20UL)
4327#define CAN2_BTR_TESG2_Msk (0x700000UL)
4328#define CAN2_BTR_SAM_Pos (23UL)
4329#define CAN2_BTR_SAM_Msk (0x800000UL)
4330/* ========================================================== EWL ========================================================== */
4331#define CAN2_EWL_EWL_Pos (0UL)
4332#define CAN2_EWL_EWL_Msk (0xffUL)
4333/* ========================================================== SR =========================================================== */
4334#define CAN2_SR_RBS_1_Pos (0UL)
4335#define CAN2_SR_RBS_1_Msk (0x1UL)
4336#define CAN2_SR_DOS_1_Pos (1UL)
4337#define CAN2_SR_DOS_1_Msk (0x2UL)
4338#define CAN2_SR_TBS1_1_Pos (2UL)
4339#define CAN2_SR_TBS1_1_Msk (0x4UL)
4340#define CAN2_SR_TCS1_1_Pos (3UL)
4341#define CAN2_SR_TCS1_1_Msk (0x8UL)
4342#define CAN2_SR_RS_1_Pos (4UL)
4343#define CAN2_SR_RS_1_Msk (0x10UL)
4344#define CAN2_SR_TS1_1_Pos (5UL)
4345#define CAN2_SR_TS1_1_Msk (0x20UL)
4346#define CAN2_SR_ES_1_Pos (6UL)
4347#define CAN2_SR_ES_1_Msk (0x40UL)
4348#define CAN2_SR_BS_1_Pos (7UL)
4349#define CAN2_SR_BS_1_Msk (0x80UL)
4350#define CAN2_SR_RBS_2_Pos (8UL)
4351#define CAN2_SR_RBS_2_Msk (0x100UL)
4352#define CAN2_SR_DOS_2_Pos (9UL)
4353#define CAN2_SR_DOS_2_Msk (0x200UL)
4354#define CAN2_SR_TBS2_2_Pos (10UL)
4355#define CAN2_SR_TBS2_2_Msk (0x400UL)
4356#define CAN2_SR_TCS2_2_Pos (11UL)
4357#define CAN2_SR_TCS2_2_Msk (0x800UL)
4358#define CAN2_SR_RS_2_Pos (12UL)
4359#define CAN2_SR_RS_2_Msk (0x1000UL)
4360#define CAN2_SR_TS2_2_Pos (13UL)
4361#define CAN2_SR_TS2_2_Msk (0x2000UL)
4362#define CAN2_SR_ES_2_Pos (14UL)
4363#define CAN2_SR_ES_2_Msk (0x4000UL)
4364#define CAN2_SR_BS_2_Pos (15UL)
4365#define CAN2_SR_BS_2_Msk (0x8000UL)
4366#define CAN2_SR_RBS_3_Pos (16UL)
4367#define CAN2_SR_RBS_3_Msk (0x10000UL)
4368#define CAN2_SR_DOS_3_Pos (17UL)
4369#define CAN2_SR_DOS_3_Msk (0x20000UL)
4370#define CAN2_SR_TBS3_3_Pos (18UL)
4371#define CAN2_SR_TBS3_3_Msk (0x40000UL)
4372#define CAN2_SR_TCS3_3_Pos (19UL)
4373#define CAN2_SR_TCS3_3_Msk (0x80000UL)
4374#define CAN2_SR_RS_3_Pos (20UL)
4375#define CAN2_SR_RS_3_Msk (0x100000UL)
4376#define CAN2_SR_TS3_3_Pos (21UL)
4377#define CAN2_SR_TS3_3_Msk (0x200000UL)
4378#define CAN2_SR_ES_3_Pos (22UL)
4379#define CAN2_SR_ES_3_Msk (0x400000UL)
4380#define CAN2_SR_BS_3_Pos (23UL)
4381#define CAN2_SR_BS_3_Msk (0x800000UL)
4382/* ========================================================== RFS ========================================================== */
4383#define CAN2_RFS_IDINDEX_Pos (0UL)
4384#define CAN2_RFS_IDINDEX_Msk (0x3ffUL)
4385#define CAN2_RFS_BP_Pos (10UL)
4386#define CAN2_RFS_BP_Msk (0x400UL)
4387#define CAN2_RFS_DLC_Pos (16UL)
4388#define CAN2_RFS_DLC_Msk (0xf0000UL)
4389#define CAN2_RFS_RTR_Pos (30UL)
4390#define CAN2_RFS_RTR_Msk (0x40000000UL)
4391#define CAN2_RFS_FF_Pos (31UL)
4392#define CAN2_RFS_FF_Msk (0x80000000UL)
4393/* ========================================================== RID ========================================================== */
4394#define CAN2_RID_ID_Pos (0UL)
4395#define CAN2_RID_ID_Msk (0x7ffUL)
4396/* ========================================================== RDA ========================================================== */
4397#define CAN2_RDA_DATA1_Pos (0UL)
4398#define CAN2_RDA_DATA1_Msk (0xffUL)
4399#define CAN2_RDA_DATA2_Pos (8UL)
4400#define CAN2_RDA_DATA2_Msk (0xff00UL)
4401#define CAN2_RDA_DATA3_Pos (16UL)
4402#define CAN2_RDA_DATA3_Msk (0xff0000UL)
4403#define CAN2_RDA_DATA4_Pos (24UL)
4404#define CAN2_RDA_DATA4_Msk (0xff000000UL)
4405/* ========================================================== RDB ========================================================== */
4406#define CAN2_RDB_DATA5_Pos (0UL)
4407#define CAN2_RDB_DATA5_Msk (0xffUL)
4408#define CAN2_RDB_DATA6_Pos (8UL)
4409#define CAN2_RDB_DATA6_Msk (0xff00UL)
4410#define CAN2_RDB_DATA7_Pos (16UL)
4411#define CAN2_RDB_DATA7_Msk (0xff0000UL)
4412#define CAN2_RDB_DATA8_Pos (24UL)
4413#define CAN2_RDB_DATA8_Msk (0xff000000UL)
4414/* ========================================================= TFI1 ========================================================== */
4415#define CAN2_TFI1_PRIO_Pos (0UL)
4416#define CAN2_TFI1_PRIO_Msk (0xffUL)
4417#define CAN2_TFI1_DLC_Pos (16UL)
4418#define CAN2_TFI1_DLC_Msk (0xf0000UL)
4419#define CAN2_TFI1_RTR_Pos (30UL)
4420#define CAN2_TFI1_RTR_Msk (0x40000000UL)
4421#define CAN2_TFI1_FF_Pos (31UL)
4422#define CAN2_TFI1_FF_Msk (0x80000000UL)
4423/* ========================================================= TFI2 ========================================================== */
4424#define CAN2_TFI2_PRIO_Pos (0UL)
4425#define CAN2_TFI2_PRIO_Msk (0xffUL)
4426#define CAN2_TFI2_DLC_Pos (16UL)
4427#define CAN2_TFI2_DLC_Msk (0xf0000UL)
4428#define CAN2_TFI2_RTR_Pos (30UL)
4429#define CAN2_TFI2_RTR_Msk (0x40000000UL)
4430#define CAN2_TFI2_FF_Pos (31UL)
4431#define CAN2_TFI2_FF_Msk (0x80000000UL)
4432/* ========================================================= TFI3 ========================================================== */
4433#define CAN2_TFI3_PRIO_Pos (0UL)
4434#define CAN2_TFI3_PRIO_Msk (0xffUL)
4435#define CAN2_TFI3_DLC_Pos (16UL)
4436#define CAN2_TFI3_DLC_Msk (0xf0000UL)
4437#define CAN2_TFI3_RTR_Pos (30UL)
4438#define CAN2_TFI3_RTR_Msk (0x40000000UL)
4439#define CAN2_TFI3_FF_Pos (31UL)
4440#define CAN2_TFI3_FF_Msk (0x80000000UL)
4441/* ========================================================= TID1 ========================================================== */
4442#define CAN2_TID1_ID_Pos (0UL)
4443#define CAN2_TID1_ID_Msk (0x7ffUL)
4444/* ========================================================= TID2 ========================================================== */
4445#define CAN2_TID2_ID_Pos (0UL)
4446#define CAN2_TID2_ID_Msk (0x7ffUL)
4447/* ========================================================= TID3 ========================================================== */
4448#define CAN2_TID3_ID_Pos (0UL)
4449#define CAN2_TID3_ID_Msk (0x7ffUL)
4450/* ========================================================= TDA1 ========================================================== */
4451#define CAN2_TDA1_DATA1_Pos (0UL)
4452#define CAN2_TDA1_DATA1_Msk (0xffUL)
4453#define CAN2_TDA1_DATA2_Pos (8UL)
4454#define CAN2_TDA1_DATA2_Msk (0xff00UL)
4455#define CAN2_TDA1_DATA3_Pos (16UL)
4456#define CAN2_TDA1_DATA3_Msk (0xff0000UL)
4457#define CAN2_TDA1_DATA4_Pos (24UL)
4458#define CAN2_TDA1_DATA4_Msk (0xff000000UL)
4459/* ========================================================= TDA2 ========================================================== */
4460#define CAN2_TDA2_DATA1_Pos (0UL)
4461#define CAN2_TDA2_DATA1_Msk (0xffUL)
4462#define CAN2_TDA2_DATA2_Pos (8UL)
4463#define CAN2_TDA2_DATA2_Msk (0xff00UL)
4464#define CAN2_TDA2_DATA3_Pos (16UL)
4465#define CAN2_TDA2_DATA3_Msk (0xff0000UL)
4466#define CAN2_TDA2_DATA4_Pos (24UL)
4467#define CAN2_TDA2_DATA4_Msk (0xff000000UL)
4468/* ========================================================= TDA3 ========================================================== */
4469#define CAN2_TDA3_DATA1_Pos (0UL)
4470#define CAN2_TDA3_DATA1_Msk (0xffUL)
4471#define CAN2_TDA3_DATA2_Pos (8UL)
4472#define CAN2_TDA3_DATA2_Msk (0xff00UL)
4473#define CAN2_TDA3_DATA3_Pos (16UL)
4474#define CAN2_TDA3_DATA3_Msk (0xff0000UL)
4475#define CAN2_TDA3_DATA4_Pos (24UL)
4476#define CAN2_TDA3_DATA4_Msk (0xff000000UL)
4477/* ========================================================= TDB1 ========================================================== */
4478#define CAN2_TDB1_DATA5_Pos (0UL)
4479#define CAN2_TDB1_DATA5_Msk (0xffUL)
4480#define CAN2_TDB1_DATA6_Pos (8UL)
4481#define CAN2_TDB1_DATA6_Msk (0xff00UL)
4482#define CAN2_TDB1_DATA7_Pos (16UL)
4483#define CAN2_TDB1_DATA7_Msk (0xff0000UL)
4484#define CAN2_TDB1_DATA8_Pos (24UL)
4485#define CAN2_TDB1_DATA8_Msk (0xff000000UL)
4486/* ========================================================= TDB2 ========================================================== */
4487#define CAN2_TDB2_DATA5_Pos (0UL)
4488#define CAN2_TDB2_DATA5_Msk (0xffUL)
4489#define CAN2_TDB2_DATA6_Pos (8UL)
4490#define CAN2_TDB2_DATA6_Msk (0xff00UL)
4491#define CAN2_TDB2_DATA7_Pos (16UL)
4492#define CAN2_TDB2_DATA7_Msk (0xff0000UL)
4493#define CAN2_TDB2_DATA8_Pos (24UL)
4494#define CAN2_TDB2_DATA8_Msk (0xff000000UL)
4495/* ========================================================= TDB3 ========================================================== */
4496#define CAN2_TDB3_DATA5_Pos (0UL)
4497#define CAN2_TDB3_DATA5_Msk (0xffUL)
4498#define CAN2_TDB3_DATA6_Pos (8UL)
4499#define CAN2_TDB3_DATA6_Msk (0xff00UL)
4500#define CAN2_TDB3_DATA7_Pos (16UL)
4501#define CAN2_TDB3_DATA7_Msk (0xff0000UL)
4502#define CAN2_TDB3_DATA8_Pos (24UL)
4503#define CAN2_TDB3_DATA8_Msk (0xff000000UL)
4506/* =========================================================================================================================== */
4507/* ================ LPC_SSP0 ================ */
4508/* =========================================================================================================================== */
4509
4510/* ========================================================== CR0 ========================================================== */
4511#define SSP0_CR0_DSS_Pos (0UL)
4512#define SSP0_CR0_DSS_Msk (0xfUL)
4513#define SSP0_CR0_FRF_Pos (4UL)
4514#define SSP0_CR0_FRF_Msk (0x30UL)
4515#define SSP0_CR0_CPOL_Pos (6UL)
4516#define SSP0_CR0_CPOL_Msk (0x40UL)
4517#define SSP0_CR0_CPHA_Pos (7UL)
4518#define SSP0_CR0_CPHA_Msk (0x80UL)
4519#define SSP0_CR0_SCR_Pos (8UL)
4520#define SSP0_CR0_SCR_Msk (0xff00UL)
4521/* ========================================================== CR1 ========================================================== */
4522#define SSP0_CR1_LBM_Pos (0UL)
4523#define SSP0_CR1_LBM_Msk (0x1UL)
4524#define SSP0_CR1_SSE_Pos (1UL)
4525#define SSP0_CR1_SSE_Msk (0x2UL)
4526#define SSP0_CR1_MS_Pos (2UL)
4527#define SSP0_CR1_MS_Msk (0x4UL)
4528#define SSP0_CR1_SOD_Pos (3UL)
4529#define SSP0_CR1_SOD_Msk (0x8UL)
4530/* ========================================================== DR =========================================================== */
4531#define SSP0_DR_DATA_Pos (0UL)
4532#define SSP0_DR_DATA_Msk (0xffffUL)
4533/* ========================================================== SR =========================================================== */
4534#define SSP0_SR_TFE_Pos (0UL)
4535#define SSP0_SR_TFE_Msk (0x1UL)
4536#define SSP0_SR_TNF_Pos (1UL)
4537#define SSP0_SR_TNF_Msk (0x2UL)
4538#define SSP0_SR_RNE_Pos (2UL)
4539#define SSP0_SR_RNE_Msk (0x4UL)
4540#define SSP0_SR_RFF_Pos (3UL)
4541#define SSP0_SR_RFF_Msk (0x8UL)
4542#define SSP0_SR_BSY_Pos (4UL)
4543#define SSP0_SR_BSY_Msk (0x10UL)
4544/* ========================================================= CPSR ========================================================== */
4545#define SSP0_CPSR_CPSDVSR_Pos (0UL)
4546#define SSP0_CPSR_CPSDVSR_Msk (0xffUL)
4547/* ========================================================= IMSC ========================================================== */
4548#define SSP0_IMSC_RORIM_Pos (0UL)
4549#define SSP0_IMSC_RORIM_Msk (0x1UL)
4550#define SSP0_IMSC_RTIM_Pos (1UL)
4551#define SSP0_IMSC_RTIM_Msk (0x2UL)
4552#define SSP0_IMSC_RXIM_Pos (2UL)
4553#define SSP0_IMSC_RXIM_Msk (0x4UL)
4554#define SSP0_IMSC_TXIM_Pos (3UL)
4555#define SSP0_IMSC_TXIM_Msk (0x8UL)
4556/* ========================================================== RIS ========================================================== */
4557#define SSP0_RIS_RORRIS_Pos (0UL)
4558#define SSP0_RIS_RORRIS_Msk (0x1UL)
4559#define SSP0_RIS_RTRIS_Pos (1UL)
4560#define SSP0_RIS_RTRIS_Msk (0x2UL)
4561#define SSP0_RIS_RXRIS_Pos (2UL)
4562#define SSP0_RIS_RXRIS_Msk (0x4UL)
4563#define SSP0_RIS_TXRIS_Pos (3UL)
4564#define SSP0_RIS_TXRIS_Msk (0x8UL)
4565/* ========================================================== MIS ========================================================== */
4566#define SSP0_MIS_RORMIS_Pos (0UL)
4567#define SSP0_MIS_RORMIS_Msk (0x1UL)
4568#define SSP0_MIS_RTMIS_Pos (1UL)
4569#define SSP0_MIS_RTMIS_Msk (0x2UL)
4570#define SSP0_MIS_RXMIS_Pos (2UL)
4571#define SSP0_MIS_RXMIS_Msk (0x4UL)
4572#define SSP0_MIS_TXMIS_Pos (3UL)
4573#define SSP0_MIS_TXMIS_Msk (0x8UL)
4574/* ========================================================== ICR ========================================================== */
4575#define SSP0_ICR_RORIC_Pos (0UL)
4576#define SSP0_ICR_RORIC_Msk (0x1UL)
4577#define SSP0_ICR_RTIC_Pos (1UL)
4578#define SSP0_ICR_RTIC_Msk (0x2UL)
4579/* ========================================================= DMACR ========================================================= */
4580#define SSP0_DMACR_RXDMAE_Pos (0UL)
4581#define SSP0_DMACR_RXDMAE_Msk (0x1UL)
4582#define SSP0_DMACR_TXDMAE_Pos (1UL)
4583#define SSP0_DMACR_TXDMAE_Msk (0x2UL)
4586/* =========================================================================================================================== */
4587/* ================ LPC_DAC ================ */
4588/* =========================================================================================================================== */
4589
4590/* ========================================================== CR =========================================================== */
4591#define DAC_CR_VALUE_Pos (6UL)
4592#define DAC_CR_VALUE_Msk (0xffc0UL)
4593#define DAC_CR_BIAS_Pos (16UL)
4594#define DAC_CR_BIAS_Msk (0x10000UL)
4595/* ========================================================= CTRL ========================================================== */
4596#define DAC_CTRL_INT_DMA_REQ_Pos (0UL)
4597#define DAC_CTRL_INT_DMA_REQ_Msk (0x1UL)
4598#define DAC_CTRL_DBLBUF_ENA_Pos (1UL)
4599#define DAC_CTRL_DBLBUF_ENA_Msk (0x2UL)
4600#define DAC_CTRL_CNT_ENA_Pos (2UL)
4601#define DAC_CTRL_CNT_ENA_Msk (0x4UL)
4602#define DAC_CTRL_DMA_ENA_Pos (3UL)
4603#define DAC_CTRL_DMA_ENA_Msk (0x8UL)
4604/* ======================================================== CNTVAL ========================================================= */
4605#define DAC_CNTVAL_VALUE_Pos (0UL)
4606#define DAC_CNTVAL_VALUE_Msk (0xffffUL)
4609/* =========================================================================================================================== */
4610/* ================ LPC_TIMER2 ================ */
4611/* =========================================================================================================================== */
4612
4613/* ========================================================== IR =========================================================== */
4614#define TIMER2_IR_MR0INT_Pos (0UL)
4615#define TIMER2_IR_MR0INT_Msk (0x1UL)
4616#define TIMER2_IR_MR1INT_Pos (1UL)
4617#define TIMER2_IR_MR1INT_Msk (0x2UL)
4618#define TIMER2_IR_MR2INT_Pos (2UL)
4619#define TIMER2_IR_MR2INT_Msk (0x4UL)
4620#define TIMER2_IR_MR3INT_Pos (3UL)
4621#define TIMER2_IR_MR3INT_Msk (0x8UL)
4622#define TIMER2_IR_CR0INT_Pos (4UL)
4623#define TIMER2_IR_CR0INT_Msk (0x10UL)
4624#define TIMER2_IR_CR1INT_Pos (5UL)
4625#define TIMER2_IR_CR1INT_Msk (0x20UL)
4626/* ========================================================== TCR ========================================================== */
4627#define TIMER2_TCR_CEN_Pos (0UL)
4628#define TIMER2_TCR_CEN_Msk (0x1UL)
4629#define TIMER2_TCR_CRST_Pos (1UL)
4630#define TIMER2_TCR_CRST_Msk (0x2UL)
4631/* ========================================================== TC =========================================================== */
4632#define TIMER2_TC_TC_Pos (0UL)
4633#define TIMER2_TC_TC_Msk (0xffffffffUL)
4634/* ========================================================== PR =========================================================== */
4635#define TIMER2_PR_PM_Pos (0UL)
4636#define TIMER2_PR_PM_Msk (0xffffffffUL)
4637/* ========================================================== PC =========================================================== */
4638#define TIMER2_PC_PC_Pos (0UL)
4639#define TIMER2_PC_PC_Msk (0xffffffffUL)
4640/* ========================================================== MCR ========================================================== */
4641#define TIMER2_MCR_MR0I_Pos (0UL)
4642#define TIMER2_MCR_MR0I_Msk (0x1UL)
4643#define TIMER2_MCR_MR0R_Pos (1UL)
4644#define TIMER2_MCR_MR0R_Msk (0x2UL)
4645#define TIMER2_MCR_MR0S_Pos (2UL)
4646#define TIMER2_MCR_MR0S_Msk (0x4UL)
4647#define TIMER2_MCR_MR1I_Pos (3UL)
4648#define TIMER2_MCR_MR1I_Msk (0x8UL)
4649#define TIMER2_MCR_MR1R_Pos (4UL)
4650#define TIMER2_MCR_MR1R_Msk (0x10UL)
4651#define TIMER2_MCR_MR1S_Pos (5UL)
4652#define TIMER2_MCR_MR1S_Msk (0x20UL)
4653#define TIMER2_MCR_MR2I_Pos (6UL)
4654#define TIMER2_MCR_MR2I_Msk (0x40UL)
4655#define TIMER2_MCR_MR2R_Pos (7UL)
4656#define TIMER2_MCR_MR2R_Msk (0x80UL)
4657#define TIMER2_MCR_MR2S_Pos (8UL)
4658#define TIMER2_MCR_MR2S_Msk (0x100UL)
4659#define TIMER2_MCR_MR3I_Pos (9UL)
4660#define TIMER2_MCR_MR3I_Msk (0x200UL)
4661#define TIMER2_MCR_MR3R_Pos (10UL)
4662#define TIMER2_MCR_MR3R_Msk (0x400UL)
4663#define TIMER2_MCR_MR3S_Pos (11UL)
4664#define TIMER2_MCR_MR3S_Msk (0x800UL)
4665/* ========================================================== CCR ========================================================== */
4666#define TIMER2_CCR_CAP0RE_Pos (0UL)
4667#define TIMER2_CCR_CAP0RE_Msk (0x1UL)
4668#define TIMER2_CCR_CAP0FE_Pos (1UL)
4669#define TIMER2_CCR_CAP0FE_Msk (0x2UL)
4670#define TIMER2_CCR_CAP0I_Pos (2UL)
4671#define TIMER2_CCR_CAP0I_Msk (0x4UL)
4672#define TIMER2_CCR_CAP1RE_Pos (3UL)
4673#define TIMER2_CCR_CAP1RE_Msk (0x8UL)
4674#define TIMER2_CCR_CAP1FE_Pos (4UL)
4675#define TIMER2_CCR_CAP1FE_Msk (0x10UL)
4676#define TIMER2_CCR_CAP1I_Pos (5UL)
4677#define TIMER2_CCR_CAP1I_Msk (0x20UL)
4678/* ========================================================== EMR ========================================================== */
4679#define TIMER2_EMR_EM0_Pos (0UL)
4680#define TIMER2_EMR_EM0_Msk (0x1UL)
4681#define TIMER2_EMR_EM1_Pos (1UL)
4682#define TIMER2_EMR_EM1_Msk (0x2UL)
4683#define TIMER2_EMR_EM2_Pos (2UL)
4684#define TIMER2_EMR_EM2_Msk (0x4UL)
4685#define TIMER2_EMR_EM3_Pos (3UL)
4686#define TIMER2_EMR_EM3_Msk (0x8UL)
4687#define TIMER2_EMR_EMC0_Pos (4UL)
4688#define TIMER2_EMR_EMC0_Msk (0x30UL)
4689#define TIMER2_EMR_EMC1_Pos (6UL)
4690#define TIMER2_EMR_EMC1_Msk (0xc0UL)
4691#define TIMER2_EMR_EMC2_Pos (8UL)
4692#define TIMER2_EMR_EMC2_Msk (0x300UL)
4693#define TIMER2_EMR_EMC3_Pos (10UL)
4694#define TIMER2_EMR_EMC3_Msk (0xc00UL)
4695/* ========================================================= CTCR ========================================================== */
4696#define TIMER2_CTCR_CTMODE_Pos (0UL)
4697#define TIMER2_CTCR_CTMODE_Msk (0x3UL)
4698#define TIMER2_CTCR_CINSEL_Pos (2UL)
4699#define TIMER2_CTCR_CINSEL_Msk (0xcUL)
4702/* =========================================================================================================================== */
4703/* ================ LPC_TIMER3 ================ */
4704/* =========================================================================================================================== */
4705
4706/* ========================================================== IR =========================================================== */
4707#define TIMER3_IR_MR0INT_Pos (0UL)
4708#define TIMER3_IR_MR0INT_Msk (0x1UL)
4709#define TIMER3_IR_MR1INT_Pos (1UL)
4710#define TIMER3_IR_MR1INT_Msk (0x2UL)
4711#define TIMER3_IR_MR2INT_Pos (2UL)
4712#define TIMER3_IR_MR2INT_Msk (0x4UL)
4713#define TIMER3_IR_MR3INT_Pos (3UL)
4714#define TIMER3_IR_MR3INT_Msk (0x8UL)
4715#define TIMER3_IR_CR0INT_Pos (4UL)
4716#define TIMER3_IR_CR0INT_Msk (0x10UL)
4717#define TIMER3_IR_CR1INT_Pos (5UL)
4718#define TIMER3_IR_CR1INT_Msk (0x20UL)
4719/* ========================================================== TCR ========================================================== */
4720#define TIMER3_TCR_CEN_Pos (0UL)
4721#define TIMER3_TCR_CEN_Msk (0x1UL)
4722#define TIMER3_TCR_CRST_Pos (1UL)
4723#define TIMER3_TCR_CRST_Msk (0x2UL)
4724/* ========================================================== TC =========================================================== */
4725#define TIMER3_TC_TC_Pos (0UL)
4726#define TIMER3_TC_TC_Msk (0xffffffffUL)
4727/* ========================================================== PR =========================================================== */
4728#define TIMER3_PR_PM_Pos (0UL)
4729#define TIMER3_PR_PM_Msk (0xffffffffUL)
4730/* ========================================================== PC =========================================================== */
4731#define TIMER3_PC_PC_Pos (0UL)
4732#define TIMER3_PC_PC_Msk (0xffffffffUL)
4733/* ========================================================== MCR ========================================================== */
4734#define TIMER3_MCR_MR0I_Pos (0UL)
4735#define TIMER3_MCR_MR0I_Msk (0x1UL)
4736#define TIMER3_MCR_MR0R_Pos (1UL)
4737#define TIMER3_MCR_MR0R_Msk (0x2UL)
4738#define TIMER3_MCR_MR0S_Pos (2UL)
4739#define TIMER3_MCR_MR0S_Msk (0x4UL)
4740#define TIMER3_MCR_MR1I_Pos (3UL)
4741#define TIMER3_MCR_MR1I_Msk (0x8UL)
4742#define TIMER3_MCR_MR1R_Pos (4UL)
4743#define TIMER3_MCR_MR1R_Msk (0x10UL)
4744#define TIMER3_MCR_MR1S_Pos (5UL)
4745#define TIMER3_MCR_MR1S_Msk (0x20UL)
4746#define TIMER3_MCR_MR2I_Pos (6UL)
4747#define TIMER3_MCR_MR2I_Msk (0x40UL)
4748#define TIMER3_MCR_MR2R_Pos (7UL)
4749#define TIMER3_MCR_MR2R_Msk (0x80UL)
4750#define TIMER3_MCR_MR2S_Pos (8UL)
4751#define TIMER3_MCR_MR2S_Msk (0x100UL)
4752#define TIMER3_MCR_MR3I_Pos (9UL)
4753#define TIMER3_MCR_MR3I_Msk (0x200UL)
4754#define TIMER3_MCR_MR3R_Pos (10UL)
4755#define TIMER3_MCR_MR3R_Msk (0x400UL)
4756#define TIMER3_MCR_MR3S_Pos (11UL)
4757#define TIMER3_MCR_MR3S_Msk (0x800UL)
4758/* ========================================================== CCR ========================================================== */
4759#define TIMER3_CCR_CAP0RE_Pos (0UL)
4760#define TIMER3_CCR_CAP0RE_Msk (0x1UL)
4761#define TIMER3_CCR_CAP0FE_Pos (1UL)
4762#define TIMER3_CCR_CAP0FE_Msk (0x2UL)
4763#define TIMER3_CCR_CAP0I_Pos (2UL)
4764#define TIMER3_CCR_CAP0I_Msk (0x4UL)
4765#define TIMER3_CCR_CAP1RE_Pos (3UL)
4766#define TIMER3_CCR_CAP1RE_Msk (0x8UL)
4767#define TIMER3_CCR_CAP1FE_Pos (4UL)
4768#define TIMER3_CCR_CAP1FE_Msk (0x10UL)
4769#define TIMER3_CCR_CAP1I_Pos (5UL)
4770#define TIMER3_CCR_CAP1I_Msk (0x20UL)
4771/* ========================================================== EMR ========================================================== */
4772#define TIMER3_EMR_EM0_Pos (0UL)
4773#define TIMER3_EMR_EM0_Msk (0x1UL)
4774#define TIMER3_EMR_EM1_Pos (1UL)
4775#define TIMER3_EMR_EM1_Msk (0x2UL)
4776#define TIMER3_EMR_EM2_Pos (2UL)
4777#define TIMER3_EMR_EM2_Msk (0x4UL)
4778#define TIMER3_EMR_EM3_Pos (3UL)
4779#define TIMER3_EMR_EM3_Msk (0x8UL)
4780#define TIMER3_EMR_EMC0_Pos (4UL)
4781#define TIMER3_EMR_EMC0_Msk (0x30UL)
4782#define TIMER3_EMR_EMC1_Pos (6UL)
4783#define TIMER3_EMR_EMC1_Msk (0xc0UL)
4784#define TIMER3_EMR_EMC2_Pos (8UL)
4785#define TIMER3_EMR_EMC2_Msk (0x300UL)
4786#define TIMER3_EMR_EMC3_Pos (10UL)
4787#define TIMER3_EMR_EMC3_Msk (0xc00UL)
4788/* ========================================================= CTCR ========================================================== */
4789#define TIMER3_CTCR_CTMODE_Pos (0UL)
4790#define TIMER3_CTCR_CTMODE_Msk (0x3UL)
4791#define TIMER3_CTCR_CINSEL_Pos (2UL)
4792#define TIMER3_CTCR_CINSEL_Msk (0xcUL)
4795/* =========================================================================================================================== */
4796/* ================ LPC_UART2 ================ */
4797/* =========================================================================================================================== */
4798
4799/* ========================================================== RBR ========================================================== */
4800#define UART2_RBR_RBR_Pos (0UL)
4801#define UART2_RBR_RBR_Msk (0xffUL)
4802/* ========================================================== THR ========================================================== */
4803#define UART2_THR_THR_Pos (0UL)
4804#define UART2_THR_THR_Msk (0xffUL)
4805/* ========================================================== DLL ========================================================== */
4806#define UART2_DLL_DLLSB_Pos (0UL)
4807#define UART2_DLL_DLLSB_Msk (0xffUL)
4808/* ========================================================== DLM ========================================================== */
4809#define UART2_DLM_DLMSB_Pos (0UL)
4810#define UART2_DLM_DLMSB_Msk (0xffUL)
4811/* ========================================================== IER ========================================================== */
4812#define UART2_IER_RBRIE_Pos (0UL)
4813#define UART2_IER_RBRIE_Msk (0x1UL)
4814#define UART2_IER_THREIE_Pos (1UL)
4815#define UART2_IER_THREIE_Msk (0x2UL)
4816#define UART2_IER_RXIE_Pos (2UL)
4817#define UART2_IER_RXIE_Msk (0x4UL)
4818#define UART2_IER_ABEOINTEN_Pos (8UL)
4819#define UART2_IER_ABEOINTEN_Msk (0x100UL)
4820#define UART2_IER_ABTOINTEN_Pos (9UL)
4821#define UART2_IER_ABTOINTEN_Msk (0x200UL)
4822/* ========================================================== IIR ========================================================== */
4823#define UART2_IIR_INTSTATUS_Pos (0UL)
4824#define UART2_IIR_INTSTATUS_Msk (0x1UL)
4825#define UART2_IIR_INTID_Pos (1UL)
4826#define UART2_IIR_INTID_Msk (0xeUL)
4827#define UART2_IIR_FIFOENABLE_Pos (6UL)
4828#define UART2_IIR_FIFOENABLE_Msk (0xc0UL)
4829#define UART2_IIR_ABEOINT_Pos (8UL)
4830#define UART2_IIR_ABEOINT_Msk (0x100UL)
4831#define UART2_IIR_ABTOINT_Pos (9UL)
4832#define UART2_IIR_ABTOINT_Msk (0x200UL)
4833/* ========================================================== FCR ========================================================== */
4834#define UART2_FCR_FIFOEN_Pos (0UL)
4835#define UART2_FCR_FIFOEN_Msk (0x1UL)
4836#define UART2_FCR_RXFIFORES_Pos (1UL)
4837#define UART2_FCR_RXFIFORES_Msk (0x2UL)
4838#define UART2_FCR_TXFIFORES_Pos (2UL)
4839#define UART2_FCR_TXFIFORES_Msk (0x4UL)
4840#define UART2_FCR_DMAMODE_Pos (3UL)
4841#define UART2_FCR_DMAMODE_Msk (0x8UL)
4842#define UART2_FCR_RXTRIGLVL_Pos (6UL)
4843#define UART2_FCR_RXTRIGLVL_Msk (0xc0UL)
4844/* ========================================================== LCR ========================================================== */
4845#define UART2_LCR_WLS_Pos (0UL)
4846#define UART2_LCR_WLS_Msk (0x3UL)
4847#define UART2_LCR_SBS_Pos (2UL)
4848#define UART2_LCR_SBS_Msk (0x4UL)
4849#define UART2_LCR_PE_Pos (3UL)
4850#define UART2_LCR_PE_Msk (0x8UL)
4851#define UART2_LCR_PS_Pos (4UL)
4852#define UART2_LCR_PS_Msk (0x30UL)
4853#define UART2_LCR_BC_Pos (6UL)
4854#define UART2_LCR_BC_Msk (0x40UL)
4855#define UART2_LCR_DLAB_Pos (7UL)
4856#define UART2_LCR_DLAB_Msk (0x80UL)
4857/* ========================================================== LSR ========================================================== */
4858#define UART2_LSR_RDR_Pos (0UL)
4859#define UART2_LSR_RDR_Msk (0x1UL)
4860#define UART2_LSR_OE_Pos (1UL)
4861#define UART2_LSR_OE_Msk (0x2UL)
4862#define UART2_LSR_PE_Pos (2UL)
4863#define UART2_LSR_PE_Msk (0x4UL)
4864#define UART2_LSR_FE_Pos (3UL)
4865#define UART2_LSR_FE_Msk (0x8UL)
4866#define UART2_LSR_BI_Pos (4UL)
4867#define UART2_LSR_BI_Msk (0x10UL)
4868#define UART2_LSR_THRE_Pos (5UL)
4869#define UART2_LSR_THRE_Msk (0x20UL)
4870#define UART2_LSR_TEMT_Pos (6UL)
4871#define UART2_LSR_TEMT_Msk (0x40UL)
4872#define UART2_LSR_RXFE_Pos (7UL)
4873#define UART2_LSR_RXFE_Msk (0x80UL)
4874/* ========================================================== SCR ========================================================== */
4875#define UART2_SCR_PAD_Pos (0UL)
4876#define UART2_SCR_PAD_Msk (0xffUL)
4877/* ========================================================== ACR ========================================================== */
4878#define UART2_ACR_START_Pos (0UL)
4879#define UART2_ACR_START_Msk (0x1UL)
4880#define UART2_ACR_MODE_Pos (1UL)
4881#define UART2_ACR_MODE_Msk (0x2UL)
4882#define UART2_ACR_AUTORESTART_Pos (2UL)
4883#define UART2_ACR_AUTORESTART_Msk (0x4UL)
4884#define UART2_ACR_ABEOINTCLR_Pos (8UL)
4885#define UART2_ACR_ABEOINTCLR_Msk (0x100UL)
4886#define UART2_ACR_ABTOINTCLR_Pos (9UL)
4887#define UART2_ACR_ABTOINTCLR_Msk (0x200UL)
4888/* ========================================================== FDR ========================================================== */
4889#define UART2_FDR_DIVADDVAL_Pos (0UL)
4890#define UART2_FDR_DIVADDVAL_Msk (0xfUL)
4891#define UART2_FDR_MULVAL_Pos (4UL)
4892#define UART2_FDR_MULVAL_Msk (0xf0UL)
4893/* ========================================================== TER ========================================================== */
4894#define UART2_TER_TXEN_Pos (7UL)
4895#define UART2_TER_TXEN_Msk (0x80UL)
4896/* ======================================================= RS485CTRL ======================================================= */
4897#define UART2_RS485CTRL_NMMEN_Pos (0UL)
4898#define UART2_RS485CTRL_NMMEN_Msk (0x1UL)
4899#define UART2_RS485CTRL_RXDIS_Pos (1UL)
4900#define UART2_RS485CTRL_RXDIS_Msk (0x2UL)
4901#define UART2_RS485CTRL_AADEN_Pos (2UL)
4902#define UART2_RS485CTRL_AADEN_Msk (0x4UL)
4903#define UART2_RS485CTRL_DCTRL_Pos (4UL)
4904#define UART2_RS485CTRL_DCTRL_Msk (0x10UL)
4905#define UART2_RS485CTRL_OINV_Pos (5UL)
4906#define UART2_RS485CTRL_OINV_Msk (0x20UL)
4907/* ===================================================== RS485ADRMATCH ===================================================== */
4908#define UART2_RS485ADRMATCH_ADRMATCH_Pos (0UL)
4909#define UART2_RS485ADRMATCH_ADRMATCH_Msk (0xffUL)
4910/* ======================================================= RS485DLY ======================================================== */
4911#define UART2_RS485DLY_DLY_Pos (0UL)
4912#define UART2_RS485DLY_DLY_Msk (0xffUL)
4915/* =========================================================================================================================== */
4916/* ================ LPC_UART3 ================ */
4917/* =========================================================================================================================== */
4918
4919/* ========================================================== RBR ========================================================== */
4920#define UART3_RBR_RBR_Pos (0UL)
4921#define UART3_RBR_RBR_Msk (0xffUL)
4922/* ========================================================== THR ========================================================== */
4923#define UART3_THR_THR_Pos (0UL)
4924#define UART3_THR_THR_Msk (0xffUL)
4925/* ========================================================== DLL ========================================================== */
4926#define UART3_DLL_DLLSB_Pos (0UL)
4927#define UART3_DLL_DLLSB_Msk (0xffUL)
4928/* ========================================================== DLM ========================================================== */
4929#define UART3_DLM_DLMSB_Pos (0UL)
4930#define UART3_DLM_DLMSB_Msk (0xffUL)
4931/* ========================================================== IER ========================================================== */
4932#define UART3_IER_RBRIE_Pos (0UL)
4933#define UART3_IER_RBRIE_Msk (0x1UL)
4934#define UART3_IER_THREIE_Pos (1UL)
4935#define UART3_IER_THREIE_Msk (0x2UL)
4936#define UART3_IER_RXIE_Pos (2UL)
4937#define UART3_IER_RXIE_Msk (0x4UL)
4938#define UART3_IER_ABEOINTEN_Pos (8UL)
4939#define UART3_IER_ABEOINTEN_Msk (0x100UL)
4940#define UART3_IER_ABTOINTEN_Pos (9UL)
4941#define UART3_IER_ABTOINTEN_Msk (0x200UL)
4942/* ========================================================== IIR ========================================================== */
4943#define UART3_IIR_INTSTATUS_Pos (0UL)
4944#define UART3_IIR_INTSTATUS_Msk (0x1UL)
4945#define UART3_IIR_INTID_Pos (1UL)
4946#define UART3_IIR_INTID_Msk (0xeUL)
4947#define UART3_IIR_FIFOENABLE_Pos (6UL)
4948#define UART3_IIR_FIFOENABLE_Msk (0xc0UL)
4949#define UART3_IIR_ABEOINT_Pos (8UL)
4950#define UART3_IIR_ABEOINT_Msk (0x100UL)
4951#define UART3_IIR_ABTOINT_Pos (9UL)
4952#define UART3_IIR_ABTOINT_Msk (0x200UL)
4953/* ========================================================== FCR ========================================================== */
4954#define UART3_FCR_FIFOEN_Pos (0UL)
4955#define UART3_FCR_FIFOEN_Msk (0x1UL)
4956#define UART3_FCR_RXFIFORES_Pos (1UL)
4957#define UART3_FCR_RXFIFORES_Msk (0x2UL)
4958#define UART3_FCR_TXFIFORES_Pos (2UL)
4959#define UART3_FCR_TXFIFORES_Msk (0x4UL)
4960#define UART3_FCR_DMAMODE_Pos (3UL)
4961#define UART3_FCR_DMAMODE_Msk (0x8UL)
4962#define UART3_FCR_RXTRIGLVL_Pos (6UL)
4963#define UART3_FCR_RXTRIGLVL_Msk (0xc0UL)
4964/* ========================================================== LCR ========================================================== */
4965#define UART3_LCR_WLS_Pos (0UL)
4966#define UART3_LCR_WLS_Msk (0x3UL)
4967#define UART3_LCR_SBS_Pos (2UL)
4968#define UART3_LCR_SBS_Msk (0x4UL)
4969#define UART3_LCR_PE_Pos (3UL)
4970#define UART3_LCR_PE_Msk (0x8UL)
4971#define UART3_LCR_PS_Pos (4UL)
4972#define UART3_LCR_PS_Msk (0x30UL)
4973#define UART3_LCR_BC_Pos (6UL)
4974#define UART3_LCR_BC_Msk (0x40UL)
4975#define UART3_LCR_DLAB_Pos (7UL)
4976#define UART3_LCR_DLAB_Msk (0x80UL)
4977/* ========================================================== LSR ========================================================== */
4978#define UART3_LSR_RDR_Pos (0UL)
4979#define UART3_LSR_RDR_Msk (0x1UL)
4980#define UART3_LSR_OE_Pos (1UL)
4981#define UART3_LSR_OE_Msk (0x2UL)
4982#define UART3_LSR_PE_Pos (2UL)
4983#define UART3_LSR_PE_Msk (0x4UL)
4984#define UART3_LSR_FE_Pos (3UL)
4985#define UART3_LSR_FE_Msk (0x8UL)
4986#define UART3_LSR_BI_Pos (4UL)
4987#define UART3_LSR_BI_Msk (0x10UL)
4988#define UART3_LSR_THRE_Pos (5UL)
4989#define UART3_LSR_THRE_Msk (0x20UL)
4990#define UART3_LSR_TEMT_Pos (6UL)
4991#define UART3_LSR_TEMT_Msk (0x40UL)
4992#define UART3_LSR_RXFE_Pos (7UL)
4993#define UART3_LSR_RXFE_Msk (0x80UL)
4994/* ========================================================== SCR ========================================================== */
4995#define UART3_SCR_PAD_Pos (0UL)
4996#define UART3_SCR_PAD_Msk (0xffUL)
4997/* ========================================================== ACR ========================================================== */
4998#define UART3_ACR_START_Pos (0UL)
4999#define UART3_ACR_START_Msk (0x1UL)
5000#define UART3_ACR_MODE_Pos (1UL)
5001#define UART3_ACR_MODE_Msk (0x2UL)
5002#define UART3_ACR_AUTORESTART_Pos (2UL)
5003#define UART3_ACR_AUTORESTART_Msk (0x4UL)
5004#define UART3_ACR_ABEOINTCLR_Pos (8UL)
5005#define UART3_ACR_ABEOINTCLR_Msk (0x100UL)
5006#define UART3_ACR_ABTOINTCLR_Pos (9UL)
5007#define UART3_ACR_ABTOINTCLR_Msk (0x200UL)
5008/* ========================================================== FDR ========================================================== */
5009#define UART3_FDR_DIVADDVAL_Pos (0UL)
5010#define UART3_FDR_DIVADDVAL_Msk (0xfUL)
5011#define UART3_FDR_MULVAL_Pos (4UL)
5012#define UART3_FDR_MULVAL_Msk (0xf0UL)
5013/* ========================================================== TER ========================================================== */
5014#define UART3_TER_TXEN_Pos (7UL)
5015#define UART3_TER_TXEN_Msk (0x80UL)
5016/* ======================================================= RS485CTRL ======================================================= */
5017#define UART3_RS485CTRL_NMMEN_Pos (0UL)
5018#define UART3_RS485CTRL_NMMEN_Msk (0x1UL)
5019#define UART3_RS485CTRL_RXDIS_Pos (1UL)
5020#define UART3_RS485CTRL_RXDIS_Msk (0x2UL)
5021#define UART3_RS485CTRL_AADEN_Pos (2UL)
5022#define UART3_RS485CTRL_AADEN_Msk (0x4UL)
5023#define UART3_RS485CTRL_DCTRL_Pos (4UL)
5024#define UART3_RS485CTRL_DCTRL_Msk (0x10UL)
5025#define UART3_RS485CTRL_OINV_Pos (5UL)
5026#define UART3_RS485CTRL_OINV_Msk (0x20UL)
5027/* ===================================================== RS485ADRMATCH ===================================================== */
5028#define UART3_RS485ADRMATCH_ADRMATCH_Pos (0UL)
5029#define UART3_RS485ADRMATCH_ADRMATCH_Msk (0xffUL)
5030/* ======================================================= RS485DLY ======================================================== */
5031#define UART3_RS485DLY_DLY_Pos (0UL)
5032#define UART3_RS485DLY_DLY_Msk (0xffUL)
5035/* =========================================================================================================================== */
5036/* ================ LPC_I2S ================ */
5037/* =========================================================================================================================== */
5038
5039/* ========================================================== DAO ========================================================== */
5040#define I2S_DAO_WORDWIDTH_Pos (0UL)
5041#define I2S_DAO_WORDWIDTH_Msk (0x3UL)
5042#define I2S_DAO_MONO_Pos (2UL)
5043#define I2S_DAO_MONO_Msk (0x4UL)
5044#define I2S_DAO_STOP_Pos (3UL)
5045#define I2S_DAO_STOP_Msk (0x8UL)
5046#define I2S_DAO_RESET_Pos (4UL)
5047#define I2S_DAO_RESET_Msk (0x10UL)
5048#define I2S_DAO_WS_SEL_Pos (5UL)
5049#define I2S_DAO_WS_SEL_Msk (0x20UL)
5050#define I2S_DAO_WS_HALFPERIOD_Pos (6UL)
5051#define I2S_DAO_WS_HALFPERIOD_Msk (0x7fc0UL)
5052#define I2S_DAO_MUTE_Pos (15UL)
5053#define I2S_DAO_MUTE_Msk (0x8000UL)
5054/* ========================================================== DAI ========================================================== */
5055#define I2S_DAI_WORDWIDTH_Pos (0UL)
5056#define I2S_DAI_WORDWIDTH_Msk (0x3UL)
5057#define I2S_DAI_MONO_Pos (2UL)
5058#define I2S_DAI_MONO_Msk (0x4UL)
5059#define I2S_DAI_STOP_Pos (3UL)
5060#define I2S_DAI_STOP_Msk (0x8UL)
5061#define I2S_DAI_RESET_Pos (4UL)
5062#define I2S_DAI_RESET_Msk (0x10UL)
5063#define I2S_DAI_WS_SEL_Pos (5UL)
5064#define I2S_DAI_WS_SEL_Msk (0x20UL)
5065#define I2S_DAI_WS_HALFPERIOD_Pos (6UL)
5066#define I2S_DAI_WS_HALFPERIOD_Msk (0x7fc0UL)
5067/* ======================================================== TXFIFO ========================================================= */
5068#define I2S_TXFIFO_I2STXFIFO_Pos (0UL)
5069#define I2S_TXFIFO_I2STXFIFO_Msk (0xffffffffUL)
5070/* ======================================================== RXFIFO ========================================================= */
5071#define I2S_RXFIFO_I2SRXFIFO_Pos (0UL)
5072#define I2S_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL)
5073/* ========================================================= STATE ========================================================= */
5074#define I2S_STATE_IRQ_Pos (0UL)
5075#define I2S_STATE_IRQ_Msk (0x1UL)
5076#define I2S_STATE_DMAREQ1_Pos (1UL)
5077#define I2S_STATE_DMAREQ1_Msk (0x2UL)
5078#define I2S_STATE_DMAREQ2_Pos (2UL)
5079#define I2S_STATE_DMAREQ2_Msk (0x4UL)
5080#define I2S_STATE_RX_LEVEL_Pos (8UL)
5081#define I2S_STATE_RX_LEVEL_Msk (0xf00UL)
5082#define I2S_STATE_TX_LEVEL_Pos (16UL)
5083#define I2S_STATE_TX_LEVEL_Msk (0xf0000UL)
5084/* ========================================================= DMA1 ========================================================== */
5085#define I2S_DMA1_RX_DMA1_ENABLE_Pos (0UL)
5086#define I2S_DMA1_RX_DMA1_ENABLE_Msk (0x1UL)
5087#define I2S_DMA1_TX_DMA1_ENABLE_Pos (1UL)
5088#define I2S_DMA1_TX_DMA1_ENABLE_Msk (0x2UL)
5089#define I2S_DMA1_RX_DEPTH_DMA1_Pos (8UL)
5090#define I2S_DMA1_RX_DEPTH_DMA1_Msk (0xf00UL)
5091#define I2S_DMA1_TX_DEPTH_DMA1_Pos (16UL)
5092#define I2S_DMA1_TX_DEPTH_DMA1_Msk (0xf0000UL)
5093/* ========================================================= DMA2 ========================================================== */
5094#define I2S_DMA2_RX_DMA2_ENABLE_Pos (0UL)
5095#define I2S_DMA2_RX_DMA2_ENABLE_Msk (0x1UL)
5096#define I2S_DMA2_TX_DMA2_ENABLE_Pos (1UL)
5097#define I2S_DMA2_TX_DMA2_ENABLE_Msk (0x2UL)
5098#define I2S_DMA2_RX_DEPTH_DMA2_Pos (8UL)
5099#define I2S_DMA2_RX_DEPTH_DMA2_Msk (0xf00UL)
5100#define I2S_DMA2_TX_DEPTH_DMA2_Pos (16UL)
5101#define I2S_DMA2_TX_DEPTH_DMA2_Msk (0xf0000UL)
5102/* ========================================================== IRQ ========================================================== */
5103#define I2S_IRQ_RX_IRQ_ENABLE_Pos (0UL)
5104#define I2S_IRQ_RX_IRQ_ENABLE_Msk (0x1UL)
5105#define I2S_IRQ_TX_IRQ_ENABLE_Pos (1UL)
5106#define I2S_IRQ_TX_IRQ_ENABLE_Msk (0x2UL)
5107#define I2S_IRQ_RX_DEPTH_IRQ_Pos (8UL)
5108#define I2S_IRQ_RX_DEPTH_IRQ_Msk (0xf00UL)
5109#define I2S_IRQ_TX_DEPTH_IRQ_Pos (16UL)
5110#define I2S_IRQ_TX_DEPTH_IRQ_Msk (0xf0000UL)
5111/* ======================================================== TXRATE ========================================================= */
5112#define I2S_TXRATE_Y_DIVIDER_Pos (0UL)
5113#define I2S_TXRATE_Y_DIVIDER_Msk (0xffUL)
5114#define I2S_TXRATE_X_DIVIDER_Pos (8UL)
5115#define I2S_TXRATE_X_DIVIDER_Msk (0xff00UL)
5116/* ======================================================== RXRATE ========================================================= */
5117#define I2S_RXRATE_Y_DIVIDER_Pos (0UL)
5118#define I2S_RXRATE_Y_DIVIDER_Msk (0xffUL)
5119#define I2S_RXRATE_X_DIVIDER_Pos (8UL)
5120#define I2S_RXRATE_X_DIVIDER_Msk (0xff00UL)
5121/* ======================================================= TXBITRATE ======================================================= */
5122#define I2S_TXBITRATE_TX_BITRATE_Pos (0UL)
5123#define I2S_TXBITRATE_TX_BITRATE_Msk (0x3fUL)
5124/* ======================================================= RXBITRATE ======================================================= */
5125#define I2S_RXBITRATE_RX_BITRATE_Pos (0UL)
5126#define I2S_RXBITRATE_RX_BITRATE_Msk (0x3fUL)
5127/* ======================================================== TXMODE ========================================================= */
5128#define I2S_TXMODE_TXCLKSEL_Pos (0UL)
5129#define I2S_TXMODE_TXCLKSEL_Msk (0x3UL)
5130#define I2S_TXMODE_TX4PIN_Pos (2UL)
5131#define I2S_TXMODE_TX4PIN_Msk (0x4UL)
5132#define I2S_TXMODE_TXMCENA_Pos (3UL)
5133#define I2S_TXMODE_TXMCENA_Msk (0x8UL)
5134/* ======================================================== RXMODE ========================================================= */
5135#define I2S_RXMODE_RXCLKSEL_Pos (0UL)
5136#define I2S_RXMODE_RXCLKSEL_Msk (0x3UL)
5137#define I2S_RXMODE_RX4PIN_Pos (2UL)
5138#define I2S_RXMODE_RX4PIN_Msk (0x4UL)
5139#define I2S_RXMODE_RXMCENA_Pos (3UL)
5140#define I2S_RXMODE_RXMCENA_Msk (0x8UL)
5143/* =========================================================================================================================== */
5144/* ================ LPC_RITIMER ================ */
5145/* =========================================================================================================================== */
5146
5147/* ======================================================== COMPVAL ======================================================== */
5148#define RITIMER_COMPVAL_RICOMP_Pos (0UL)
5149#define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL)
5150/* ========================================================= MASK ========================================================== */
5151#define RITIMER_MASK_RIMASK_Pos (0UL)
5152#define RITIMER_MASK_RIMASK_Msk (0xffffffffUL)
5153/* ========================================================= CTRL ========================================================== */
5154#define RITIMER_CTRL_RITINT_Pos (0UL)
5155#define RITIMER_CTRL_RITINT_Msk (0x1UL)
5156#define RITIMER_CTRL_RITENCLR_Pos (1UL)
5157#define RITIMER_CTRL_RITENCLR_Msk (0x2UL)
5158#define RITIMER_CTRL_RITENBR_Pos (2UL)
5159#define RITIMER_CTRL_RITENBR_Msk (0x4UL)
5160#define RITIMER_CTRL_RITEN_Pos (3UL)
5161#define RITIMER_CTRL_RITEN_Msk (0x8UL)
5162/* ======================================================== COUNTER ======================================================== */
5163#define RITIMER_COUNTER_RICOUNTER_Pos (0UL)
5164#define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL)
5167/* =========================================================================================================================== */
5168/* ================ LPC_MCPWM ================ */
5169/* =========================================================================================================================== */
5170
5171/* ========================================================== CON ========================================================== */
5172#define MCPWM_CON_RUN0_Pos (0UL)
5173#define MCPWM_CON_RUN0_Msk (0x1UL)
5174#define MCPWM_CON_CENTER0_Pos (1UL)
5175#define MCPWM_CON_CENTER0_Msk (0x2UL)
5176#define MCPWM_CON_POLA0_Pos (2UL)
5177#define MCPWM_CON_POLA0_Msk (0x4UL)
5178#define MCPWM_CON_DTE0_Pos (3UL)
5179#define MCPWM_CON_DTE0_Msk (0x8UL)
5180#define MCPWM_CON_DISUP0_Pos (4UL)
5181#define MCPWM_CON_DISUP0_Msk (0x10UL)
5182#define MCPWM_CON_RUN1_Pos (8UL)
5183#define MCPWM_CON_RUN1_Msk (0x100UL)
5184#define MCPWM_CON_CENTER1_Pos (9UL)
5185#define MCPWM_CON_CENTER1_Msk (0x200UL)
5186#define MCPWM_CON_POLA1_Pos (10UL)
5187#define MCPWM_CON_POLA1_Msk (0x400UL)
5188#define MCPWM_CON_DTE1_Pos (11UL)
5189#define MCPWM_CON_DTE1_Msk (0x800UL)
5190#define MCPWM_CON_DISUP1_Pos (12UL)
5191#define MCPWM_CON_DISUP1_Msk (0x1000UL)
5192#define MCPWM_CON_RUN2_Pos (16UL)
5193#define MCPWM_CON_RUN2_Msk (0x10000UL)
5194#define MCPWM_CON_CENTER2_Pos (17UL)
5195#define MCPWM_CON_CENTER2_Msk (0x20000UL)
5196#define MCPWM_CON_POLA2_Pos (18UL)
5197#define MCPWM_CON_POLA2_Msk (0x40000UL)
5198#define MCPWM_CON_DTE2_Pos (19UL)
5199#define MCPWM_CON_DTE2_Msk (0x80000UL)
5200#define MCPWM_CON_DISUP2_Pos (20UL)
5201#define MCPWM_CON_DISUP2_Msk (0x100000UL)
5202#define MCPWM_CON_INVBDC_Pos (29UL)
5203#define MCPWM_CON_INVBDC_Msk (0x20000000UL)
5204#define MCPWM_CON_ACMODE_Pos (30UL)
5205#define MCPWM_CON_ACMODE_Msk (0x40000000UL)
5206#define MCPWM_CON_DCMODE_Pos (31UL)
5207#define MCPWM_CON_DCMODE_Msk (0x80000000UL)
5208/* ======================================================== CON_SET ======================================================== */
5209#define MCPWM_CON_SET_RUN0_SET_Pos (0UL)
5210#define MCPWM_CON_SET_RUN0_SET_Msk (0x1UL)
5211#define MCPWM_CON_SET_CENTER0_SET_Pos (1UL)
5212#define MCPWM_CON_SET_CENTER0_SET_Msk (0x2UL)
5213#define MCPWM_CON_SET_POLA0_SET_Pos (2UL)
5214#define MCPWM_CON_SET_POLA0_SET_Msk (0x4UL)
5215#define MCPWM_CON_SET_DTE0_SET_Pos (3UL)
5216#define MCPWM_CON_SET_DTE0_SET_Msk (0x8UL)
5217#define MCPWM_CON_SET_DISUP0_SET_Pos (4UL)
5218#define MCPWM_CON_SET_DISUP0_SET_Msk (0x10UL)
5219#define MCPWM_CON_SET_RUN1_SET_Pos (8UL)
5220#define MCPWM_CON_SET_RUN1_SET_Msk (0x100UL)
5221#define MCPWM_CON_SET_CENTER1_SET_Pos (9UL)
5222#define MCPWM_CON_SET_CENTER1_SET_Msk (0x200UL)
5223#define MCPWM_CON_SET_POLA1_SET_Pos (10UL)
5224#define MCPWM_CON_SET_POLA1_SET_Msk (0x400UL)
5225#define MCPWM_CON_SET_DTE1_SET_Pos (11UL)
5226#define MCPWM_CON_SET_DTE1_SET_Msk (0x800UL)
5227#define MCPWM_CON_SET_DISUP1_SET_Pos (12UL)
5228#define MCPWM_CON_SET_DISUP1_SET_Msk (0x1000UL)
5229#define MCPWM_CON_SET_RUN2_SET_Pos (16UL)
5230#define MCPWM_CON_SET_RUN2_SET_Msk (0x10000UL)
5231#define MCPWM_CON_SET_CENTER2_SET_Pos (17UL)
5232#define MCPWM_CON_SET_CENTER2_SET_Msk (0x20000UL)
5233#define MCPWM_CON_SET_POLA2_SET_Pos (18UL)
5234#define MCPWM_CON_SET_POLA2_SET_Msk (0x40000UL)
5235#define MCPWM_CON_SET_DTE2_SET_Pos (19UL)
5236#define MCPWM_CON_SET_DTE2_SET_Msk (0x80000UL)
5237#define MCPWM_CON_SET_DISUP2_SET_Pos (20UL)
5238#define MCPWM_CON_SET_DISUP2_SET_Msk (0x100000UL)
5239#define MCPWM_CON_SET_INVBDC_SET_Pos (29UL)
5240#define MCPWM_CON_SET_INVBDC_SET_Msk (0x20000000UL)
5241#define MCPWM_CON_SET_ACMODE_SET_Pos (30UL)
5242#define MCPWM_CON_SET_ACMODE_SET_Msk (0x40000000UL)
5243#define MCPWM_CON_SET_DCMODE_SET_Pos (31UL)
5244#define MCPWM_CON_SET_DCMODE_SET_Msk (0x80000000UL)
5245/* ======================================================== CON_CLR ======================================================== */
5246#define MCPWM_CON_CLR_RUN0_CLR_Pos (0UL)
5247#define MCPWM_CON_CLR_RUN0_CLR_Msk (0x1UL)
5248#define MCPWM_CON_CLR_CENTER0_CLR_Pos (1UL)
5249#define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x2UL)
5250#define MCPWM_CON_CLR_POLA0_CLR_Pos (2UL)
5251#define MCPWM_CON_CLR_POLA0_CLR_Msk (0x4UL)
5252#define MCPWM_CON_CLR_DTE0_CLR_Pos (3UL)
5253#define MCPWM_CON_CLR_DTE0_CLR_Msk (0x8UL)
5254#define MCPWM_CON_CLR_DISUP0_CLR_Pos (4UL)
5255#define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x10UL)
5256#define MCPWM_CON_CLR_RUN1_CLR_Pos (8UL)
5257#define MCPWM_CON_CLR_RUN1_CLR_Msk (0x100UL)
5258#define MCPWM_CON_CLR_CENTER1_CLR_Pos (9UL)
5259#define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x200UL)
5260#define MCPWM_CON_CLR_POLA1_CLR_Pos (10UL)
5261#define MCPWM_CON_CLR_POLA1_CLR_Msk (0x400UL)
5262#define MCPWM_CON_CLR_DTE1_CLR_Pos (11UL)
5263#define MCPWM_CON_CLR_DTE1_CLR_Msk (0x800UL)
5264#define MCPWM_CON_CLR_DISUP1_CLR_Pos (12UL)
5265#define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x1000UL)
5266#define MCPWM_CON_CLR_RUN2_CLR_Pos (16UL)
5267#define MCPWM_CON_CLR_RUN2_CLR_Msk (0x10000UL)
5268#define MCPWM_CON_CLR_CENTER2_CLR_Pos (17UL)
5269#define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x20000UL)
5270#define MCPWM_CON_CLR_POLA2_CLR_Pos (18UL)
5271#define MCPWM_CON_CLR_POLA2_CLR_Msk (0x40000UL)
5272#define MCPWM_CON_CLR_DTE2_CLR_Pos (19UL)
5273#define MCPWM_CON_CLR_DTE2_CLR_Msk (0x80000UL)
5274#define MCPWM_CON_CLR_DISUP2_CLR_Pos (20UL)
5275#define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x100000UL)
5276#define MCPWM_CON_CLR_INVBDC_CLR_Pos (29UL)
5277#define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x20000000UL)
5278#define MCPWM_CON_CLR_ACMOD_CLR_Pos (30UL)
5279#define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x40000000UL)
5280#define MCPWM_CON_CLR_DCMODE_CLR_Pos (31UL)
5281#define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x80000000UL)
5282/* ======================================================== CAPCON ========================================================= */
5283#define MCPWM_CAPCON_CAP0MCI0_RE_Pos (0UL)
5284#define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x1UL)
5285#define MCPWM_CAPCON_CAP0MCI0_FE_Pos (1UL)
5286#define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x2UL)
5287#define MCPWM_CAPCON_CAP0MCI1_RE_Pos (2UL)
5288#define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x4UL)
5289#define MCPWM_CAPCON_CAP0MCI1_FE_Pos (3UL)
5290#define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x8UL)
5291#define MCPWM_CAPCON_CAP0MCI2_RE_Pos (4UL)
5292#define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x10UL)
5293#define MCPWM_CAPCON_CAP0MCI2_FE_Pos (5UL)
5294#define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x20UL)
5295#define MCPWM_CAPCON_CAP1MCI0_RE_Pos (6UL)
5296#define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x40UL)
5297#define MCPWM_CAPCON_CAP1MCI0_FE_Pos (7UL)
5298#define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x80UL)
5299#define MCPWM_CAPCON_CAP1MCI1_RE_Pos (8UL)
5300#define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x100UL)
5301#define MCPWM_CAPCON_CAP1MCI1_FE_Pos (9UL)
5302#define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x200UL)
5303#define MCPWM_CAPCON_CAP1MCI2_RE_Pos (10UL)
5304#define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x400UL)
5305#define MCPWM_CAPCON_CAP1MCI2_FE_Pos (11UL)
5306#define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x800UL)
5307#define MCPWM_CAPCON_CAP2MCI0_RE_Pos (12UL)
5308#define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x1000UL)
5309#define MCPWM_CAPCON_CAP2MCI0_FE_Pos (13UL)
5310#define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x2000UL)
5311#define MCPWM_CAPCON_CAP2MCI1_RE_Pos (14UL)
5312#define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x4000UL)
5313#define MCPWM_CAPCON_CAP2MCI1_FE_Pos (15UL)
5314#define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x8000UL)
5315#define MCPWM_CAPCON_CAP2MCI2_RE_Pos (16UL)
5316#define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x10000UL)
5317#define MCPWM_CAPCON_CAP2MCI2_FE_Pos (17UL)
5318#define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x20000UL)
5319#define MCPWM_CAPCON_RT0_Pos (18UL)
5320#define MCPWM_CAPCON_RT0_Msk (0x40000UL)
5321#define MCPWM_CAPCON_RT1_Pos (19UL)
5322#define MCPWM_CAPCON_RT1_Msk (0x80000UL)
5323#define MCPWM_CAPCON_RT2_Pos (20UL)
5324#define MCPWM_CAPCON_RT2_Msk (0x100000UL)
5325/* ====================================================== CAPCON_SET ======================================================= */
5326#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos (0UL)
5327#define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x1UL)
5328#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos (1UL)
5329#define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x2UL)
5330#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos (2UL)
5331#define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x4UL)
5332#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos (3UL)
5333#define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x8UL)
5334#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos (4UL)
5335#define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x10UL)
5336#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos (5UL)
5337#define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x20UL)
5338#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos (6UL)
5339#define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x40UL)
5340#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos (7UL)
5341#define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x80UL)
5342#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos (8UL)
5343#define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x100UL)
5344#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos (9UL)
5345#define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x200UL)
5346#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos (10UL)
5347#define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x400UL)
5348#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos (11UL)
5349#define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x800UL)
5350#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos (12UL)
5351#define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x1000UL)
5352#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos (13UL)
5353#define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x2000UL)
5354#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos (14UL)
5355#define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x4000UL)
5356#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos (15UL)
5357#define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x8000UL)
5358#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos (16UL)
5359#define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x10000UL)
5360#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos (17UL)
5361#define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x20000UL)
5362#define MCPWM_CAPCON_SET_RT0_SET_Pos (18UL)
5363#define MCPWM_CAPCON_SET_RT0_SET_Msk (0x40000UL)
5364#define MCPWM_CAPCON_SET_RT1_SET_Pos (19UL)
5365#define MCPWM_CAPCON_SET_RT1_SET_Msk (0x80000UL)
5366#define MCPWM_CAPCON_SET_RT2_SET_Pos (20UL)
5367#define MCPWM_CAPCON_SET_RT2_SET_Msk (0x100000UL)
5368/* ====================================================== CAPCON_CLR ======================================================= */
5369#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos (0UL)
5370#define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x1UL)
5371#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos (1UL)
5372#define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x2UL)
5373#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos (2UL)
5374#define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x4UL)
5375#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos (3UL)
5376#define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x8UL)
5377#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos (4UL)
5378#define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x10UL)
5379#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos (5UL)
5380#define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x20UL)
5381#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos (6UL)
5382#define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x40UL)
5383#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos (7UL)
5384#define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x80UL)
5385#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos (8UL)
5386#define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x100UL)
5387#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos (9UL)
5388#define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x200UL)
5389#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos (10UL)
5390#define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x400UL)
5391#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos (11UL)
5392#define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x800UL)
5393#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos (12UL)
5394#define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x1000UL)
5395#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos (13UL)
5396#define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x2000UL)
5397#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos (14UL)
5398#define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x4000UL)
5399#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos (15UL)
5400#define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x8000UL)
5401#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos (16UL)
5402#define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x10000UL)
5403#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos (17UL)
5404#define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x20000UL)
5405#define MCPWM_CAPCON_CLR_RT0_CLR_Pos (18UL)
5406#define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x40000UL)
5407#define MCPWM_CAPCON_CLR_RT1_CLR_Pos (19UL)
5408#define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x80000UL)
5409#define MCPWM_CAPCON_CLR_RT2_CLR_Pos (20UL)
5410#define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x100000UL)
5411/* ========================================================== DT =========================================================== */
5412#define MCPWM_DT_DT0_Pos (0UL)
5413#define MCPWM_DT_DT0_Msk (0x3ffUL)
5414#define MCPWM_DT_DT1_Pos (10UL)
5415#define MCPWM_DT_DT1_Msk (0xffc00UL)
5416#define MCPWM_DT_DT2_Pos (20UL)
5417#define MCPWM_DT_DT2_Msk (0x3ff00000UL)
5418/* ========================================================== CP =========================================================== */
5419#define MCPWM_CP_CCPA0_Pos (0UL)
5420#define MCPWM_CP_CCPA0_Msk (0x1UL)
5421#define MCPWM_CP_CCPB0_Pos (1UL)
5422#define MCPWM_CP_CCPB0_Msk (0x2UL)
5423#define MCPWM_CP_CCPA1_Pos (2UL)
5424#define MCPWM_CP_CCPA1_Msk (0x4UL)
5425#define MCPWM_CP_CCPB1_Pos (3UL)
5426#define MCPWM_CP_CCPB1_Msk (0x8UL)
5427#define MCPWM_CP_CCPA2_Pos (4UL)
5428#define MCPWM_CP_CCPA2_Msk (0x10UL)
5429#define MCPWM_CP_CCPB2_Pos (5UL)
5430#define MCPWM_CP_CCPB2_Msk (0x20UL)
5431/* ========================================================= INTEN ========================================================= */
5432#define MCPWM_INTEN_ILIM0_Pos (0UL)
5433#define MCPWM_INTEN_ILIM0_Msk (0x1UL)
5434#define MCPWM_INTEN_IMAT0_Pos (1UL)
5435#define MCPWM_INTEN_IMAT0_Msk (0x2UL)
5436#define MCPWM_INTEN_ICAP0_Pos (2UL)
5437#define MCPWM_INTEN_ICAP0_Msk (0x4UL)
5438#define MCPWM_INTEN_ILIM1_Pos (4UL)
5439#define MCPWM_INTEN_ILIM1_Msk (0x10UL)
5440#define MCPWM_INTEN_IMAT1_Pos (5UL)
5441#define MCPWM_INTEN_IMAT1_Msk (0x20UL)
5442#define MCPWM_INTEN_ICAP1_Pos (6UL)
5443#define MCPWM_INTEN_ICAP1_Msk (0x40UL)
5444#define MCPWM_INTEN_ILIM2_Pos (8UL)
5445#define MCPWM_INTEN_ILIM2_Msk (0x100UL)
5446#define MCPWM_INTEN_IMAT2_Pos (9UL)
5447#define MCPWM_INTEN_IMAT2_Msk (0x200UL)
5448#define MCPWM_INTEN_ICAP2_Pos (10UL)
5449#define MCPWM_INTEN_ICAP2_Msk (0x400UL)
5450#define MCPWM_INTEN_ABORT_Pos (15UL)
5451#define MCPWM_INTEN_ABORT_Msk (0x8000UL)
5452/* ======================================================= INTEN_SET ======================================================= */
5453#define MCPWM_INTEN_SET_ILIM0_SET_Pos (0UL)
5454#define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x1UL)
5455#define MCPWM_INTEN_SET_IMAT0_SET_Pos (1UL)
5456#define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x2UL)
5457#define MCPWM_INTEN_SET_ICAP0_SET_Pos (2UL)
5458#define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x4UL)
5459#define MCPWM_INTEN_SET_ILIM1_SET_Pos (4UL)
5460#define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x10UL)
5461#define MCPWM_INTEN_SET_IMAT1_SET_Pos (5UL)
5462#define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x20UL)
5463#define MCPWM_INTEN_SET_ICAP1_SET_Pos (6UL)
5464#define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x40UL)
5465#define MCPWM_INTEN_SET_ILIM2_SET_Pos (9UL)
5466#define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x200UL)
5467#define MCPWM_INTEN_SET_IMAT2_SET_Pos (10UL)
5468#define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x400UL)
5469#define MCPWM_INTEN_SET_ICAP2_SET_Pos (11UL)
5470#define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x800UL)
5471#define MCPWM_INTEN_SET_ABORT_SET_Pos (15UL)
5472#define MCPWM_INTEN_SET_ABORT_SET_Msk (0x8000UL)
5473/* ======================================================= INTEN_CLR ======================================================= */
5474#define MCPWM_INTEN_CLR_ILIM0_CLR_Pos (0UL)
5475#define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x1UL)
5476#define MCPWM_INTEN_CLR_IMAT0_CLR_Pos (1UL)
5477#define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x2UL)
5478#define MCPWM_INTEN_CLR_ICAP0_CLR_Pos (2UL)
5479#define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x4UL)
5480#define MCPWM_INTEN_CLR_ILIM1_CLR_Pos (4UL)
5481#define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x10UL)
5482#define MCPWM_INTEN_CLR_IMAT1_CLR_Pos (5UL)
5483#define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x20UL)
5484#define MCPWM_INTEN_CLR_ICAP1_CLR_Pos (6UL)
5485#define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x40UL)
5486#define MCPWM_INTEN_CLR_ILIM2_CLR_Pos (8UL)
5487#define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x100UL)
5488#define MCPWM_INTEN_CLR_IMAT2_CLR_Pos (9UL)
5489#define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x200UL)
5490#define MCPWM_INTEN_CLR_ICAP2_CLR_Pos (10UL)
5491#define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x400UL)
5492#define MCPWM_INTEN_CLR_ABORT_CLR_Pos (15UL)
5493#define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x8000UL)
5494/* ========================================================= INTF ========================================================== */
5495#define MCPWM_INTF_ILIM0_F_Pos (0UL)
5496#define MCPWM_INTF_ILIM0_F_Msk (0x1UL)
5497#define MCPWM_INTF_IMAT0_F_Pos (1UL)
5498#define MCPWM_INTF_IMAT0_F_Msk (0x2UL)
5499#define MCPWM_INTF_ICAP0_F_Pos (2UL)
5500#define MCPWM_INTF_ICAP0_F_Msk (0x4UL)
5501#define MCPWM_INTF_ILIM1_F_Pos (4UL)
5502#define MCPWM_INTF_ILIM1_F_Msk (0x10UL)
5503#define MCPWM_INTF_IMAT1_F_Pos (5UL)
5504#define MCPWM_INTF_IMAT1_F_Msk (0x20UL)
5505#define MCPWM_INTF_ICAP1_F_Pos (6UL)
5506#define MCPWM_INTF_ICAP1_F_Msk (0x40UL)
5507#define MCPWM_INTF_ILIM2_F_Pos (8UL)
5508#define MCPWM_INTF_ILIM2_F_Msk (0x100UL)
5509#define MCPWM_INTF_IMAT2_F_Pos (9UL)
5510#define MCPWM_INTF_IMAT2_F_Msk (0x200UL)
5511#define MCPWM_INTF_ICAP2_F_Pos (10UL)
5512#define MCPWM_INTF_ICAP2_F_Msk (0x400UL)
5513#define MCPWM_INTF_ABORT_F_Pos (15UL)
5514#define MCPWM_INTF_ABORT_F_Msk (0x8000UL)
5515/* ======================================================= INTF_SET ======================================================== */
5516#define MCPWM_INTF_SET_ILIM0_F_SET_Pos (0UL)
5517#define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x1UL)
5518#define MCPWM_INTF_SET_IMAT0_F_SET_Pos (1UL)
5519#define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x2UL)
5520#define MCPWM_INTF_SET_ICAP0_F_SET_Pos (2UL)
5521#define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x4UL)
5522#define MCPWM_INTF_SET_ILIM1_F_SET_Pos (4UL)
5523#define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x10UL)
5524#define MCPWM_INTF_SET_IMAT1_F_SET_Pos (5UL)
5525#define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x20UL)
5526#define MCPWM_INTF_SET_ICAP1_F_SET_Pos (6UL)
5527#define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x40UL)
5528#define MCPWM_INTF_SET_ILIM2_F_SET_Pos (8UL)
5529#define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x100UL)
5530#define MCPWM_INTF_SET_IMAT2_F_SET_Pos (9UL)
5531#define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x200UL)
5532#define MCPWM_INTF_SET_ICAP2_F_SET_Pos (10UL)
5533#define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x400UL)
5534#define MCPWM_INTF_SET_ABORT_F_SET_Pos (15UL)
5535#define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x8000UL)
5536/* ======================================================= INTF_CLR ======================================================== */
5537#define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos (0UL)
5538#define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x1UL)
5539#define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos (1UL)
5540#define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x2UL)
5541#define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos (2UL)
5542#define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x4UL)
5543#define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos (4UL)
5544#define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x10UL)
5545#define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos (5UL)
5546#define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x20UL)
5547#define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos (6UL)
5548#define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x40UL)
5549#define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos (8UL)
5550#define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x100UL)
5551#define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos (9UL)
5552#define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x200UL)
5553#define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos (10UL)
5554#define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x400UL)
5555#define MCPWM_INTF_CLR_ABORT_F_CLR_Pos (15UL)
5556#define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x8000UL)
5557/* ======================================================== CNTCON ========================================================= */
5558#define MCPWM_CNTCON_TC0MCI0_RE_Pos (0UL)
5559#define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x1UL)
5560#define MCPWM_CNTCON_TC0MCI0_FE_Pos (1UL)
5561#define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x2UL)
5562#define MCPWM_CNTCON_TC0MCI1_RE_Pos (2UL)
5563#define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x4UL)
5564#define MCPWM_CNTCON_TC0MCI1_FE_Pos (3UL)
5565#define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x8UL)
5566#define MCPWM_CNTCON_TC0MCI2_RE_Pos (4UL)
5567#define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x10UL)
5568#define MCPWM_CNTCON_TC0MCI2_FE_Pos (5UL)
5569#define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x20UL)
5570#define MCPWM_CNTCON_TC1MCI0_RE_Pos (6UL)
5571#define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x40UL)
5572#define MCPWM_CNTCON_TC1MCI0_FE_Pos (7UL)
5573#define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x80UL)
5574#define MCPWM_CNTCON_TC1MCI1_RE_Pos (8UL)
5575#define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x100UL)
5576#define MCPWM_CNTCON_TC1MCI1_FE_Pos (9UL)
5577#define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x200UL)
5578#define MCPWM_CNTCON_TC1MCI2_RE_Pos (10UL)
5579#define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x400UL)
5580#define MCPWM_CNTCON_TC1MCI2_FE_Pos (11UL)
5581#define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x800UL)
5582#define MCPWM_CNTCON_TC2MCI0_RE_Pos (12UL)
5583#define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x1000UL)
5584#define MCPWM_CNTCON_TC2MCI0_FE_Pos (13UL)
5585#define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x2000UL)
5586#define MCPWM_CNTCON_TC2MCI1_RE_Pos (14UL)
5587#define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x4000UL)
5588#define MCPWM_CNTCON_TC2MCI1_FE_Pos (15UL)
5589#define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x8000UL)
5590#define MCPWM_CNTCON_TC2MCI2_RE_Pos (16UL)
5591#define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x10000UL)
5592#define MCPWM_CNTCON_TC2MCI2_FE_Pos (17UL)
5593#define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x20000UL)
5594#define MCPWM_CNTCON_CNTR0_Pos (29UL)
5595#define MCPWM_CNTCON_CNTR0_Msk (0x20000000UL)
5596#define MCPWM_CNTCON_CNTR1_Pos (30UL)
5597#define MCPWM_CNTCON_CNTR1_Msk (0x40000000UL)
5598#define MCPWM_CNTCON_CNTR2_Pos (31UL)
5599#define MCPWM_CNTCON_CNTR2_Msk (0x80000000UL)
5600/* ====================================================== CNTCON_SET ======================================================= */
5601#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos (0UL)
5602#define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x1UL)
5603#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos (1UL)
5604#define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x2UL)
5605#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos (2UL)
5606#define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x4UL)
5607#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos (3UL)
5608#define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x8UL)
5609#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos (4UL)
5610#define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x10UL)
5611#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos (5UL)
5612#define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x20UL)
5613#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos (6UL)
5614#define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x40UL)
5615#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos (7UL)
5616#define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x80UL)
5617#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos (8UL)
5618#define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x100UL)
5619#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos (9UL)
5620#define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x200UL)
5621#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos (10UL)
5622#define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x400UL)
5623#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos (11UL)
5624#define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x800UL)
5625#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos (12UL)
5626#define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x1000UL)
5627#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos (13UL)
5628#define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x2000UL)
5629#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos (14UL)
5630#define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x4000UL)
5631#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos (15UL)
5632#define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x8000UL)
5633#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos (16UL)
5634#define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x10000UL)
5635#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos (17UL)
5636#define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x20000UL)
5637#define MCPWM_CNTCON_SET_CNTR0_SET_Pos (29UL)
5638#define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x20000000UL)
5639#define MCPWM_CNTCON_SET_CNTR1_SET_Pos (30UL)
5640#define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x40000000UL)
5641#define MCPWM_CNTCON_SET_CNTR2_SET_Pos (31UL)
5642#define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x80000000UL)
5643/* ====================================================== CNTCON_CLR ======================================================= */
5644#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos (0UL)
5645#define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x1UL)
5646#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos (1UL)
5647#define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x2UL)
5648#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos (2UL)
5649#define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x4UL)
5650#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos (3UL)
5651#define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x8UL)
5652#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos (4UL)
5653#define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x10UL)
5654#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos (5UL)
5655#define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x20UL)
5656#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos (6UL)
5657#define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x40UL)
5658#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos (7UL)
5659#define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x80UL)
5660#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos (8UL)
5661#define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x100UL)
5662#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos (9UL)
5663#define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x200UL)
5664#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos (10UL)
5665#define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x400UL)
5666#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos (11UL)
5667#define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x800UL)
5668#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos (12UL)
5669#define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x1000UL)
5670#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos (13UL)
5671#define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x2000UL)
5672#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos (14UL)
5673#define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x4000UL)
5674#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos (15UL)
5675#define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x8000UL)
5676#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos (16UL)
5677#define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x10000UL)
5678#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos (17UL)
5679#define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x20000UL)
5680#define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos (29UL)
5681#define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x20000000UL)
5682#define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos (30UL)
5683#define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x40000000UL)
5684#define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos (31UL)
5685#define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x80000000UL)
5686/* ======================================================== CAP_CLR ======================================================== */
5687#define MCPWM_CAP_CLR_CAP_CLR0_Pos (0UL)
5688#define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x1UL)
5689#define MCPWM_CAP_CLR_CAP_CLR1_Pos (1UL)
5690#define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x2UL)
5691#define MCPWM_CAP_CLR_CAP_CLR2_Pos (2UL)
5692#define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x4UL)
5695/* =========================================================================================================================== */
5696/* ================ LPC_QEI ================ */
5697/* =========================================================================================================================== */
5698
5699/* ========================================================== CON ========================================================== */
5700#define QEI_CON_RESP_Pos (0UL)
5701#define QEI_CON_RESP_Msk (0x1UL)
5702#define QEI_CON_RESPI_Pos (1UL)
5703#define QEI_CON_RESPI_Msk (0x2UL)
5704#define QEI_CON_RESV_Pos (2UL)
5705#define QEI_CON_RESV_Msk (0x4UL)
5706#define QEI_CON_RESI_Pos (3UL)
5707#define QEI_CON_RESI_Msk (0x8UL)
5708/* ========================================================= CONF ========================================================== */
5709#define QEI_CONF_DIRINV_Pos (0UL)
5710#define QEI_CONF_DIRINV_Msk (0x1UL)
5711#define QEI_CONF_SIGMODE_Pos (1UL)
5712#define QEI_CONF_SIGMODE_Msk (0x2UL)
5713#define QEI_CONF_CAPMODE_Pos (2UL)
5714#define QEI_CONF_CAPMODE_Msk (0x4UL)
5715#define QEI_CONF_INVINX_Pos (3UL)
5716#define QEI_CONF_INVINX_Msk (0x8UL)
5717#define QEI_CONF_CRESPI_Pos (4UL)
5718#define QEI_CONF_CRESPI_Msk (0x10UL)
5719#define QEI_CONF_INXGATE_Pos (16UL)
5720#define QEI_CONF_INXGATE_Msk (0xf0000UL)
5721/* ========================================================= STAT ========================================================== */
5722#define QEI_STAT_DIR_Pos (0UL)
5723#define QEI_STAT_DIR_Msk (0x1UL)
5724/* ========================================================== POS ========================================================== */
5725#define QEI_POS_POS_Pos (0UL)
5726#define QEI_POS_POS_Msk (0xffffffffUL)
5727/* ======================================================== MAXPOS ========================================================= */
5728#define QEI_MAXPOS_MAXPOS_Pos (0UL)
5729#define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL)
5730/* ======================================================== CMPOS0 ========================================================= */
5731#define QEI_CMPOS0_PCMP0_Pos (0UL)
5732#define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL)
5733/* ======================================================== CMPOS1 ========================================================= */
5734#define QEI_CMPOS1_PCMP1_Pos (0UL)
5735#define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL)
5736/* ======================================================== CMPOS2 ========================================================= */
5737#define QEI_CMPOS2_PCMP2_Pos (0UL)
5738#define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL)
5739/* ======================================================== INXCNT ========================================================= */
5740#define QEI_INXCNT_ENCPOS_Pos (0UL)
5741#define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL)
5742/* ======================================================== INXCMP0 ======================================================== */
5743#define QEI_INXCMP0_ICMP0_Pos (0UL)
5744#define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL)
5745/* ========================================================= LOAD ========================================================== */
5746#define QEI_LOAD_VELLOAD_Pos (0UL)
5747#define QEI_LOAD_VELLOAD_Msk (0xffffffffUL)
5748/* ========================================================= TIME ========================================================== */
5749#define QEI_TIME_VELVAL_Pos (0UL)
5750#define QEI_TIME_VELVAL_Msk (0xffffffffUL)
5751/* ========================================================== VEL ========================================================== */
5752#define QEI_VEL_VELPC_Pos (0UL)
5753#define QEI_VEL_VELPC_Msk (0xffffffffUL)
5754/* ========================================================== CAP ========================================================== */
5755#define QEI_CAP_VELCAP_Pos (0UL)
5756#define QEI_CAP_VELCAP_Msk (0xffffffffUL)
5757/* ======================================================== VELCOMP ======================================================== */
5758#define QEI_VELCOMP_VELPC_Pos (0UL)
5759#define QEI_VELCOMP_VELPC_Msk (0xffffffffUL)
5760/* ======================================================== FILTER ========================================================= */
5761#define QEI_FILTER_FILTA_Pos (0UL)
5762#define QEI_FILTER_FILTA_Msk (0xffffffffUL)
5763/* ======================================================== INTSTAT ======================================================== */
5764#define QEI_INTSTAT_INX_INT_Pos (0UL)
5765#define QEI_INTSTAT_INX_INT_Msk (0x1UL)
5766#define QEI_INTSTAT_TIM_INT_Pos (1UL)
5767#define QEI_INTSTAT_TIM_INT_Msk (0x2UL)
5768#define QEI_INTSTAT_VELC_INT_Pos (2UL)
5769#define QEI_INTSTAT_VELC_INT_Msk (0x4UL)
5770#define QEI_INTSTAT_DIR_INT_Pos (3UL)
5771#define QEI_INTSTAT_DIR_INT_Msk (0x8UL)
5772#define QEI_INTSTAT_ERR_INT_Pos (4UL)
5773#define QEI_INTSTAT_ERR_INT_Msk (0x10UL)
5774#define QEI_INTSTAT_ENCLK_INT_Pos (5UL)
5775#define QEI_INTSTAT_ENCLK_INT_Msk (0x20UL)
5776#define QEI_INTSTAT_POS0_INT_Pos (6UL)
5777#define QEI_INTSTAT_POS0_INT_Msk (0x40UL)
5778#define QEI_INTSTAT_POS1_INT_Pos (7UL)
5779#define QEI_INTSTAT_POS1_INT_Msk (0x80UL)
5780#define QEI_INTSTAT_POS2_INT_Pos (8UL)
5781#define QEI_INTSTAT_POS2_INT_Msk (0x100UL)
5782#define QEI_INTSTAT_REV0_INT_Pos (9UL)
5783#define QEI_INTSTAT_REV0_INT_Msk (0x200UL)
5784#define QEI_INTSTAT_POS0REV_INT_Pos (10UL)
5785#define QEI_INTSTAT_POS0REV_INT_Msk (0x400UL)
5786#define QEI_INTSTAT_POS1REV_INT_Pos (11UL)
5787#define QEI_INTSTAT_POS1REV_INT_Msk (0x800UL)
5788#define QEI_INTSTAT_POS2REV_INT_Pos (12UL)
5789#define QEI_INTSTAT_POS2REV_INT_Msk (0x1000UL)
5790#define QEI_INTSTAT_REV1_INT_Pos (13UL)
5791#define QEI_INTSTAT_REV1_INT_Msk (0x2000UL)
5792#define QEI_INTSTAT_REV2_INT_Pos (14UL)
5793#define QEI_INTSTAT_REV2_INT_Msk (0x4000UL)
5794#define QEI_INTSTAT_MAXPOS_INT_Pos (15UL)
5795#define QEI_INTSTAT_MAXPOS_INT_Msk (0x8000UL)
5796/* ========================================================== SET ========================================================== */
5797#define QEI_SET_INX_INT_Pos (0UL)
5798#define QEI_SET_INX_INT_Msk (0x1UL)
5799#define QEI_SET_TIM_INT_Pos (1UL)
5800#define QEI_SET_TIM_INT_Msk (0x2UL)
5801#define QEI_SET_VELC_INT_Pos (2UL)
5802#define QEI_SET_VELC_INT_Msk (0x4UL)
5803#define QEI_SET_DIR_INT_Pos (3UL)
5804#define QEI_SET_DIR_INT_Msk (0x8UL)
5805#define QEI_SET_ERR_INT_Pos (4UL)
5806#define QEI_SET_ERR_INT_Msk (0x10UL)
5807#define QEI_SET_ENCLK_INT_Pos (5UL)
5808#define QEI_SET_ENCLK_INT_Msk (0x20UL)
5809#define QEI_SET_POS0_INT_Pos (6UL)
5810#define QEI_SET_POS0_INT_Msk (0x40UL)
5811#define QEI_SET_POS1_INT_Pos (7UL)
5812#define QEI_SET_POS1_INT_Msk (0x80UL)
5813#define QEI_SET_POS2_INT_Pos (8UL)
5814#define QEI_SET_POS2_INT_Msk (0x100UL)
5815#define QEI_SET_REV0_INT_Pos (9UL)
5816#define QEI_SET_REV0_INT_Msk (0x200UL)
5817#define QEI_SET_POS0REV_INT_Pos (10UL)
5818#define QEI_SET_POS0REV_INT_Msk (0x400UL)
5819#define QEI_SET_POS1REV_INT_Pos (11UL)
5820#define QEI_SET_POS1REV_INT_Msk (0x800UL)
5821#define QEI_SET_POS2REV_INT_Pos (12UL)
5822#define QEI_SET_POS2REV_INT_Msk (0x1000UL)
5823#define QEI_SET_REV1_INT_Pos (13UL)
5824#define QEI_SET_REV1_INT_Msk (0x2000UL)
5825#define QEI_SET_REV2_INT_Pos (14UL)
5826#define QEI_SET_REV2_INT_Msk (0x4000UL)
5827#define QEI_SET_MAXPOS_INT_Pos (15UL)
5828#define QEI_SET_MAXPOS_INT_Msk (0x8000UL)
5829/* ========================================================== CLR ========================================================== */
5830#define QEI_CLR_INX_INT_Pos (0UL)
5831#define QEI_CLR_INX_INT_Msk (0x1UL)
5832#define QEI_CLR_TIM_INT_Pos (1UL)
5833#define QEI_CLR_TIM_INT_Msk (0x2UL)
5834#define QEI_CLR_VELC_INT_Pos (2UL)
5835#define QEI_CLR_VELC_INT_Msk (0x4UL)
5836#define QEI_CLR_DIR_INT_Pos (3UL)
5837#define QEI_CLR_DIR_INT_Msk (0x8UL)
5838#define QEI_CLR_ERR_INT_Pos (4UL)
5839#define QEI_CLR_ERR_INT_Msk (0x10UL)
5840#define QEI_CLR_ENCLK_INT_Pos (5UL)
5841#define QEI_CLR_ENCLK_INT_Msk (0x20UL)
5842#define QEI_CLR_POS0_INT_Pos (6UL)
5843#define QEI_CLR_POS0_INT_Msk (0x40UL)
5844#define QEI_CLR_POS1_INT_Pos (7UL)
5845#define QEI_CLR_POS1_INT_Msk (0x80UL)
5846#define QEI_CLR_POS2_INT_Pos (8UL)
5847#define QEI_CLR_POS2_INT_Msk (0x100UL)
5848#define QEI_CLR_REV0_INT_Pos (9UL)
5849#define QEI_CLR_REV0_INT_Msk (0x200UL)
5850#define QEI_CLR_POS0REV_INT_Pos (10UL)
5851#define QEI_CLR_POS0REV_INT_Msk (0x400UL)
5852#define QEI_CLR_POS1REV_INT_Pos (11UL)
5853#define QEI_CLR_POS1REV_INT_Msk (0x800UL)
5854#define QEI_CLR_POS2REV_INT_Pos (12UL)
5855#define QEI_CLR_POS2REV_INT_Msk (0x1000UL)
5856#define QEI_CLR_REV1_INT_Pos (13UL)
5857#define QEI_CLR_REV1_INT_Msk (0x2000UL)
5858#define QEI_CLR_REV2_INT_Pos (14UL)
5859#define QEI_CLR_REV2_INT_Msk (0x4000UL)
5860#define QEI_CLR_MAXPOS_INT_Pos (15UL)
5861#define QEI_CLR_MAXPOS_INT_Msk (0x8000UL)
5862/* ========================================================== IE =========================================================== */
5863#define QEI_IE_INX_INT_Pos (0UL)
5864#define QEI_IE_INX_INT_Msk (0x1UL)
5865#define QEI_IE_TIM_INT_Pos (1UL)
5866#define QEI_IE_TIM_INT_Msk (0x2UL)
5867#define QEI_IE_VELC_INT_Pos (2UL)
5868#define QEI_IE_VELC_INT_Msk (0x4UL)
5869#define QEI_IE_DIR_INT_Pos (3UL)
5870#define QEI_IE_DIR_INT_Msk (0x8UL)
5871#define QEI_IE_ERR_INT_Pos (4UL)
5872#define QEI_IE_ERR_INT_Msk (0x10UL)
5873#define QEI_IE_ENCLK_INT_Pos (5UL)
5874#define QEI_IE_ENCLK_INT_Msk (0x20UL)
5875#define QEI_IE_POS0_INT_Pos (6UL)
5876#define QEI_IE_POS0_INT_Msk (0x40UL)
5877#define QEI_IE_POS1_INT_Pos (7UL)
5878#define QEI_IE_POS1_INT_Msk (0x80UL)
5879#define QEI_IE_POS2_INT_Pos (8UL)
5880#define QEI_IE_POS2_INT_Msk (0x100UL)
5881#define QEI_IE_REV0_INT_Pos (9UL)
5882#define QEI_IE_REV0_INT_Msk (0x200UL)
5883#define QEI_IE_POS0REV_INT_Pos (10UL)
5884#define QEI_IE_POS0REV_INT_Msk (0x400UL)
5885#define QEI_IE_POS1REV_INT_Pos (11UL)
5886#define QEI_IE_POS1REV_INT_Msk (0x800UL)
5887#define QEI_IE_POS2REV_INT_Pos (12UL)
5888#define QEI_IE_POS2REV_INT_Msk (0x1000UL)
5889#define QEI_IE_REV1_INT_Pos (13UL)
5890#define QEI_IE_REV1_INT_Msk (0x2000UL)
5891#define QEI_IE_REV2_INT_Pos (14UL)
5892#define QEI_IE_REV2_INT_Msk (0x4000UL)
5893#define QEI_IE_MAXPOS_INT_Pos (15UL)
5894#define QEI_IE_MAXPOS_INT_Msk (0x8000UL)
5895/* ========================================================== IES ========================================================== */
5896#define QEI_IES_INX_INT_Pos (0UL)
5897#define QEI_IES_INX_INT_Msk (0x1UL)
5898#define QEI_IES_TIM_INT_Pos (1UL)
5899#define QEI_IES_TIM_INT_Msk (0x2UL)
5900#define QEI_IES_VELC_INT_Pos (2UL)
5901#define QEI_IES_VELC_INT_Msk (0x4UL)
5902#define QEI_IES_DIR_INT_Pos (3UL)
5903#define QEI_IES_DIR_INT_Msk (0x8UL)
5904#define QEI_IES_ERR_INT_Pos (4UL)
5905#define QEI_IES_ERR_INT_Msk (0x10UL)
5906#define QEI_IES_ENCLK_INT_Pos (5UL)
5907#define QEI_IES_ENCLK_INT_Msk (0x20UL)
5908#define QEI_IES_POS0_INT_Pos (6UL)
5909#define QEI_IES_POS0_INT_Msk (0x40UL)
5910#define QEI_IES_POS1_INT_Pos (7UL)
5911#define QEI_IES_POS1_INT_Msk (0x80UL)
5912#define QEI_IES_POS2_INT_Pos (8UL)
5913#define QEI_IES_POS2_INT_Msk (0x100UL)
5914#define QEI_IES_REV0_INT_Pos (9UL)
5915#define QEI_IES_REV0_INT_Msk (0x200UL)
5916#define QEI_IES_POS0REV_INT_Pos (10UL)
5917#define QEI_IES_POS0REV_INT_Msk (0x400UL)
5918#define QEI_IES_POS1REV_INT_Pos (11UL)
5919#define QEI_IES_POS1REV_INT_Msk (0x800UL)
5920#define QEI_IES_POS2REV_INT_Pos (12UL)
5921#define QEI_IES_POS2REV_INT_Msk (0x1000UL)
5922#define QEI_IES_REV1_INT_Pos (13UL)
5923#define QEI_IES_REV1_INT_Msk (0x2000UL)
5924#define QEI_IES_REV2_INT_Pos (14UL)
5925#define QEI_IES_REV2_INT_Msk (0x4000UL)
5926#define QEI_IES_MAXPOS_INT_Pos (15UL)
5927#define QEI_IES_MAXPOS_INT_Msk (0x8000UL)
5928/* ========================================================== IEC ========================================================== */
5929#define QEI_IEC_INX_INT_Pos (0UL)
5930#define QEI_IEC_INX_INT_Msk (0x1UL)
5931#define QEI_IEC_TIM_INT_Pos (1UL)
5932#define QEI_IEC_TIM_INT_Msk (0x2UL)
5933#define QEI_IEC_VELC_INT_Pos (2UL)
5934#define QEI_IEC_VELC_INT_Msk (0x4UL)
5935#define QEI_IEC_DIR_INT_Pos (3UL)
5936#define QEI_IEC_DIR_INT_Msk (0x8UL)
5937#define QEI_IEC_ERR_INT_Pos (4UL)
5938#define QEI_IEC_ERR_INT_Msk (0x10UL)
5939#define QEI_IEC_ENCLK_INT_Pos (5UL)
5940#define QEI_IEC_ENCLK_INT_Msk (0x20UL)
5941#define QEI_IEC_POS0_INT_Pos (6UL)
5942#define QEI_IEC_POS0_INT_Msk (0x40UL)
5943#define QEI_IEC_POS1_INT_Pos (7UL)
5944#define QEI_IEC_POS1_INT_Msk (0x80UL)
5945#define QEI_IEC_POS2_INT_Pos (8UL)
5946#define QEI_IEC_POS2_INT_Msk (0x100UL)
5947#define QEI_IEC_REV0_INT_Pos (9UL)
5948#define QEI_IEC_REV0_INT_Msk (0x200UL)
5949#define QEI_IEC_POS0REV_INT_Pos (10UL)
5950#define QEI_IEC_POS0REV_INT_Msk (0x400UL)
5951#define QEI_IEC_POS1REV_INT_Pos (11UL)
5952#define QEI_IEC_POS1REV_INT_Msk (0x800UL)
5953#define QEI_IEC_POS2REV_INT_Pos (12UL)
5954#define QEI_IEC_POS2REV_INT_Msk (0x1000UL)
5955#define QEI_IEC_REV1_INT_Pos (13UL)
5956#define QEI_IEC_REV1_INT_Msk (0x2000UL)
5957#define QEI_IEC_REV2_INT_Pos (14UL)
5958#define QEI_IEC_REV2_INT_Msk (0x4000UL)
5959#define QEI_IEC_MAXPOS_INT_Pos (15UL)
5960#define QEI_IEC_MAXPOS_INT_Msk (0x8000UL)
5963/* =========================================================================================================================== */
5964/* ================ LPC_SYSCON ================ */
5965/* =========================================================================================================================== */
5966
5967/* ======================================================= FLASHCFG ======================================================== */
5968#define SYSCON_FLASHCFG_FLASHTIM_Pos (12UL)
5969#define SYSCON_FLASHCFG_FLASHTIM_Msk (0xf000UL)
5970/* ======================================================== PLL0CON ======================================================== */
5971#define SYSCON_PLL0CON_PLLE0_Pos (0UL)
5972#define SYSCON_PLL0CON_PLLE0_Msk (0x1UL)
5973#define SYSCON_PLL0CON_PLLC0_Pos (1UL)
5974#define SYSCON_PLL0CON_PLLC0_Msk (0x2UL)
5975/* ======================================================== PLL0CFG ======================================================== */
5976#define SYSCON_PLL0CFG_MSEL0_Pos (0UL)
5977#define SYSCON_PLL0CFG_MSEL0_Msk (0x7fffUL)
5978#define SYSCON_PLL0CFG_NSEL0_Pos (16UL)
5979#define SYSCON_PLL0CFG_NSEL0_Msk (0xff0000UL)
5980/* ======================================================= PLL0STAT ======================================================== */
5981#define SYSCON_PLL0STAT_MSEL0_Pos (0UL)
5982#define SYSCON_PLL0STAT_MSEL0_Msk (0x7fffUL)
5983#define SYSCON_PLL0STAT_NSEL0_Pos (16UL)
5984#define SYSCON_PLL0STAT_NSEL0_Msk (0xff0000UL)
5985#define SYSCON_PLL0STAT_PLLE0_STAT_Pos (24UL)
5986#define SYSCON_PLL0STAT_PLLE0_STAT_Msk (0x1000000UL)
5987#define SYSCON_PLL0STAT_PLLC0_STAT_Pos (25UL)
5988#define SYSCON_PLL0STAT_PLLC0_STAT_Msk (0x2000000UL)
5989#define SYSCON_PLL0STAT_PLOCK0_Pos (26UL)
5990#define SYSCON_PLL0STAT_PLOCK0_Msk (0x4000000UL)
5991/* ======================================================= PLL0FEED ======================================================== */
5992#define SYSCON_PLL0FEED_PLL0FEED_Pos (0UL)
5993#define SYSCON_PLL0FEED_PLL0FEED_Msk (0xffUL)
5994/* ======================================================== PLL1CON ======================================================== */
5995#define SYSCON_PLL1CON_PLLE1_Pos (0UL)
5996#define SYSCON_PLL1CON_PLLE1_Msk (0x1UL)
5997#define SYSCON_PLL1CON_PLLC1_Pos (1UL)
5998#define SYSCON_PLL1CON_PLLC1_Msk (0x2UL)
5999/* ======================================================== PLL1CFG ======================================================== */
6000#define SYSCON_PLL1CFG_MSEL1_Pos (0UL)
6001#define SYSCON_PLL1CFG_MSEL1_Msk (0x1fUL)
6002#define SYSCON_PLL1CFG_PSEL1_Pos (5UL)
6003#define SYSCON_PLL1CFG_PSEL1_Msk (0x60UL)
6004/* ======================================================= PLL1STAT ======================================================== */
6005#define SYSCON_PLL1STAT_MSEL1_Pos (0UL)
6006#define SYSCON_PLL1STAT_MSEL1_Msk (0x1fUL)
6007#define SYSCON_PLL1STAT_PSEL1_Pos (5UL)
6008#define SYSCON_PLL1STAT_PSEL1_Msk (0x60UL)
6009#define SYSCON_PLL1STAT_PLLE1_STAT_Pos (8UL)
6010#define SYSCON_PLL1STAT_PLLE1_STAT_Msk (0x100UL)
6011#define SYSCON_PLL1STAT_PLLC1_STAT_Pos (9UL)
6012#define SYSCON_PLL1STAT_PLLC1_STAT_Msk (0x200UL)
6013#define SYSCON_PLL1STAT_PLOCK1_Pos (10UL)
6014#define SYSCON_PLL1STAT_PLOCK1_Msk (0x400UL)
6015/* ======================================================= PLL1FEED ======================================================== */
6016#define SYSCON_PLL1FEED_PLL1FEED_Pos (0UL)
6017#define SYSCON_PLL1FEED_PLL1FEED_Msk (0xffUL)
6018/* ========================================================= PCON ========================================================== */
6019#define SYSCON_PCON_PM0_Pos (0UL)
6020#define SYSCON_PCON_PM0_Msk (0x1UL)
6021#define SYSCON_PCON_PM1_Pos (1UL)
6022#define SYSCON_PCON_PM1_Msk (0x2UL)
6023#define SYSCON_PCON_BODRPM_Pos (2UL)
6024#define SYSCON_PCON_BODRPM_Msk (0x4UL)
6025#define SYSCON_PCON_BOGD_Pos (3UL)
6026#define SYSCON_PCON_BOGD_Msk (0x8UL)
6027#define SYSCON_PCON_BORD_Pos (4UL)
6028#define SYSCON_PCON_BORD_Msk (0x10UL)
6029#define SYSCON_PCON_SMFLAG_Pos (8UL)
6030#define SYSCON_PCON_SMFLAG_Msk (0x100UL)
6031#define SYSCON_PCON_DSFLAG_Pos (9UL)
6032#define SYSCON_PCON_DSFLAG_Msk (0x200UL)
6033#define SYSCON_PCON_PDFLAG_Pos (10UL)
6034#define SYSCON_PCON_PDFLAG_Msk (0x400UL)
6035#define SYSCON_PCON_DPDFLAG_Pos (11UL)
6036#define SYSCON_PCON_DPDFLAG_Msk (0x800UL)
6037/* ========================================================= PCONP ========================================================= */
6038#define SYSCON_PCONP_PCTIM0_Pos (1UL)
6039#define SYSCON_PCONP_PCTIM0_Msk (0x2UL)
6040#define SYSCON_PCONP_PCTIM1_Pos (2UL)
6041#define SYSCON_PCONP_PCTIM1_Msk (0x4UL)
6042#define SYSCON_PCONP_PCUART0_Pos (3UL)
6043#define SYSCON_PCONP_PCUART0_Msk (0x8UL)
6044#define SYSCON_PCONP_PCUART1_Pos (4UL)
6045#define SYSCON_PCONP_PCUART1_Msk (0x10UL)
6046#define SYSCON_PCONP_PCPWM1_Pos (6UL)
6047#define SYSCON_PCONP_PCPWM1_Msk (0x40UL)
6048#define SYSCON_PCONP_PCI2C0_Pos (7UL)
6049#define SYSCON_PCONP_PCI2C0_Msk (0x80UL)
6050#define SYSCON_PCONP_PCSPI_Pos (8UL)
6051#define SYSCON_PCONP_PCSPI_Msk (0x100UL)
6052#define SYSCON_PCONP_PCRTC_Pos (9UL)
6053#define SYSCON_PCONP_PCRTC_Msk (0x200UL)
6054#define SYSCON_PCONP_PCSSP1_Pos (10UL)
6055#define SYSCON_PCONP_PCSSP1_Msk (0x400UL)
6056#define SYSCON_PCONP_PCADC_Pos (12UL)
6057#define SYSCON_PCONP_PCADC_Msk (0x1000UL)
6058#define SYSCON_PCONP_PCCAN1_Pos (13UL)
6059#define SYSCON_PCONP_PCCAN1_Msk (0x2000UL)
6060#define SYSCON_PCONP_PCCAN2_Pos (14UL)
6061#define SYSCON_PCONP_PCCAN2_Msk (0x4000UL)
6062#define SYSCON_PCONP_PCGPIO_Pos (15UL)
6063#define SYSCON_PCONP_PCGPIO_Msk (0x8000UL)
6064#define SYSCON_PCONP_PCRIT_Pos (16UL)
6065#define SYSCON_PCONP_PCRIT_Msk (0x10000UL)
6066#define SYSCON_PCONP_PCMCPWM_Pos (17UL)
6067#define SYSCON_PCONP_PCMCPWM_Msk (0x20000UL)
6068#define SYSCON_PCONP_PCQEI_Pos (18UL)
6069#define SYSCON_PCONP_PCQEI_Msk (0x40000UL)
6070#define SYSCON_PCONP_PCI2C1_Pos (19UL)
6071#define SYSCON_PCONP_PCI2C1_Msk (0x80000UL)
6072#define SYSCON_PCONP_PCSSP0_Pos (21UL)
6073#define SYSCON_PCONP_PCSSP0_Msk (0x200000UL)
6074#define SYSCON_PCONP_PCTIM2_Pos (22UL)
6075#define SYSCON_PCONP_PCTIM2_Msk (0x400000UL)
6076#define SYSCON_PCONP_PCTIM3_Pos (23UL)
6077#define SYSCON_PCONP_PCTIM3_Msk (0x800000UL)
6078#define SYSCON_PCONP_PCUART2_Pos (24UL)
6079#define SYSCON_PCONP_PCUART2_Msk (0x1000000UL)
6080#define SYSCON_PCONP_PCUART3_Pos (25UL)
6081#define SYSCON_PCONP_PCUART3_Msk (0x2000000UL)
6082#define SYSCON_PCONP_PCI2C2_Pos (26UL)
6083#define SYSCON_PCONP_PCI2C2_Msk (0x4000000UL)
6084#define SYSCON_PCONP_PCI2S_Pos (27UL)
6085#define SYSCON_PCONP_PCI2S_Msk (0x8000000UL)
6086#define SYSCON_PCONP_PCGPDMA_Pos (29UL)
6087#define SYSCON_PCONP_PCGPDMA_Msk (0x20000000UL)
6088#define SYSCON_PCONP_PCENET_Pos (30UL)
6089#define SYSCON_PCONP_PCENET_Msk (0x40000000UL)
6090#define SYSCON_PCONP_PCUSB_Pos (31UL)
6091#define SYSCON_PCONP_PCUSB_Msk (0x80000000UL)
6092/* ======================================================== CCLKCFG ======================================================== */
6093#define SYSCON_CCLKCFG_CCLKSEL_Pos (0UL)
6094#define SYSCON_CCLKCFG_CCLKSEL_Msk (0xffUL)
6095/* ======================================================= USBCLKCFG ======================================================= */
6096#define SYSCON_USBCLKCFG_USBSEL_Pos (0UL)
6097#define SYSCON_USBCLKCFG_USBSEL_Msk (0xfUL)
6098/* ======================================================= CLKSRCSEL ======================================================= */
6099#define SYSCON_CLKSRCSEL_CLKSRC_Pos (0UL)
6100#define SYSCON_CLKSRCSEL_CLKSRC_Msk (0x3UL)
6101/* ====================================================== CANSLEEPCLR ====================================================== */
6102#define SYSCON_CANSLEEPCLR_CAN1SLEEP_Pos (1UL)
6103#define SYSCON_CANSLEEPCLR_CAN1SLEEP_Msk (0x2UL)
6104#define SYSCON_CANSLEEPCLR_CAN2SLEEP_Pos (2UL)
6105#define SYSCON_CANSLEEPCLR_CAN2SLEEP_Msk (0x4UL)
6106/* ===================================================== CANWAKEFLAGS ====================================================== */
6107#define SYSCON_CANWAKEFLAGS_CAN1WAKE_Pos (1UL)
6108#define SYSCON_CANWAKEFLAGS_CAN1WAKE_Msk (0x2UL)
6109#define SYSCON_CANWAKEFLAGS_CAN2WAKE_Pos (2UL)
6110#define SYSCON_CANWAKEFLAGS_CAN2WAKE_Msk (0x4UL)
6111/* ======================================================== EXTINT ========================================================= */
6112#define SYSCON_EXTINT_EINT0_Pos (0UL)
6113#define SYSCON_EXTINT_EINT0_Msk (0x1UL)
6114#define SYSCON_EXTINT_EINT1_Pos (1UL)
6115#define SYSCON_EXTINT_EINT1_Msk (0x2UL)
6116#define SYSCON_EXTINT_EINT2_Pos (2UL)
6117#define SYSCON_EXTINT_EINT2_Msk (0x4UL)
6118#define SYSCON_EXTINT_EINT3_Pos (3UL)
6119#define SYSCON_EXTINT_EINT3_Msk (0x8UL)
6120/* ======================================================== EXTMODE ======================================================== */
6121#define SYSCON_EXTMODE_EXTMODE0_Pos (0UL)
6122#define SYSCON_EXTMODE_EXTMODE0_Msk (0x1UL)
6123#define SYSCON_EXTMODE_EXTMODE1_Pos (1UL)
6124#define SYSCON_EXTMODE_EXTMODE1_Msk (0x2UL)
6125#define SYSCON_EXTMODE_EXTMODE2_Pos (2UL)
6126#define SYSCON_EXTMODE_EXTMODE2_Msk (0x4UL)
6127#define SYSCON_EXTMODE_EXTMODE3_Pos (3UL)
6128#define SYSCON_EXTMODE_EXTMODE3_Msk (0x8UL)
6129/* ======================================================= EXTPOLAR ======================================================== */
6130#define SYSCON_EXTPOLAR_EXTPOLAR0_Pos (0UL)
6131#define SYSCON_EXTPOLAR_EXTPOLAR0_Msk (0x1UL)
6132#define SYSCON_EXTPOLAR_EXTPOLAR1_Pos (1UL)
6133#define SYSCON_EXTPOLAR_EXTPOLAR1_Msk (0x2UL)
6134#define SYSCON_EXTPOLAR_EXTPOLAR2_Pos (2UL)
6135#define SYSCON_EXTPOLAR_EXTPOLAR2_Msk (0x4UL)
6136#define SYSCON_EXTPOLAR_EXTPOLAR3_Pos (3UL)
6137#define SYSCON_EXTPOLAR_EXTPOLAR3_Msk (0x8UL)
6138/* ========================================================= RSID ========================================================== */
6139#define SYSCON_RSID_POR_Pos (0UL)
6140#define SYSCON_RSID_POR_Msk (0x1UL)
6141#define SYSCON_RSID_EXTR_Pos (1UL)
6142#define SYSCON_RSID_EXTR_Msk (0x2UL)
6143#define SYSCON_RSID_WDTR_Pos (2UL)
6144#define SYSCON_RSID_WDTR_Msk (0x4UL)
6145#define SYSCON_RSID_BODR_Pos (3UL)
6146#define SYSCON_RSID_BODR_Msk (0x8UL)
6147/* ========================================================== SCS ========================================================== */
6148#define SYSCON_SCS_OSCRANGE_Pos (4UL)
6149#define SYSCON_SCS_OSCRANGE_Msk (0x10UL)
6150#define SYSCON_SCS_OSCEN_Pos (5UL)
6151#define SYSCON_SCS_OSCEN_Msk (0x20UL)
6152#define SYSCON_SCS_OSCSTAT_Pos (6UL)
6153#define SYSCON_SCS_OSCSTAT_Msk (0x40UL)
6154/* ======================================================= PCLKSEL0 ======================================================== */
6155#define SYSCON_PCLKSEL0_PCLK_WDT_Pos (0UL)
6156#define SYSCON_PCLKSEL0_PCLK_WDT_Msk (0x3UL)
6157#define SYSCON_PCLKSEL0_PCLK_TIMER0_Pos (2UL)
6158#define SYSCON_PCLKSEL0_PCLK_TIMER0_Msk (0xcUL)
6159#define SYSCON_PCLKSEL0_PCLK_TIMER1_Pos (4UL)
6160#define SYSCON_PCLKSEL0_PCLK_TIMER1_Msk (0x30UL)
6161#define SYSCON_PCLKSEL0_PCLK_UART0_Pos (6UL)
6162#define SYSCON_PCLKSEL0_PCLK_UART0_Msk (0xc0UL)
6163#define SYSCON_PCLKSEL0_PCLK_UART1_Pos (8UL)
6164#define SYSCON_PCLKSEL0_PCLK_UART1_Msk (0x300UL)
6165#define SYSCON_PCLKSEL0_PCLK_PWM1_Pos (12UL)
6166#define SYSCON_PCLKSEL0_PCLK_PWM1_Msk (0x3000UL)
6167#define SYSCON_PCLKSEL0_PCLK_I2C0_Pos (14UL)
6168#define SYSCON_PCLKSEL0_PCLK_I2C0_Msk (0xc000UL)
6169#define SYSCON_PCLKSEL0_PCLK_SPI_Pos (16UL)
6170#define SYSCON_PCLKSEL0_PCLK_SPI_Msk (0x30000UL)
6171#define SYSCON_PCLKSEL0_PCLK_SSP1_Pos (20UL)
6172#define SYSCON_PCLKSEL0_PCLK_SSP1_Msk (0x300000UL)
6173#define SYSCON_PCLKSEL0_PCLK_DAC_Pos (22UL)
6174#define SYSCON_PCLKSEL0_PCLK_DAC_Msk (0xc00000UL)
6175#define SYSCON_PCLKSEL0_PCLK_ADC_Pos (24UL)
6176#define SYSCON_PCLKSEL0_PCLK_ADC_Msk (0x3000000UL)
6177#define SYSCON_PCLKSEL0_PCLK_CAN1_Pos (26UL)
6178#define SYSCON_PCLKSEL0_PCLK_CAN1_Msk (0xc000000UL)
6179#define SYSCON_PCLKSEL0_PCLK_CAN2_Pos (28UL)
6180#define SYSCON_PCLKSEL0_PCLK_CAN2_Msk (0x30000000UL)
6181#define SYSCON_PCLKSEL0_PCLK_ACF_Pos (30UL)
6182#define SYSCON_PCLKSEL0_PCLK_ACF_Msk (0xc0000000UL)
6183/* ======================================================= PCLKSEL1 ======================================================== */
6184#define SYSCON_PCLKSEL1_PCLK_QEI_Pos (0UL)
6185#define SYSCON_PCLKSEL1_PCLK_QEI_Msk (0x3UL)
6186#define SYSCON_PCLKSEL1_PCLK_GPIOINT_Pos (2UL)
6187#define SYSCON_PCLKSEL1_PCLK_GPIOINT_Msk (0xcUL)
6188#define SYSCON_PCLKSEL1_PCLK_PCB_Pos (4UL)
6189#define SYSCON_PCLKSEL1_PCLK_PCB_Msk (0x30UL)
6190#define SYSCON_PCLKSEL1_PCLK_I2C1_Pos (6UL)
6191#define SYSCON_PCLKSEL1_PCLK_I2C1_Msk (0xc0UL)
6192#define SYSCON_PCLKSEL1_PCLK_SSP0_Pos (10UL)
6193#define SYSCON_PCLKSEL1_PCLK_SSP0_Msk (0xc00UL)
6194#define SYSCON_PCLKSEL1_PCLK_TIMER2_Pos (12UL)
6195#define SYSCON_PCLKSEL1_PCLK_TIMER2_Msk (0x3000UL)
6196#define SYSCON_PCLKSEL1_PCLK_TIMER3_Pos (14UL)
6197#define SYSCON_PCLKSEL1_PCLK_TIMER3_Msk (0xc000UL)
6198#define SYSCON_PCLKSEL1_PCLK_UART2_Pos (16UL)
6199#define SYSCON_PCLKSEL1_PCLK_UART2_Msk (0x30000UL)
6200#define SYSCON_PCLKSEL1_PCLK_UART3_Pos (18UL)
6201#define SYSCON_PCLKSEL1_PCLK_UART3_Msk (0xc0000UL)
6202#define SYSCON_PCLKSEL1_PCLK_I2C2_Pos (20UL)
6203#define SYSCON_PCLKSEL1_PCLK_I2C2_Msk (0x300000UL)
6204#define SYSCON_PCLKSEL1_PCLK_I2S_Pos (22UL)
6205#define SYSCON_PCLKSEL1_PCLK_I2S_Msk (0xc00000UL)
6206#define SYSCON_PCLKSEL1_PCLK_RIT_Pos (26UL)
6207#define SYSCON_PCLKSEL1_PCLK_RIT_Msk (0xc000000UL)
6208#define SYSCON_PCLKSEL1_PCLK_SYSCON_Pos (28UL)
6209#define SYSCON_PCLKSEL1_PCLK_SYSCON_Msk (0x30000000UL)
6210#define SYSCON_PCLKSEL1_PCLK_MC_Pos (30UL)
6211#define SYSCON_PCLKSEL1_PCLK_MC_Msk (0xc0000000UL)
6212/* ======================================================= USBINTST ======================================================== */
6213#define SYSCON_USBINTST_USB_INT_REQ_LP_Pos (0UL)
6214#define SYSCON_USBINTST_USB_INT_REQ_LP_Msk (0x1UL)
6215#define SYSCON_USBINTST_USB_INT_REQ_HP_Pos (1UL)
6216#define SYSCON_USBINTST_USB_INT_REQ_HP_Msk (0x2UL)
6217#define SYSCON_USBINTST_USB_INT_REQ_DMA_Pos (2UL)
6218#define SYSCON_USBINTST_USB_INT_REQ_DMA_Msk (0x4UL)
6219#define SYSCON_USBINTST_USB_HOST_INT_Pos (3UL)
6220#define SYSCON_USBINTST_USB_HOST_INT_Msk (0x8UL)
6221#define SYSCON_USBINTST_USB_ATX_INT_Pos (4UL)
6222#define SYSCON_USBINTST_USB_ATX_INT_Msk (0x10UL)
6223#define SYSCON_USBINTST_USB_OTG_INT_Pos (5UL)
6224#define SYSCON_USBINTST_USB_OTG_INT_Msk (0x20UL)
6225#define SYSCON_USBINTST_USB_I2C_INT_Pos (6UL)
6226#define SYSCON_USBINTST_USB_I2C_INT_Msk (0x40UL)
6227#define SYSCON_USBINTST_USB_NEED_CLK_Pos (8UL)
6228#define SYSCON_USBINTST_USB_NEED_CLK_Msk (0x100UL)
6229#define SYSCON_USBINTST_EN_USB_INTS_Pos (31UL)
6230#define SYSCON_USBINTST_EN_USB_INTS_Msk (0x80000000UL)
6231/* ====================================================== DMACREQSEL ======================================================= */
6232#define SYSCON_DMACREQSEL_DMASEL08_Pos (0UL)
6233#define SYSCON_DMACREQSEL_DMASEL08_Msk (0x1UL)
6234#define SYSCON_DMACREQSEL_DMASEL09_Pos (1UL)
6235#define SYSCON_DMACREQSEL_DMASEL09_Msk (0x2UL)
6236#define SYSCON_DMACREQSEL_DMASEL10_Pos (2UL)
6237#define SYSCON_DMACREQSEL_DMASEL10_Msk (0x4UL)
6238#define SYSCON_DMACREQSEL_DMASEL11_Pos (3UL)
6239#define SYSCON_DMACREQSEL_DMASEL11_Msk (0x8UL)
6240#define SYSCON_DMACREQSEL_DMASEL12_Pos (4UL)
6241#define SYSCON_DMACREQSEL_DMASEL12_Msk (0x10UL)
6242#define SYSCON_DMACREQSEL_DMASEL13_Pos (5UL)
6243#define SYSCON_DMACREQSEL_DMASEL13_Msk (0x20UL)
6244#define SYSCON_DMACREQSEL_DMASEL14_Pos (6UL)
6245#define SYSCON_DMACREQSEL_DMASEL14_Msk (0x40UL)
6246#define SYSCON_DMACREQSEL_DMASEL15_Pos (7UL)
6247#define SYSCON_DMACREQSEL_DMASEL15_Msk (0x80UL)
6248/* ======================================================= CLKOUTCFG ======================================================= */
6249#define SYSCON_CLKOUTCFG_CLKOUTSEL_Pos (0UL)
6250#define SYSCON_CLKOUTCFG_CLKOUTSEL_Msk (0xfUL)
6251#define SYSCON_CLKOUTCFG_CLKOUTDIV_Pos (4UL)
6252#define SYSCON_CLKOUTCFG_CLKOUTDIV_Msk (0xf0UL)
6253#define SYSCON_CLKOUTCFG_CLKOUT_EN_Pos (8UL)
6254#define SYSCON_CLKOUTCFG_CLKOUT_EN_Msk (0x100UL)
6255#define SYSCON_CLKOUTCFG_CLKOUT_ACT_Pos (9UL)
6256#define SYSCON_CLKOUTCFG_CLKOUT_ACT_Msk (0x200UL)
6259/* =========================================================================================================================== */
6260/* ================ LPC_EMAC ================ */
6261/* =========================================================================================================================== */
6262
6263/* ========================================================= MAC1 ========================================================== */
6264#define EMAC_MAC1_RXENABLE_Pos (0UL)
6265#define EMAC_MAC1_RXENABLE_Msk (0x1UL)
6266#define EMAC_MAC1_PARF_Pos (1UL)
6267#define EMAC_MAC1_PARF_Msk (0x2UL)
6268#define EMAC_MAC1_RXFLOWCTRL_Pos (2UL)
6269#define EMAC_MAC1_RXFLOWCTRL_Msk (0x4UL)
6270#define EMAC_MAC1_TXFLOWCTRL_Pos (3UL)
6271#define EMAC_MAC1_TXFLOWCTRL_Msk (0x8UL)
6272#define EMAC_MAC1_LOOPBACK_Pos (4UL)
6273#define EMAC_MAC1_LOOPBACK_Msk (0x10UL)
6274#define EMAC_MAC1_RESETTX_Pos (8UL)
6275#define EMAC_MAC1_RESETTX_Msk (0x100UL)
6276#define EMAC_MAC1_RESETMCSTX_Pos (9UL)
6277#define EMAC_MAC1_RESETMCSTX_Msk (0x200UL)
6278#define EMAC_MAC1_RESETRX_Pos (10UL)
6279#define EMAC_MAC1_RESETRX_Msk (0x400UL)
6280#define EMAC_MAC1_RESETMCSRX_Pos (11UL)
6281#define EMAC_MAC1_RESETMCSRX_Msk (0x800UL)
6282#define EMAC_MAC1_SIMRESET_Pos (14UL)
6283#define EMAC_MAC1_SIMRESET_Msk (0x4000UL)
6284#define EMAC_MAC1_SOFTRESET_Pos (15UL)
6285#define EMAC_MAC1_SOFTRESET_Msk (0x8000UL)
6286/* ========================================================= MAC2 ========================================================== */
6287#define EMAC_MAC2_FULLDUPLEX_Pos (0UL)
6288#define EMAC_MAC2_FULLDUPLEX_Msk (0x1UL)
6289#define EMAC_MAC2_FLC_Pos (1UL)
6290#define EMAC_MAC2_FLC_Msk (0x2UL)
6291#define EMAC_MAC2_HFEN_Pos (2UL)
6292#define EMAC_MAC2_HFEN_Msk (0x4UL)
6293#define EMAC_MAC2_DELAYEDCRC_Pos (3UL)
6294#define EMAC_MAC2_DELAYEDCRC_Msk (0x8UL)
6295#define EMAC_MAC2_CRCEN_Pos (4UL)
6296#define EMAC_MAC2_CRCEN_Msk (0x10UL)
6297#define EMAC_MAC2_PADCRCEN_Pos (5UL)
6298#define EMAC_MAC2_PADCRCEN_Msk (0x20UL)
6299#define EMAC_MAC2_VLANPADEN_Pos (6UL)
6300#define EMAC_MAC2_VLANPADEN_Msk (0x40UL)
6301#define EMAC_MAC2_AUTODETPADEN_Pos (7UL)
6302#define EMAC_MAC2_AUTODETPADEN_Msk (0x80UL)
6303#define EMAC_MAC2_PPENF_Pos (8UL)
6304#define EMAC_MAC2_PPENF_Msk (0x100UL)
6305#define EMAC_MAC2_LPENF_Pos (9UL)
6306#define EMAC_MAC2_LPENF_Msk (0x200UL)
6307#define EMAC_MAC2_NOBACKOFF_Pos (12UL)
6308#define EMAC_MAC2_NOBACKOFF_Msk (0x1000UL)
6309#define EMAC_MAC2_BP_NOBACKOFF_Pos (13UL)
6310#define EMAC_MAC2_BP_NOBACKOFF_Msk (0x2000UL)
6311#define EMAC_MAC2_EXCESSDEFER_Pos (14UL)
6312#define EMAC_MAC2_EXCESSDEFER_Msk (0x4000UL)
6313/* ========================================================= IPGT ========================================================== */
6314#define EMAC_IPGT_BTOBINTEGAP_Pos (0UL)
6315#define EMAC_IPGT_BTOBINTEGAP_Msk (0x7fUL)
6316/* ========================================================= IPGR ========================================================== */
6317#define EMAC_IPGR_NBTOBINTEGAP2_Pos (0UL)
6318#define EMAC_IPGR_NBTOBINTEGAP2_Msk (0x7fUL)
6319#define EMAC_IPGR_NBTOBINTEGAP1_Pos (8UL)
6320#define EMAC_IPGR_NBTOBINTEGAP1_Msk (0x7f00UL)
6321/* ========================================================= CLRT ========================================================== */
6322#define EMAC_CLRT_RETRANSMAX_Pos (0UL)
6323#define EMAC_CLRT_RETRANSMAX_Msk (0xfUL)
6324#define EMAC_CLRT_COLLWIN_Pos (8UL)
6325#define EMAC_CLRT_COLLWIN_Msk (0x3f00UL)
6326/* ========================================================= MAXF ========================================================== */
6327#define EMAC_MAXF_MAXFLEN_Pos (0UL)
6328#define EMAC_MAXF_MAXFLEN_Msk (0xffffUL)
6329/* ========================================================= SUPP ========================================================== */
6330#define EMAC_SUPP_SPEED_Pos (8UL)
6331#define EMAC_SUPP_SPEED_Msk (0x100UL)
6332/* ========================================================= TEST ========================================================== */
6333#define EMAC_TEST_SCPQ_Pos (0UL)
6334#define EMAC_TEST_SCPQ_Msk (0x1UL)
6335#define EMAC_TEST_TESTPAUSE_Pos (1UL)
6336#define EMAC_TEST_TESTPAUSE_Msk (0x2UL)
6337#define EMAC_TEST_TESTBP_Pos (2UL)
6338#define EMAC_TEST_TESTBP_Msk (0x4UL)
6339/* ========================================================= MCFG ========================================================== */
6340#define EMAC_MCFG_SCANINC_Pos (0UL)
6341#define EMAC_MCFG_SCANINC_Msk (0x1UL)
6342#define EMAC_MCFG_SUPPPREAMBLE_Pos (1UL)
6343#define EMAC_MCFG_SUPPPREAMBLE_Msk (0x2UL)
6344#define EMAC_MCFG_CLOCKSEL_Pos (2UL)
6345#define EMAC_MCFG_CLOCKSEL_Msk (0x3cUL)
6346#define EMAC_MCFG_RESETMIIMGMT_Pos (15UL)
6347#define EMAC_MCFG_RESETMIIMGMT_Msk (0x8000UL)
6348/* ========================================================= MCMD ========================================================== */
6349#define EMAC_MCMD_READ_Pos (0UL)
6350#define EMAC_MCMD_READ_Msk (0x1UL)
6351#define EMAC_MCMD_SCAN_Pos (1UL)
6352#define EMAC_MCMD_SCAN_Msk (0x2UL)
6353/* ========================================================= MADR ========================================================== */
6354#define EMAC_MADR_REGADDR_Pos (0UL)
6355#define EMAC_MADR_REGADDR_Msk (0x1fUL)
6356#define EMAC_MADR_PHYADDR_Pos (8UL)
6357#define EMAC_MADR_PHYADDR_Msk (0x1f00UL)
6358/* ========================================================= MWTD ========================================================== */
6359#define EMAC_MWTD_WRITEDATA_Pos (0UL)
6360#define EMAC_MWTD_WRITEDATA_Msk (0xffffUL)
6361/* ========================================================= MRDD ========================================================== */
6362#define EMAC_MRDD_READDATA_Pos (0UL)
6363#define EMAC_MRDD_READDATA_Msk (0xffffUL)
6364/* ========================================================= MIND ========================================================== */
6365#define EMAC_MIND_BUSY_Pos (0UL)
6366#define EMAC_MIND_BUSY_Msk (0x1UL)
6367#define EMAC_MIND_SCANNING_Pos (1UL)
6368#define EMAC_MIND_SCANNING_Msk (0x2UL)
6369#define EMAC_MIND_NOTVALID_Pos (2UL)
6370#define EMAC_MIND_NOTVALID_Msk (0x4UL)
6371#define EMAC_MIND_MIILINKFAIL_Pos (3UL)
6372#define EMAC_MIND_MIILINKFAIL_Msk (0x8UL)
6373/* ========================================================== SA0 ========================================================== */
6374#define EMAC_SA0_SADDR2_Pos (0UL)
6375#define EMAC_SA0_SADDR2_Msk (0xffUL)
6376#define EMAC_SA0_SADDR1_Pos (8UL)
6377#define EMAC_SA0_SADDR1_Msk (0xff00UL)
6378/* ========================================================== SA1 ========================================================== */
6379#define EMAC_SA1_SADDR4_Pos (0UL)
6380#define EMAC_SA1_SADDR4_Msk (0xffUL)
6381#define EMAC_SA1_SADDR3_Pos (8UL)
6382#define EMAC_SA1_SADDR3_Msk (0xff00UL)
6383/* ========================================================== SA2 ========================================================== */
6384#define EMAC_SA2_SADDR6_Pos (0UL)
6385#define EMAC_SA2_SADDR6_Msk (0xffUL)
6386#define EMAC_SA2_SADDR5_Pos (8UL)
6387#define EMAC_SA2_SADDR5_Msk (0xff00UL)
6388/* ======================================================== COMMAND ======================================================== */
6389#define EMAC_COMMAND_RXENABLE_Pos (0UL)
6390#define EMAC_COMMAND_RXENABLE_Msk (0x1UL)
6391#define EMAC_COMMAND_TXENABLE_Pos (1UL)
6392#define EMAC_COMMAND_TXENABLE_Msk (0x2UL)
6393#define EMAC_COMMAND_REGRESET_Pos (3UL)
6394#define EMAC_COMMAND_REGRESET_Msk (0x8UL)
6395#define EMAC_COMMAND_TXRESET_Pos (4UL)
6396#define EMAC_COMMAND_TXRESET_Msk (0x10UL)
6397#define EMAC_COMMAND_RXRESET_Pos (5UL)
6398#define EMAC_COMMAND_RXRESET_Msk (0x20UL)
6399#define EMAC_COMMAND_PASSRUNTFRAME_Pos (6UL)
6400#define EMAC_COMMAND_PASSRUNTFRAME_Msk (0x40UL)
6401#define EMAC_COMMAND_PASSRXFILTER_Pos (7UL)
6402#define EMAC_COMMAND_PASSRXFILTER_Msk (0x80UL)
6403#define EMAC_COMMAND_TXFLOWCONTROL_Pos (8UL)
6404#define EMAC_COMMAND_TXFLOWCONTROL_Msk (0x100UL)
6405#define EMAC_COMMAND_RMII_Pos (9UL)
6406#define EMAC_COMMAND_RMII_Msk (0x200UL)
6407#define EMAC_COMMAND_FULLDUPLEX_Pos (10UL)
6408#define EMAC_COMMAND_FULLDUPLEX_Msk (0x400UL)
6409/* ======================================================== STATUS ========================================================= */
6410#define EMAC_STATUS_RXSTATUS_Pos (0UL)
6411#define EMAC_STATUS_RXSTATUS_Msk (0x1UL)
6412#define EMAC_STATUS_TXSTATUS_Pos (1UL)
6413#define EMAC_STATUS_TXSTATUS_Msk (0x2UL)
6414/* ===================================================== RXDESCRIPTOR ====================================================== */
6415#define EMAC_RXDESCRIPTOR_RXDESCRIPTOR_Pos (2UL)
6416#define EMAC_RXDESCRIPTOR_RXDESCRIPTOR_Msk (0xfffffffcUL)
6417/* ======================================================= RXSTATUS ======================================================== */
6418#define EMAC_RXSTATUS_RXSTATUS_Pos (3UL)
6419#define EMAC_RXSTATUS_RXSTATUS_Msk (0xfffffff8UL)
6420/* ================================================== RXDESCRIPTORNUMBER =================================================== */
6421#define EMAC_RXDESCRIPTORNUMBER_RXDESCRIPTORN_Pos (0UL)
6422#define EMAC_RXDESCRIPTORNUMBER_RXDESCRIPTORN_Msk (0xffffUL)
6423/* ==================================================== RXPRODUCEINDEX ===================================================== */
6424#define EMAC_RXPRODUCEINDEX_RXPRODUCEIX_Pos (0UL)
6425#define EMAC_RXPRODUCEINDEX_RXPRODUCEIX_Msk (0xffffUL)
6426/* ==================================================== RXCONSUMEINDEX ===================================================== */
6427#define EMAC_RXCONSUMEINDEX_RXCONSUMEIX_Pos (0UL)
6428#define EMAC_RXCONSUMEINDEX_RXCONSUMEIX_Msk (0xffffUL)
6429/* ===================================================== TXDESCRIPTOR ====================================================== */
6430#define EMAC_TXDESCRIPTOR_TXD_Pos (2UL)
6431#define EMAC_TXDESCRIPTOR_TXD_Msk (0xfffffffcUL)
6432/* ======================================================= TXSTATUS ======================================================== */
6433#define EMAC_TXSTATUS_TXSTAT_Pos (2UL)
6434#define EMAC_TXSTATUS_TXSTAT_Msk (0xfffffffcUL)
6435/* ================================================== TXDESCRIPTORNUMBER =================================================== */
6436#define EMAC_TXDESCRIPTORNUMBER_TXDN_Pos (0UL)
6437#define EMAC_TXDESCRIPTORNUMBER_TXDN_Msk (0xffffUL)
6438/* ==================================================== TXPRODUCEINDEX ===================================================== */
6439#define EMAC_TXPRODUCEINDEX_TXPI_Pos (0UL)
6440#define EMAC_TXPRODUCEINDEX_TXPI_Msk (0xffffUL)
6441/* ==================================================== TXCONSUMEINDEX ===================================================== */
6442#define EMAC_TXCONSUMEINDEX_TXCI_Pos (0UL)
6443#define EMAC_TXCONSUMEINDEX_TXCI_Msk (0xffffUL)
6444/* ========================================================= TSV0 ========================================================== */
6445#define EMAC_TSV0_CRCERR_Pos (0UL)
6446#define EMAC_TSV0_CRCERR_Msk (0x1UL)
6447#define EMAC_TSV0_LCE_Pos (1UL)
6448#define EMAC_TSV0_LCE_Msk (0x2UL)
6449#define EMAC_TSV0_LOR_Pos (2UL)
6450#define EMAC_TSV0_LOR_Msk (0x4UL)
6451#define EMAC_TSV0_DONE_Pos (3UL)
6452#define EMAC_TSV0_DONE_Msk (0x8UL)
6453#define EMAC_TSV0_MULTICAST_Pos (4UL)
6454#define EMAC_TSV0_MULTICAST_Msk (0x10UL)
6455#define EMAC_TSV0_BROADCAST_Pos (5UL)
6456#define EMAC_TSV0_BROADCAST_Msk (0x20UL)
6457#define EMAC_TSV0_PACKETDEFER_Pos (6UL)
6458#define EMAC_TSV0_PACKETDEFER_Msk (0x40UL)
6459#define EMAC_TSV0_EXDF_Pos (7UL)
6460#define EMAC_TSV0_EXDF_Msk (0x80UL)
6461#define EMAC_TSV0_EXCOL_Pos (8UL)
6462#define EMAC_TSV0_EXCOL_Msk (0x100UL)
6463#define EMAC_TSV0_LCOL_Pos (9UL)
6464#define EMAC_TSV0_LCOL_Msk (0x200UL)
6465#define EMAC_TSV0_GIANT_Pos (10UL)
6466#define EMAC_TSV0_GIANT_Msk (0x400UL)
6467#define EMAC_TSV0_UNDERRUN_Pos (11UL)
6468#define EMAC_TSV0_UNDERRUN_Msk (0x800UL)
6469#define EMAC_TSV0_TOTALBYTES_Pos (12UL)
6470#define EMAC_TSV0_TOTALBYTES_Msk (0xffff000UL)
6471#define EMAC_TSV0_CONTROLFRAME_Pos (28UL)
6472#define EMAC_TSV0_CONTROLFRAME_Msk (0x10000000UL)
6473#define EMAC_TSV0_PAUSE_Pos (29UL)
6474#define EMAC_TSV0_PAUSE_Msk (0x20000000UL)
6475#define EMAC_TSV0_BACKPRESSURE_Pos (30UL)
6476#define EMAC_TSV0_BACKPRESSURE_Msk (0x40000000UL)
6477#define EMAC_TSV0_VLAN_Pos (31UL)
6478#define EMAC_TSV0_VLAN_Msk (0x80000000UL)
6479/* ========================================================= TSV1 ========================================================== */
6480#define EMAC_TSV1_TBC_Pos (0UL)
6481#define EMAC_TSV1_TBC_Msk (0xffffUL)
6482#define EMAC_TSV1_TCC_Pos (16UL)
6483#define EMAC_TSV1_TCC_Msk (0xf0000UL)
6484/* ========================================================== RSV ========================================================== */
6485#define EMAC_RSV_RBC_Pos (0UL)
6486#define EMAC_RSV_RBC_Msk (0xffffUL)
6487#define EMAC_RSV_PPI_Pos (16UL)
6488#define EMAC_RSV_PPI_Msk (0x10000UL)
6489#define EMAC_RSV_RXDVSEEN_Pos (17UL)
6490#define EMAC_RSV_RXDVSEEN_Msk (0x20000UL)
6491#define EMAC_RSV_CESEEN_Pos (18UL)
6492#define EMAC_RSV_CESEEN_Msk (0x40000UL)
6493#define EMAC_RSV_RCV_Pos (19UL)
6494#define EMAC_RSV_RCV_Msk (0x80000UL)
6495#define EMAC_RSV_CRCERR_Pos (20UL)
6496#define EMAC_RSV_CRCERR_Msk (0x100000UL)
6497#define EMAC_RSV_LCERR_Pos (21UL)
6498#define EMAC_RSV_LCERR_Msk (0x200000UL)
6499#define EMAC_RSV_LOR_Pos (22UL)
6500#define EMAC_RSV_LOR_Msk (0x400000UL)
6501#define EMAC_RSV_ROK_Pos (23UL)
6502#define EMAC_RSV_ROK_Msk (0x800000UL)
6503#define EMAC_RSV_MULTICAST_Pos (24UL)
6504#define EMAC_RSV_MULTICAST_Msk (0x1000000UL)
6505#define EMAC_RSV_BROADCAST_Pos (25UL)
6506#define EMAC_RSV_BROADCAST_Msk (0x2000000UL)
6507#define EMAC_RSV_DRIBBLENIBBLE_Pos (26UL)
6508#define EMAC_RSV_DRIBBLENIBBLE_Msk (0x4000000UL)
6509#define EMAC_RSV_CONTROLFRAME_Pos (27UL)
6510#define EMAC_RSV_CONTROLFRAME_Msk (0x8000000UL)
6511#define EMAC_RSV_PAUSE_Pos (28UL)
6512#define EMAC_RSV_PAUSE_Msk (0x10000000UL)
6513#define EMAC_RSV_UO_Pos (29UL)
6514#define EMAC_RSV_UO_Msk (0x20000000UL)
6515#define EMAC_RSV_VLAN_Pos (30UL)
6516#define EMAC_RSV_VLAN_Msk (0x40000000UL)
6517/* ================================================== FLOWCONTROLCOUNTER =================================================== */
6518#define EMAC_FLOWCONTROLCOUNTER_MC_Pos (0UL)
6519#define EMAC_FLOWCONTROLCOUNTER_MC_Msk (0xffffUL)
6520#define EMAC_FLOWCONTROLCOUNTER_PT_Pos (16UL)
6521#define EMAC_FLOWCONTROLCOUNTER_PT_Msk (0xffff0000UL)
6522/* =================================================== FLOWCONTROLSTATUS =================================================== */
6523#define EMAC_FLOWCONTROLSTATUS_MCC_Pos (0UL)
6524#define EMAC_FLOWCONTROLSTATUS_MCC_Msk (0xffffUL)
6525/* ===================================================== RXFILTERCTRL ====================================================== */
6526#define EMAC_RXFILTERCTRL_AUE_Pos (0UL)
6527#define EMAC_RXFILTERCTRL_AUE_Msk (0x1UL)
6528#define EMAC_RXFILTERCTRL_ABE_Pos (1UL)
6529#define EMAC_RXFILTERCTRL_ABE_Msk (0x2UL)
6530#define EMAC_RXFILTERCTRL_AME_Pos (2UL)
6531#define EMAC_RXFILTERCTRL_AME_Msk (0x4UL)
6532#define EMAC_RXFILTERCTRL_AUHE_Pos (3UL)
6533#define EMAC_RXFILTERCTRL_AUHE_Msk (0x8UL)
6534#define EMAC_RXFILTERCTRL_AMHE_Pos (4UL)
6535#define EMAC_RXFILTERCTRL_AMHE_Msk (0x10UL)
6536#define EMAC_RXFILTERCTRL_APE_Pos (5UL)
6537#define EMAC_RXFILTERCTRL_APE_Msk (0x20UL)
6538#define EMAC_RXFILTERCTRL_MPEW_Pos (12UL)
6539#define EMAC_RXFILTERCTRL_MPEW_Msk (0x1000UL)
6540#define EMAC_RXFILTERCTRL_RFEW_Pos (13UL)
6541#define EMAC_RXFILTERCTRL_RFEW_Msk (0x2000UL)
6542/* =================================================== RXFILTERWOLSTATUS =================================================== */
6543#define EMAC_RXFILTERWOLSTATUS_AUW_Pos (0UL)
6544#define EMAC_RXFILTERWOLSTATUS_AUW_Msk (0x1UL)
6545#define EMAC_RXFILTERWOLSTATUS_ABW_Pos (1UL)
6546#define EMAC_RXFILTERWOLSTATUS_ABW_Msk (0x2UL)
6547#define EMAC_RXFILTERWOLSTATUS_AMW_Pos (2UL)
6548#define EMAC_RXFILTERWOLSTATUS_AMW_Msk (0x4UL)
6549#define EMAC_RXFILTERWOLSTATUS_AUHW_Pos (3UL)
6550#define EMAC_RXFILTERWOLSTATUS_AUHW_Msk (0x8UL)
6551#define EMAC_RXFILTERWOLSTATUS_AMHW_Pos (4UL)
6552#define EMAC_RXFILTERWOLSTATUS_AMHW_Msk (0x10UL)
6553#define EMAC_RXFILTERWOLSTATUS_APW_Pos (5UL)
6554#define EMAC_RXFILTERWOLSTATUS_APW_Msk (0x20UL)
6555#define EMAC_RXFILTERWOLSTATUS_RFW_Pos (7UL)
6556#define EMAC_RXFILTERWOLSTATUS_RFW_Msk (0x80UL)
6557#define EMAC_RXFILTERWOLSTATUS_MPW_Pos (8UL)
6558#define EMAC_RXFILTERWOLSTATUS_MPW_Msk (0x100UL)
6559/* =================================================== RXFILTERWOLCLEAR ==================================================== */
6560#define EMAC_RXFILTERWOLCLEAR_AUWCLR_Pos (0UL)
6561#define EMAC_RXFILTERWOLCLEAR_AUWCLR_Msk (0x1UL)
6562#define EMAC_RXFILTERWOLCLEAR_ABWCLR_Pos (1UL)
6563#define EMAC_RXFILTERWOLCLEAR_ABWCLR_Msk (0x2UL)
6564#define EMAC_RXFILTERWOLCLEAR_AMWCLR_Pos (2UL)
6565#define EMAC_RXFILTERWOLCLEAR_AMWCLR_Msk (0x4UL)
6566#define EMAC_RXFILTERWOLCLEAR_AUHWCLR_Pos (3UL)
6567#define EMAC_RXFILTERWOLCLEAR_AUHWCLR_Msk (0x8UL)
6568#define EMAC_RXFILTERWOLCLEAR_AMHWCLR_Pos (4UL)
6569#define EMAC_RXFILTERWOLCLEAR_AMHWCLR_Msk (0x10UL)
6570#define EMAC_RXFILTERWOLCLEAR_APWCLR_Pos (5UL)
6571#define EMAC_RXFILTERWOLCLEAR_APWCLR_Msk (0x20UL)
6572#define EMAC_RXFILTERWOLCLEAR_RFWCLR_Pos (7UL)
6573#define EMAC_RXFILTERWOLCLEAR_RFWCLR_Msk (0x80UL)
6574#define EMAC_RXFILTERWOLCLEAR_MPWCLR_Pos (8UL)
6575#define EMAC_RXFILTERWOLCLEAR_MPWCLR_Msk (0x100UL)
6576/* ====================================================== HASHFILTERL ====================================================== */
6577#define EMAC_HASHFILTERL_HFL_Pos (0UL)
6578#define EMAC_HASHFILTERL_HFL_Msk (0xffffffffUL)
6579/* ====================================================== HASHFILTERH ====================================================== */
6580#define EMAC_HASHFILTERH_HFH_Pos (0UL)
6581#define EMAC_HASHFILTERH_HFH_Msk (0xffffffffUL)
6582/* ======================================================= INTSTATUS ======================================================= */
6583#define EMAC_INTSTATUS_RXOVERRUNINT_Pos (0UL)
6584#define EMAC_INTSTATUS_RXOVERRUNINT_Msk (0x1UL)
6585#define EMAC_INTSTATUS_RXERRORINT_Pos (1UL)
6586#define EMAC_INTSTATUS_RXERRORINT_Msk (0x2UL)
6587#define EMAC_INTSTATUS_RXFINISHEDINT_Pos (2UL)
6588#define EMAC_INTSTATUS_RXFINISHEDINT_Msk (0x4UL)
6589#define EMAC_INTSTATUS_RXDONEINT_Pos (3UL)
6590#define EMAC_INTSTATUS_RXDONEINT_Msk (0x8UL)
6591#define EMAC_INTSTATUS_TXUNDERRUNINT_Pos (4UL)
6592#define EMAC_INTSTATUS_TXUNDERRUNINT_Msk (0x10UL)
6593#define EMAC_INTSTATUS_TXERRORINT_Pos (5UL)
6594#define EMAC_INTSTATUS_TXERRORINT_Msk (0x20UL)
6595#define EMAC_INTSTATUS_TXFINISHEDINT_Pos (6UL)
6596#define EMAC_INTSTATUS_TXFINISHEDINT_Msk (0x40UL)
6597#define EMAC_INTSTATUS_TXDONEINT_Pos (7UL)
6598#define EMAC_INTSTATUS_TXDONEINT_Msk (0x80UL)
6599#define EMAC_INTSTATUS_SOFTINT_Pos (12UL)
6600#define EMAC_INTSTATUS_SOFTINT_Msk (0x1000UL)
6601#define EMAC_INTSTATUS_WAKEUPINT_Pos (13UL)
6602#define EMAC_INTSTATUS_WAKEUPINT_Msk (0x2000UL)
6603/* ======================================================= INTENABLE ======================================================= */
6604#define EMAC_INTENABLE_RXOVERRUNINTEN_Pos (0UL)
6605#define EMAC_INTENABLE_RXOVERRUNINTEN_Msk (0x1UL)
6606#define EMAC_INTENABLE_RXERRORINTEN_Pos (1UL)
6607#define EMAC_INTENABLE_RXERRORINTEN_Msk (0x2UL)
6608#define EMAC_INTENABLE_RXFINISHEDINTEN_Pos (2UL)
6609#define EMAC_INTENABLE_RXFINISHEDINTEN_Msk (0x4UL)
6610#define EMAC_INTENABLE_RXDONEINTEN_Pos (3UL)
6611#define EMAC_INTENABLE_RXDONEINTEN_Msk (0x8UL)
6612#define EMAC_INTENABLE_TXUNDERRUNINTEN_Pos (4UL)
6613#define EMAC_INTENABLE_TXUNDERRUNINTEN_Msk (0x10UL)
6614#define EMAC_INTENABLE_TXERRORINTEN_Pos (5UL)
6615#define EMAC_INTENABLE_TXERRORINTEN_Msk (0x20UL)
6616#define EMAC_INTENABLE_TXFINISHEDINTEN_Pos (6UL)
6617#define EMAC_INTENABLE_TXFINISHEDINTEN_Msk (0x40UL)
6618#define EMAC_INTENABLE_TXDONEINTEN_Pos (7UL)
6619#define EMAC_INTENABLE_TXDONEINTEN_Msk (0x80UL)
6620#define EMAC_INTENABLE_SOFTINTEN_Pos (12UL)
6621#define EMAC_INTENABLE_SOFTINTEN_Msk (0x1000UL)
6622#define EMAC_INTENABLE_WAKEUPINTEN_Pos (13UL)
6623#define EMAC_INTENABLE_WAKEUPINTEN_Msk (0x2000UL)
6624/* ======================================================= INTCLEAR ======================================================== */
6625#define EMAC_INTCLEAR_RXOVERRUNINTCLR_Pos (0UL)
6626#define EMAC_INTCLEAR_RXOVERRUNINTCLR_Msk (0x1UL)
6627#define EMAC_INTCLEAR_RXERRORINTCLR_Pos (1UL)
6628#define EMAC_INTCLEAR_RXERRORINTCLR_Msk (0x2UL)
6629#define EMAC_INTCLEAR_RXFINISHEDINTCLR_Pos (2UL)
6630#define EMAC_INTCLEAR_RXFINISHEDINTCLR_Msk (0x4UL)
6631#define EMAC_INTCLEAR_RXDONEINTCLR_Pos (3UL)
6632#define EMAC_INTCLEAR_RXDONEINTCLR_Msk (0x8UL)
6633#define EMAC_INTCLEAR_TXUNDERRUNINTCLR_Pos (4UL)
6634#define EMAC_INTCLEAR_TXUNDERRUNINTCLR_Msk (0x10UL)
6635#define EMAC_INTCLEAR_TXERRORINTCLR_Pos (5UL)
6636#define EMAC_INTCLEAR_TXERRORINTCLR_Msk (0x20UL)
6637#define EMAC_INTCLEAR_TXFINISHEDINTCLR_Pos (6UL)
6638#define EMAC_INTCLEAR_TXFINISHEDINTCLR_Msk (0x40UL)
6639#define EMAC_INTCLEAR_TXDONEINTCLR_Pos (7UL)
6640#define EMAC_INTCLEAR_TXDONEINTCLR_Msk (0x80UL)
6641#define EMAC_INTCLEAR_SOFTINTCLR_Pos (12UL)
6642#define EMAC_INTCLEAR_SOFTINTCLR_Msk (0x1000UL)
6643#define EMAC_INTCLEAR_WAKEUPINTCLR_Pos (13UL)
6644#define EMAC_INTCLEAR_WAKEUPINTCLR_Msk (0x2000UL)
6645/* ======================================================== INTSET ========================================================= */
6646#define EMAC_INTSET_RXOVERRUNINTSET_Pos (0UL)
6647#define EMAC_INTSET_RXOVERRUNINTSET_Msk (0x1UL)
6648#define EMAC_INTSET_RXERRORINTSET_Pos (1UL)
6649#define EMAC_INTSET_RXERRORINTSET_Msk (0x2UL)
6650#define EMAC_INTSET_RXFINISHEDINTSET_Pos (2UL)
6651#define EMAC_INTSET_RXFINISHEDINTSET_Msk (0x4UL)
6652#define EMAC_INTSET_RXDONEINTSET_Pos (3UL)
6653#define EMAC_INTSET_RXDONEINTSET_Msk (0x8UL)
6654#define EMAC_INTSET_TXUNDERRUNINTSET_Pos (4UL)
6655#define EMAC_INTSET_TXUNDERRUNINTSET_Msk (0x10UL)
6656#define EMAC_INTSET_TXERRORINTSET_Pos (5UL)
6657#define EMAC_INTSET_TXERRORINTSET_Msk (0x20UL)
6658#define EMAC_INTSET_TXFINISHEDINTSET_Pos (6UL)
6659#define EMAC_INTSET_TXFINISHEDINTSET_Msk (0x40UL)
6660#define EMAC_INTSET_TXDONEINTSET_Pos (7UL)
6661#define EMAC_INTSET_TXDONEINTSET_Msk (0x80UL)
6662#define EMAC_INTSET_SOFTINTSET_Pos (12UL)
6663#define EMAC_INTSET_SOFTINTSET_Msk (0x1000UL)
6664#define EMAC_INTSET_WAKEUPINTSET_Pos (13UL)
6665#define EMAC_INTSET_WAKEUPINTSET_Msk (0x2000UL)
6666/* ======================================================= POWERDOWN ======================================================= */
6667#define EMAC_POWERDOWN_PD_Pos (31UL)
6668#define EMAC_POWERDOWN_PD_Msk (0x80000000UL)
6671/* =========================================================================================================================== */
6672/* ================ LPC_GPDMA ================ */
6673/* =========================================================================================================================== */
6674
6675/* ======================================================== INTSTAT ======================================================== */
6676#define GPDMA_INTSTAT_INTSTAT0_Pos (0UL)
6677#define GPDMA_INTSTAT_INTSTAT0_Msk (0x1UL)
6678#define GPDMA_INTSTAT_INTSTAT1_Pos (1UL)
6679#define GPDMA_INTSTAT_INTSTAT1_Msk (0x2UL)
6680#define GPDMA_INTSTAT_INTSTAT2_Pos (2UL)
6681#define GPDMA_INTSTAT_INTSTAT2_Msk (0x4UL)
6682#define GPDMA_INTSTAT_INTSTAT3_Pos (3UL)
6683#define GPDMA_INTSTAT_INTSTAT3_Msk (0x8UL)
6684#define GPDMA_INTSTAT_INTSTAT4_Pos (4UL)
6685#define GPDMA_INTSTAT_INTSTAT4_Msk (0x10UL)
6686#define GPDMA_INTSTAT_INTSTAT5_Pos (5UL)
6687#define GPDMA_INTSTAT_INTSTAT5_Msk (0x20UL)
6688#define GPDMA_INTSTAT_INTSTAT6_Pos (6UL)
6689#define GPDMA_INTSTAT_INTSTAT6_Msk (0x40UL)
6690#define GPDMA_INTSTAT_INTSTAT7_Pos (7UL)
6691#define GPDMA_INTSTAT_INTSTAT7_Msk (0x80UL)
6692/* ======================================================= INTTCSTAT ======================================================= */
6693#define GPDMA_INTTCSTAT_INTTCSTAT0_Pos (0UL)
6694#define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x1UL)
6695#define GPDMA_INTTCSTAT_INTTCSTAT1_Pos (1UL)
6696#define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x2UL)
6697#define GPDMA_INTTCSTAT_INTTCSTAT2_Pos (2UL)
6698#define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x4UL)
6699#define GPDMA_INTTCSTAT_INTTCSTAT3_Pos (3UL)
6700#define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x8UL)
6701#define GPDMA_INTTCSTAT_INTTCSTAT4_Pos (4UL)
6702#define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x10UL)
6703#define GPDMA_INTTCSTAT_INTTCSTAT5_Pos (5UL)
6704#define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x20UL)
6705#define GPDMA_INTTCSTAT_INTTCSTAT6_Pos (6UL)
6706#define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x40UL)
6707#define GPDMA_INTTCSTAT_INTTCSTAT7_Pos (7UL)
6708#define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x80UL)
6709/* ====================================================== INTTCCLEAR ======================================================= */
6710#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos (0UL)
6711#define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x1UL)
6712#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos (1UL)
6713#define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x2UL)
6714#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos (2UL)
6715#define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x4UL)
6716#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos (3UL)
6717#define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x8UL)
6718#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos (4UL)
6719#define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x10UL)
6720#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos (5UL)
6721#define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x20UL)
6722#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos (6UL)
6723#define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x40UL)
6724#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos (7UL)
6725#define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x80UL)
6726/* ====================================================== INTERRSTAT ======================================================= */
6727#define GPDMA_INTERRSTAT_INTERRSTAT0_Pos (0UL)
6728#define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x1UL)
6729#define GPDMA_INTERRSTAT_INTERRSTAT1_Pos (1UL)
6730#define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x2UL)
6731#define GPDMA_INTERRSTAT_INTERRSTAT2_Pos (2UL)
6732#define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x4UL)
6733#define GPDMA_INTERRSTAT_INTERRSTAT3_Pos (3UL)
6734#define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x8UL)
6735#define GPDMA_INTERRSTAT_INTERRSTAT4_Pos (4UL)
6736#define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x10UL)
6737#define GPDMA_INTERRSTAT_INTERRSTAT5_Pos (5UL)
6738#define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x20UL)
6739#define GPDMA_INTERRSTAT_INTERRSTAT6_Pos (6UL)
6740#define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x40UL)
6741#define GPDMA_INTERRSTAT_INTERRSTAT7_Pos (7UL)
6742#define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x80UL)
6743/* ======================================================= INTERRCLR ======================================================= */
6744#define GPDMA_INTERRCLR_INTERRCLR0_Pos (0UL)
6745#define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x1UL)
6746#define GPDMA_INTERRCLR_INTERRCLR1_Pos (1UL)
6747#define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x2UL)
6748#define GPDMA_INTERRCLR_INTERRCLR2_Pos (2UL)
6749#define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x4UL)
6750#define GPDMA_INTERRCLR_INTERRCLR3_Pos (3UL)
6751#define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x8UL)
6752#define GPDMA_INTERRCLR_INTERRCLR4_Pos (4UL)
6753#define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x10UL)
6754#define GPDMA_INTERRCLR_INTERRCLR5_Pos (5UL)
6755#define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x20UL)
6756#define GPDMA_INTERRCLR_INTERRCLR6_Pos (6UL)
6757#define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x40UL)
6758#define GPDMA_INTERRCLR_INTERRCLR7_Pos (7UL)
6759#define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x80UL)
6760/* ===================================================== RAWINTTCSTAT ====================================================== */
6761#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos (0UL)
6762#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x1UL)
6763#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos (1UL)
6764#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x2UL)
6765#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos (2UL)
6766#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x4UL)
6767#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos (3UL)
6768#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x8UL)
6769#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos (4UL)
6770#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x10UL)
6771#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos (5UL)
6772#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x20UL)
6773#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos (6UL)
6774#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x40UL)
6775#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos (7UL)
6776#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x80UL)
6777/* ===================================================== RAWINTERRSTAT ===================================================== */
6778#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos (0UL)
6779#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x1UL)
6780#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos (1UL)
6781#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x2UL)
6782#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos (2UL)
6783#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x4UL)
6784#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos (3UL)
6785#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x8UL)
6786#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos (4UL)
6787#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x10UL)
6788#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos (5UL)
6789#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x20UL)
6790#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos (6UL)
6791#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x40UL)
6792#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos (7UL)
6793#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x80UL)
6794/* ======================================================= ENBLDCHNS ======================================================= */
6795#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos (0UL)
6796#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x1UL)
6797#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos (1UL)
6798#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x2UL)
6799#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos (2UL)
6800#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x4UL)
6801#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos (3UL)
6802#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x8UL)
6803#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos (4UL)
6804#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x10UL)
6805#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos (5UL)
6806#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x20UL)
6807#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos (6UL)
6808#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x40UL)
6809#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos (7UL)
6810#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x80UL)
6811/* ======================================================= SOFTBREQ ======================================================== */
6812#define GPDMA_SOFTBREQ_SOFTBREQ0_Pos (0UL)
6813#define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x1UL)
6814#define GPDMA_SOFTBREQ_SOFTBREQ1_Pos (1UL)
6815#define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x2UL)
6816#define GPDMA_SOFTBREQ_SOFTBREQ2_Pos (2UL)
6817#define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x4UL)
6818#define GPDMA_SOFTBREQ_SOFTBREQ3_Pos (3UL)
6819#define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x8UL)
6820#define GPDMA_SOFTBREQ_SOFTBREQ4_Pos (4UL)
6821#define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x10UL)
6822#define GPDMA_SOFTBREQ_SOFTBREQ5_Pos (5UL)
6823#define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x20UL)
6824#define GPDMA_SOFTBREQ_SOFTBREQ6_Pos (6UL)
6825#define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x40UL)
6826#define GPDMA_SOFTBREQ_SOFTBREQ7_Pos (7UL)
6827#define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x80UL)
6828#define GPDMA_SOFTBREQ_SOFTBREQ8_Pos (8UL)
6829#define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x100UL)
6830#define GPDMA_SOFTBREQ_SOFTBREQ9_Pos (9UL)
6831#define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x200UL)
6832#define GPDMA_SOFTBREQ_SOFTBREQ10_Pos (10UL)
6833#define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x400UL)
6834#define GPDMA_SOFTBREQ_SOFTBREQ11_Pos (11UL)
6835#define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x800UL)
6836#define GPDMA_SOFTBREQ_SOFTBREQ12_Pos (12UL)
6837#define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x1000UL)
6838#define GPDMA_SOFTBREQ_SOFTBREQ13_Pos (13UL)
6839#define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x2000UL)
6840#define GPDMA_SOFTBREQ_SOFTBREQ14_Pos (14UL)
6841#define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x4000UL)
6842#define GPDMA_SOFTBREQ_SOFTBREQ15_Pos (15UL)
6843#define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x8000UL)
6844/* ======================================================= SOFTSREQ ======================================================== */
6845#define GPDMA_SOFTSREQ_SOFTSREQ0_Pos (0UL)
6846#define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x1UL)
6847#define GPDMA_SOFTSREQ_SOFTSREQ1_Pos (1UL)
6848#define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x2UL)
6849#define GPDMA_SOFTSREQ_SOFTSREQ2_Pos (2UL)
6850#define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x4UL)
6851#define GPDMA_SOFTSREQ_SOFTSREQ3_Pos (3UL)
6852#define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x8UL)
6853#define GPDMA_SOFTSREQ_SOFTSREQ4_Pos (4UL)
6854#define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x10UL)
6855#define GPDMA_SOFTSREQ_SOFTSREQ5_Pos (5UL)
6856#define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x20UL)
6857#define GPDMA_SOFTSREQ_SOFTSREQ6_Pos (6UL)
6858#define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x40UL)
6859#define GPDMA_SOFTSREQ_SOFTSREQ7_Pos (7UL)
6860#define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x80UL)
6861#define GPDMA_SOFTSREQ_SOFTSREQ8_Pos (8UL)
6862#define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x100UL)
6863#define GPDMA_SOFTSREQ_SOFTSREQ9_Pos (9UL)
6864#define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x200UL)
6865#define GPDMA_SOFTSREQ_SOFTSREQ10_Pos (10UL)
6866#define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x400UL)
6867#define GPDMA_SOFTSREQ_SOFTSREQ11_Pos (11UL)
6868#define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x800UL)
6869#define GPDMA_SOFTSREQ_SOFTSREQ12_Pos (12UL)
6870#define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x1000UL)
6871#define GPDMA_SOFTSREQ_SOFTSREQ13_Pos (13UL)
6872#define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x2000UL)
6873#define GPDMA_SOFTSREQ_SOFTSREQ14_Pos (14UL)
6874#define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x4000UL)
6875#define GPDMA_SOFTSREQ_SOFTSREQ15_Pos (15UL)
6876#define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x8000UL)
6877/* ======================================================= SOFTLBREQ ======================================================= */
6878#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos (0UL)
6879#define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x1UL)
6880#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos (1UL)
6881#define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x2UL)
6882#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos (2UL)
6883#define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x4UL)
6884#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos (3UL)
6885#define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x8UL)
6886#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos (4UL)
6887#define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x10UL)
6888#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos (5UL)
6889#define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x20UL)
6890#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos (6UL)
6891#define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x40UL)
6892#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos (7UL)
6893#define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x80UL)
6894#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos (8UL)
6895#define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x100UL)
6896#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos (9UL)
6897#define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x200UL)
6898#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos (10UL)
6899#define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x400UL)
6900#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos (11UL)
6901#define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x800UL)
6902#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos (12UL)
6903#define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x1000UL)
6904#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos (13UL)
6905#define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x2000UL)
6906#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos (14UL)
6907#define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x4000UL)
6908#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos (15UL)
6909#define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x8000UL)
6910/* ======================================================= SOFTLSREQ ======================================================= */
6911#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos (0UL)
6912#define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x1UL)
6913#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos (1UL)
6914#define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x2UL)
6915#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos (2UL)
6916#define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x4UL)
6917#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos (3UL)
6918#define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x8UL)
6919#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos (4UL)
6920#define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x10UL)
6921#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos (5UL)
6922#define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x20UL)
6923#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos (6UL)
6924#define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x40UL)
6925#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos (7UL)
6926#define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x80UL)
6927#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos (8UL)
6928#define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x100UL)
6929#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos (9UL)
6930#define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x200UL)
6931#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos (10UL)
6932#define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x400UL)
6933#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos (11UL)
6934#define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x800UL)
6935#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos (12UL)
6936#define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x1000UL)
6937#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos (13UL)
6938#define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x2000UL)
6939#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos (14UL)
6940#define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x4000UL)
6941#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos (15UL)
6942#define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x8000UL)
6943/* ======================================================== CONFIG ========================================================= */
6944#define GPDMA_CONFIG_E_Pos (0UL)
6945#define GPDMA_CONFIG_E_Msk (0x1UL)
6946#define GPDMA_CONFIG_M_Pos (1UL)
6947#define GPDMA_CONFIG_M_Msk (0x2UL)
6948/* ========================================================= SYNC ========================================================== */
6949#define GPDMA_SYNC_DMACSYNC0_Pos (0UL)
6950#define GPDMA_SYNC_DMACSYNC0_Msk (0x1UL)
6951#define GPDMA_SYNC_DMACSYNC1_Pos (1UL)
6952#define GPDMA_SYNC_DMACSYNC1_Msk (0x2UL)
6953#define GPDMA_SYNC_DMACSYNC2_Pos (2UL)
6954#define GPDMA_SYNC_DMACSYNC2_Msk (0x4UL)
6955#define GPDMA_SYNC_DMACSYNC3_Pos (3UL)
6956#define GPDMA_SYNC_DMACSYNC3_Msk (0x8UL)
6957#define GPDMA_SYNC_DMACSYNC4_Pos (4UL)
6958#define GPDMA_SYNC_DMACSYNC4_Msk (0x10UL)
6959#define GPDMA_SYNC_DMACSYNC5_Pos (5UL)
6960#define GPDMA_SYNC_DMACSYNC5_Msk (0x20UL)
6961#define GPDMA_SYNC_DMACSYNC6_Pos (6UL)
6962#define GPDMA_SYNC_DMACSYNC6_Msk (0x40UL)
6963#define GPDMA_SYNC_DMACSYNC7_Pos (7UL)
6964#define GPDMA_SYNC_DMACSYNC7_Msk (0x80UL)
6965#define GPDMA_SYNC_DMACSYNC8_Pos (8UL)
6966#define GPDMA_SYNC_DMACSYNC8_Msk (0x100UL)
6967#define GPDMA_SYNC_DMACSYNC9_Pos (9UL)
6968#define GPDMA_SYNC_DMACSYNC9_Msk (0x200UL)
6969#define GPDMA_SYNC_DMACSYNC10_Pos (10UL)
6970#define GPDMA_SYNC_DMACSYNC10_Msk (0x400UL)
6971#define GPDMA_SYNC_DMACSYNC11_Pos (11UL)
6972#define GPDMA_SYNC_DMACSYNC11_Msk (0x800UL)
6973#define GPDMA_SYNC_DMACSYNC12_Pos (12UL)
6974#define GPDMA_SYNC_DMACSYNC12_Msk (0x1000UL)
6975#define GPDMA_SYNC_DMACSYNC13_Pos (13UL)
6976#define GPDMA_SYNC_DMACSYNC13_Msk (0x2000UL)
6977#define GPDMA_SYNC_DMACSYNC14_Pos (14UL)
6978#define GPDMA_SYNC_DMACSYNC14_Msk (0x4000UL)
6979#define GPDMA_SYNC_DMACSYNC15_Pos (15UL)
6980#define GPDMA_SYNC_DMACSYNC15_Msk (0x8000UL)
6981/* ======================================================= SRCADDR0 ======================================================== */
6982#define GPDMA_SRCADDR0_SRCADDR_Pos (0UL)
6983#define GPDMA_SRCADDR0_SRCADDR_Msk (0xffffffffUL)
6984/* ======================================================= SRCADDR1 ======================================================== */
6985#define GPDMA_SRCADDR1_SRCADDR_Pos (0UL)
6986#define GPDMA_SRCADDR1_SRCADDR_Msk (0xffffffffUL)
6987/* ======================================================= SRCADDR2 ======================================================== */
6988#define GPDMA_SRCADDR2_SRCADDR_Pos (0UL)
6989#define GPDMA_SRCADDR2_SRCADDR_Msk (0xffffffffUL)
6990/* ======================================================= SRCADDR3 ======================================================== */
6991#define GPDMA_SRCADDR3_SRCADDR_Pos (0UL)
6992#define GPDMA_SRCADDR3_SRCADDR_Msk (0xffffffffUL)
6993/* ======================================================= SRCADDR4 ======================================================== */
6994#define GPDMA_SRCADDR4_SRCADDR_Pos (0UL)
6995#define GPDMA_SRCADDR4_SRCADDR_Msk (0xffffffffUL)
6996/* ======================================================= SRCADDR5 ======================================================== */
6997#define GPDMA_SRCADDR5_SRCADDR_Pos (0UL)
6998#define GPDMA_SRCADDR5_SRCADDR_Msk (0xffffffffUL)
6999/* ======================================================= SRCADDR6 ======================================================== */
7000#define GPDMA_SRCADDR6_SRCADDR_Pos (0UL)
7001#define GPDMA_SRCADDR6_SRCADDR_Msk (0xffffffffUL)
7002/* ======================================================= SRCADDR7 ======================================================== */
7003#define GPDMA_SRCADDR7_SRCADDR_Pos (0UL)
7004#define GPDMA_SRCADDR7_SRCADDR_Msk (0xffffffffUL)
7005/* ======================================================= DESTADDR0 ======================================================= */
7006#define GPDMA_DESTADDR0_DESTADDR_Pos (0UL)
7007#define GPDMA_DESTADDR0_DESTADDR_Msk (0xffffffffUL)
7008/* ======================================================= DESTADDR1 ======================================================= */
7009#define GPDMA_DESTADDR1_DESTADDR_Pos (0UL)
7010#define GPDMA_DESTADDR1_DESTADDR_Msk (0xffffffffUL)
7011/* ======================================================= DESTADDR2 ======================================================= */
7012#define GPDMA_DESTADDR2_DESTADDR_Pos (0UL)
7013#define GPDMA_DESTADDR2_DESTADDR_Msk (0xffffffffUL)
7014/* ======================================================= DESTADDR3 ======================================================= */
7015#define GPDMA_DESTADDR3_DESTADDR_Pos (0UL)
7016#define GPDMA_DESTADDR3_DESTADDR_Msk (0xffffffffUL)
7017/* ======================================================= DESTADDR4 ======================================================= */
7018#define GPDMA_DESTADDR4_DESTADDR_Pos (0UL)
7019#define GPDMA_DESTADDR4_DESTADDR_Msk (0xffffffffUL)
7020/* ======================================================= DESTADDR5 ======================================================= */
7021#define GPDMA_DESTADDR5_DESTADDR_Pos (0UL)
7022#define GPDMA_DESTADDR5_DESTADDR_Msk (0xffffffffUL)
7023/* ======================================================= DESTADDR6 ======================================================= */
7024#define GPDMA_DESTADDR6_DESTADDR_Pos (0UL)
7025#define GPDMA_DESTADDR6_DESTADDR_Msk (0xffffffffUL)
7026/* ======================================================= DESTADDR7 ======================================================= */
7027#define GPDMA_DESTADDR7_DESTADDR_Pos (0UL)
7028#define GPDMA_DESTADDR7_DESTADDR_Msk (0xffffffffUL)
7029/* ========================================================= LLI0 ========================================================== */
7030#define GPDMA_LLI0_LLI_Pos (2UL)
7031#define GPDMA_LLI0_LLI_Msk (0xfffffffcUL)
7032/* ========================================================= LLI1 ========================================================== */
7033#define GPDMA_LLI1_LLI_Pos (2UL)
7034#define GPDMA_LLI1_LLI_Msk (0xfffffffcUL)
7035/* ========================================================= LLI2 ========================================================== */
7036#define GPDMA_LLI2_LLI_Pos (2UL)
7037#define GPDMA_LLI2_LLI_Msk (0xfffffffcUL)
7038/* ========================================================= LLI3 ========================================================== */
7039#define GPDMA_LLI3_LLI_Pos (2UL)
7040#define GPDMA_LLI3_LLI_Msk (0xfffffffcUL)
7041/* ========================================================= LLI4 ========================================================== */
7042#define GPDMA_LLI4_LLI_Pos (2UL)
7043#define GPDMA_LLI4_LLI_Msk (0xfffffffcUL)
7044/* ========================================================= LLI5 ========================================================== */
7045#define GPDMA_LLI5_LLI_Pos (2UL)
7046#define GPDMA_LLI5_LLI_Msk (0xfffffffcUL)
7047/* ========================================================= LLI6 ========================================================== */
7048#define GPDMA_LLI6_LLI_Pos (2UL)
7049#define GPDMA_LLI6_LLI_Msk (0xfffffffcUL)
7050/* ========================================================= LLI7 ========================================================== */
7051#define GPDMA_LLI7_LLI_Pos (2UL)
7052#define GPDMA_LLI7_LLI_Msk (0xfffffffcUL)
7053/* ======================================================= CONTROL0 ======================================================== */
7054#define GPDMA_CONTROL0_TRANSFERSIZE_Pos (0UL)
7055#define GPDMA_CONTROL0_TRANSFERSIZE_Msk (0xfffUL)
7056#define GPDMA_CONTROL0_SBSIZE_Pos (12UL)
7057#define GPDMA_CONTROL0_SBSIZE_Msk (0x7000UL)
7058#define GPDMA_CONTROL0_DBSIZE_Pos (15UL)
7059#define GPDMA_CONTROL0_DBSIZE_Msk (0x38000UL)
7060#define GPDMA_CONTROL0_SWIDTH_Pos (18UL)
7061#define GPDMA_CONTROL0_SWIDTH_Msk (0x1c0000UL)
7062#define GPDMA_CONTROL0_DWIDTH_Pos (21UL)
7063#define GPDMA_CONTROL0_DWIDTH_Msk (0xe00000UL)
7064#define GPDMA_CONTROL0_SI_Pos (26UL)
7065#define GPDMA_CONTROL0_SI_Msk (0x4000000UL)
7066#define GPDMA_CONTROL0_DI_Pos (27UL)
7067#define GPDMA_CONTROL0_DI_Msk (0x8000000UL)
7068#define GPDMA_CONTROL0_PROT1_Pos (28UL)
7069#define GPDMA_CONTROL0_PROT1_Msk (0x10000000UL)
7070#define GPDMA_CONTROL0_PROT2_Pos (29UL)
7071#define GPDMA_CONTROL0_PROT2_Msk (0x20000000UL)
7072#define GPDMA_CONTROL0_PROT3_Pos (30UL)
7073#define GPDMA_CONTROL0_PROT3_Msk (0x40000000UL)
7074#define GPDMA_CONTROL0_I_Pos (31UL)
7075#define GPDMA_CONTROL0_I_Msk (0x80000000UL)
7076/* ======================================================= CONTROL1 ======================================================== */
7077#define GPDMA_CONTROL1_TRANSFERSIZE_Pos (0UL)
7078#define GPDMA_CONTROL1_TRANSFERSIZE_Msk (0xfffUL)
7079#define GPDMA_CONTROL1_SBSIZE_Pos (12UL)
7080#define GPDMA_CONTROL1_SBSIZE_Msk (0x7000UL)
7081#define GPDMA_CONTROL1_DBSIZE_Pos (15UL)
7082#define GPDMA_CONTROL1_DBSIZE_Msk (0x38000UL)
7083#define GPDMA_CONTROL1_SWIDTH_Pos (18UL)
7084#define GPDMA_CONTROL1_SWIDTH_Msk (0x1c0000UL)
7085#define GPDMA_CONTROL1_DWIDTH_Pos (21UL)
7086#define GPDMA_CONTROL1_DWIDTH_Msk (0xe00000UL)
7087#define GPDMA_CONTROL1_SI_Pos (26UL)
7088#define GPDMA_CONTROL1_SI_Msk (0x4000000UL)
7089#define GPDMA_CONTROL1_DI_Pos (27UL)
7090#define GPDMA_CONTROL1_DI_Msk (0x8000000UL)
7091#define GPDMA_CONTROL1_PROT1_Pos (28UL)
7092#define GPDMA_CONTROL1_PROT1_Msk (0x10000000UL)
7093#define GPDMA_CONTROL1_PROT2_Pos (29UL)
7094#define GPDMA_CONTROL1_PROT2_Msk (0x20000000UL)
7095#define GPDMA_CONTROL1_PROT3_Pos (30UL)
7096#define GPDMA_CONTROL1_PROT3_Msk (0x40000000UL)
7097#define GPDMA_CONTROL1_I_Pos (31UL)
7098#define GPDMA_CONTROL1_I_Msk (0x80000000UL)
7099/* ======================================================= CONTROL2 ======================================================== */
7100#define GPDMA_CONTROL2_TRANSFERSIZE_Pos (0UL)
7101#define GPDMA_CONTROL2_TRANSFERSIZE_Msk (0xfffUL)
7102#define GPDMA_CONTROL2_SBSIZE_Pos (12UL)
7103#define GPDMA_CONTROL2_SBSIZE_Msk (0x7000UL)
7104#define GPDMA_CONTROL2_DBSIZE_Pos (15UL)
7105#define GPDMA_CONTROL2_DBSIZE_Msk (0x38000UL)
7106#define GPDMA_CONTROL2_SWIDTH_Pos (18UL)
7107#define GPDMA_CONTROL2_SWIDTH_Msk (0x1c0000UL)
7108#define GPDMA_CONTROL2_DWIDTH_Pos (21UL)
7109#define GPDMA_CONTROL2_DWIDTH_Msk (0xe00000UL)
7110#define GPDMA_CONTROL2_SI_Pos (26UL)
7111#define GPDMA_CONTROL2_SI_Msk (0x4000000UL)
7112#define GPDMA_CONTROL2_DI_Pos (27UL)
7113#define GPDMA_CONTROL2_DI_Msk (0x8000000UL)
7114#define GPDMA_CONTROL2_PROT1_Pos (28UL)
7115#define GPDMA_CONTROL2_PROT1_Msk (0x10000000UL)
7116#define GPDMA_CONTROL2_PROT2_Pos (29UL)
7117#define GPDMA_CONTROL2_PROT2_Msk (0x20000000UL)
7118#define GPDMA_CONTROL2_PROT3_Pos (30UL)
7119#define GPDMA_CONTROL2_PROT3_Msk (0x40000000UL)
7120#define GPDMA_CONTROL2_I_Pos (31UL)
7121#define GPDMA_CONTROL2_I_Msk (0x80000000UL)
7122/* ======================================================= CONTROL3 ======================================================== */
7123#define GPDMA_CONTROL3_TRANSFERSIZE_Pos (0UL)
7124#define GPDMA_CONTROL3_TRANSFERSIZE_Msk (0xfffUL)
7125#define GPDMA_CONTROL3_SBSIZE_Pos (12UL)
7126#define GPDMA_CONTROL3_SBSIZE_Msk (0x7000UL)
7127#define GPDMA_CONTROL3_DBSIZE_Pos (15UL)
7128#define GPDMA_CONTROL3_DBSIZE_Msk (0x38000UL)
7129#define GPDMA_CONTROL3_SWIDTH_Pos (18UL)
7130#define GPDMA_CONTROL3_SWIDTH_Msk (0x1c0000UL)
7131#define GPDMA_CONTROL3_DWIDTH_Pos (21UL)
7132#define GPDMA_CONTROL3_DWIDTH_Msk (0xe00000UL)
7133#define GPDMA_CONTROL3_SI_Pos (26UL)
7134#define GPDMA_CONTROL3_SI_Msk (0x4000000UL)
7135#define GPDMA_CONTROL3_DI_Pos (27UL)
7136#define GPDMA_CONTROL3_DI_Msk (0x8000000UL)
7137#define GPDMA_CONTROL3_PROT1_Pos (28UL)
7138#define GPDMA_CONTROL3_PROT1_Msk (0x10000000UL)
7139#define GPDMA_CONTROL3_PROT2_Pos (29UL)
7140#define GPDMA_CONTROL3_PROT2_Msk (0x20000000UL)
7141#define GPDMA_CONTROL3_PROT3_Pos (30UL)
7142#define GPDMA_CONTROL3_PROT3_Msk (0x40000000UL)
7143#define GPDMA_CONTROL3_I_Pos (31UL)
7144#define GPDMA_CONTROL3_I_Msk (0x80000000UL)
7145/* ======================================================= CONTROL4 ======================================================== */
7146#define GPDMA_CONTROL4_TRANSFERSIZE_Pos (0UL)
7147#define GPDMA_CONTROL4_TRANSFERSIZE_Msk (0xfffUL)
7148#define GPDMA_CONTROL4_SBSIZE_Pos (12UL)
7149#define GPDMA_CONTROL4_SBSIZE_Msk (0x7000UL)
7150#define GPDMA_CONTROL4_DBSIZE_Pos (15UL)
7151#define GPDMA_CONTROL4_DBSIZE_Msk (0x38000UL)
7152#define GPDMA_CONTROL4_SWIDTH_Pos (18UL)
7153#define GPDMA_CONTROL4_SWIDTH_Msk (0x1c0000UL)
7154#define GPDMA_CONTROL4_DWIDTH_Pos (21UL)
7155#define GPDMA_CONTROL4_DWIDTH_Msk (0xe00000UL)
7156#define GPDMA_CONTROL4_SI_Pos (26UL)
7157#define GPDMA_CONTROL4_SI_Msk (0x4000000UL)
7158#define GPDMA_CONTROL4_DI_Pos (27UL)
7159#define GPDMA_CONTROL4_DI_Msk (0x8000000UL)
7160#define GPDMA_CONTROL4_PROT1_Pos (28UL)
7161#define GPDMA_CONTROL4_PROT1_Msk (0x10000000UL)
7162#define GPDMA_CONTROL4_PROT2_Pos (29UL)
7163#define GPDMA_CONTROL4_PROT2_Msk (0x20000000UL)
7164#define GPDMA_CONTROL4_PROT3_Pos (30UL)
7165#define GPDMA_CONTROL4_PROT3_Msk (0x40000000UL)
7166#define GPDMA_CONTROL4_I_Pos (31UL)
7167#define GPDMA_CONTROL4_I_Msk (0x80000000UL)
7168/* ======================================================= CONTROL5 ======================================================== */
7169#define GPDMA_CONTROL5_TRANSFERSIZE_Pos (0UL)
7170#define GPDMA_CONTROL5_TRANSFERSIZE_Msk (0xfffUL)
7171#define GPDMA_CONTROL5_SBSIZE_Pos (12UL)
7172#define GPDMA_CONTROL5_SBSIZE_Msk (0x7000UL)
7173#define GPDMA_CONTROL5_DBSIZE_Pos (15UL)
7174#define GPDMA_CONTROL5_DBSIZE_Msk (0x38000UL)
7175#define GPDMA_CONTROL5_SWIDTH_Pos (18UL)
7176#define GPDMA_CONTROL5_SWIDTH_Msk (0x1c0000UL)
7177#define GPDMA_CONTROL5_DWIDTH_Pos (21UL)
7178#define GPDMA_CONTROL5_DWIDTH_Msk (0xe00000UL)
7179#define GPDMA_CONTROL5_SI_Pos (26UL)
7180#define GPDMA_CONTROL5_SI_Msk (0x4000000UL)
7181#define GPDMA_CONTROL5_DI_Pos (27UL)
7182#define GPDMA_CONTROL5_DI_Msk (0x8000000UL)
7183#define GPDMA_CONTROL5_PROT1_Pos (28UL)
7184#define GPDMA_CONTROL5_PROT1_Msk (0x10000000UL)
7185#define GPDMA_CONTROL5_PROT2_Pos (29UL)
7186#define GPDMA_CONTROL5_PROT2_Msk (0x20000000UL)
7187#define GPDMA_CONTROL5_PROT3_Pos (30UL)
7188#define GPDMA_CONTROL5_PROT3_Msk (0x40000000UL)
7189#define GPDMA_CONTROL5_I_Pos (31UL)
7190#define GPDMA_CONTROL5_I_Msk (0x80000000UL)
7191/* ======================================================= CONTROL6 ======================================================== */
7192#define GPDMA_CONTROL6_TRANSFERSIZE_Pos (0UL)
7193#define GPDMA_CONTROL6_TRANSFERSIZE_Msk (0xfffUL)
7194#define GPDMA_CONTROL6_SBSIZE_Pos (12UL)
7195#define GPDMA_CONTROL6_SBSIZE_Msk (0x7000UL)
7196#define GPDMA_CONTROL6_DBSIZE_Pos (15UL)
7197#define GPDMA_CONTROL6_DBSIZE_Msk (0x38000UL)
7198#define GPDMA_CONTROL6_SWIDTH_Pos (18UL)
7199#define GPDMA_CONTROL6_SWIDTH_Msk (0x1c0000UL)
7200#define GPDMA_CONTROL6_DWIDTH_Pos (21UL)
7201#define GPDMA_CONTROL6_DWIDTH_Msk (0xe00000UL)
7202#define GPDMA_CONTROL6_SI_Pos (26UL)
7203#define GPDMA_CONTROL6_SI_Msk (0x4000000UL)
7204#define GPDMA_CONTROL6_DI_Pos (27UL)
7205#define GPDMA_CONTROL6_DI_Msk (0x8000000UL)
7206#define GPDMA_CONTROL6_PROT1_Pos (28UL)
7207#define GPDMA_CONTROL6_PROT1_Msk (0x10000000UL)
7208#define GPDMA_CONTROL6_PROT2_Pos (29UL)
7209#define GPDMA_CONTROL6_PROT2_Msk (0x20000000UL)
7210#define GPDMA_CONTROL6_PROT3_Pos (30UL)
7211#define GPDMA_CONTROL6_PROT3_Msk (0x40000000UL)
7212#define GPDMA_CONTROL6_I_Pos (31UL)
7213#define GPDMA_CONTROL6_I_Msk (0x80000000UL)
7214/* ======================================================= CONTROL7 ======================================================== */
7215#define GPDMA_CONTROL7_TRANSFERSIZE_Pos (0UL)
7216#define GPDMA_CONTROL7_TRANSFERSIZE_Msk (0xfffUL)
7217#define GPDMA_CONTROL7_SBSIZE_Pos (12UL)
7218#define GPDMA_CONTROL7_SBSIZE_Msk (0x7000UL)
7219#define GPDMA_CONTROL7_DBSIZE_Pos (15UL)
7220#define GPDMA_CONTROL7_DBSIZE_Msk (0x38000UL)
7221#define GPDMA_CONTROL7_SWIDTH_Pos (18UL)
7222#define GPDMA_CONTROL7_SWIDTH_Msk (0x1c0000UL)
7223#define GPDMA_CONTROL7_DWIDTH_Pos (21UL)
7224#define GPDMA_CONTROL7_DWIDTH_Msk (0xe00000UL)
7225#define GPDMA_CONTROL7_SI_Pos (26UL)
7226#define GPDMA_CONTROL7_SI_Msk (0x4000000UL)
7227#define GPDMA_CONTROL7_DI_Pos (27UL)
7228#define GPDMA_CONTROL7_DI_Msk (0x8000000UL)
7229#define GPDMA_CONTROL7_PROT1_Pos (28UL)
7230#define GPDMA_CONTROL7_PROT1_Msk (0x10000000UL)
7231#define GPDMA_CONTROL7_PROT2_Pos (29UL)
7232#define GPDMA_CONTROL7_PROT2_Msk (0x20000000UL)
7233#define GPDMA_CONTROL7_PROT3_Pos (30UL)
7234#define GPDMA_CONTROL7_PROT3_Msk (0x40000000UL)
7235#define GPDMA_CONTROL7_I_Pos (31UL)
7236#define GPDMA_CONTROL7_I_Msk (0x80000000UL)
7237/* ======================================================== CONFIG0 ======================================================== */
7238#define GPDMA_CONFIG0_E_Pos (0UL)
7239#define GPDMA_CONFIG0_E_Msk (0x1UL)
7240#define GPDMA_CONFIG0_SRCPERIPHERAL_Pos (1UL)
7241#define GPDMA_CONFIG0_SRCPERIPHERAL_Msk (0x3eUL)
7242#define GPDMA_CONFIG0_DESTPERIPHERAL_Pos (6UL)
7243#define GPDMA_CONFIG0_DESTPERIPHERAL_Msk (0x7c0UL)
7244#define GPDMA_CONFIG0_TRANSFERTYPE_Pos (11UL)
7245#define GPDMA_CONFIG0_TRANSFERTYPE_Msk (0x3800UL)
7246#define GPDMA_CONFIG0_IE_Pos (14UL)
7247#define GPDMA_CONFIG0_IE_Msk (0x4000UL)
7248#define GPDMA_CONFIG0_ITC_Pos (15UL)
7249#define GPDMA_CONFIG0_ITC_Msk (0x8000UL)
7250#define GPDMA_CONFIG0_L_Pos (16UL)
7251#define GPDMA_CONFIG0_L_Msk (0x10000UL)
7252#define GPDMA_CONFIG0_A_Pos (17UL)
7253#define GPDMA_CONFIG0_A_Msk (0x20000UL)
7254#define GPDMA_CONFIG0_H_Pos (18UL)
7255#define GPDMA_CONFIG0_H_Msk (0x40000UL)
7256/* ======================================================== CONFIG1 ======================================================== */
7257#define GPDMA_CONFIG1_E_Pos (0UL)
7258#define GPDMA_CONFIG1_E_Msk (0x1UL)
7259#define GPDMA_CONFIG1_SRCPERIPHERAL_Pos (1UL)
7260#define GPDMA_CONFIG1_SRCPERIPHERAL_Msk (0x3eUL)
7261#define GPDMA_CONFIG1_DESTPERIPHERAL_Pos (6UL)
7262#define GPDMA_CONFIG1_DESTPERIPHERAL_Msk (0x7c0UL)
7263#define GPDMA_CONFIG1_TRANSFERTYPE_Pos (11UL)
7264#define GPDMA_CONFIG1_TRANSFERTYPE_Msk (0x3800UL)
7265#define GPDMA_CONFIG1_IE_Pos (14UL)
7266#define GPDMA_CONFIG1_IE_Msk (0x4000UL)
7267#define GPDMA_CONFIG1_ITC_Pos (15UL)
7268#define GPDMA_CONFIG1_ITC_Msk (0x8000UL)
7269#define GPDMA_CONFIG1_L_Pos (16UL)
7270#define GPDMA_CONFIG1_L_Msk (0x10000UL)
7271#define GPDMA_CONFIG1_A_Pos (17UL)
7272#define GPDMA_CONFIG1_A_Msk (0x20000UL)
7273#define GPDMA_CONFIG1_H_Pos (18UL)
7274#define GPDMA_CONFIG1_H_Msk (0x40000UL)
7275/* ======================================================== CONFIG2 ======================================================== */
7276#define GPDMA_CONFIG2_E_Pos (0UL)
7277#define GPDMA_CONFIG2_E_Msk (0x1UL)
7278#define GPDMA_CONFIG2_SRCPERIPHERAL_Pos (1UL)
7279#define GPDMA_CONFIG2_SRCPERIPHERAL_Msk (0x3eUL)
7280#define GPDMA_CONFIG2_DESTPERIPHERAL_Pos (6UL)
7281#define GPDMA_CONFIG2_DESTPERIPHERAL_Msk (0x7c0UL)
7282#define GPDMA_CONFIG2_TRANSFERTYPE_Pos (11UL)
7283#define GPDMA_CONFIG2_TRANSFERTYPE_Msk (0x3800UL)
7284#define GPDMA_CONFIG2_IE_Pos (14UL)
7285#define GPDMA_CONFIG2_IE_Msk (0x4000UL)
7286#define GPDMA_CONFIG2_ITC_Pos (15UL)
7287#define GPDMA_CONFIG2_ITC_Msk (0x8000UL)
7288#define GPDMA_CONFIG2_L_Pos (16UL)
7289#define GPDMA_CONFIG2_L_Msk (0x10000UL)
7290#define GPDMA_CONFIG2_A_Pos (17UL)
7291#define GPDMA_CONFIG2_A_Msk (0x20000UL)
7292#define GPDMA_CONFIG2_H_Pos (18UL)
7293#define GPDMA_CONFIG2_H_Msk (0x40000UL)
7294/* ======================================================== CONFIG3 ======================================================== */
7295#define GPDMA_CONFIG3_E_Pos (0UL)
7296#define GPDMA_CONFIG3_E_Msk (0x1UL)
7297#define GPDMA_CONFIG3_SRCPERIPHERAL_Pos (1UL)
7298#define GPDMA_CONFIG3_SRCPERIPHERAL_Msk (0x3eUL)
7299#define GPDMA_CONFIG3_DESTPERIPHERAL_Pos (6UL)
7300#define GPDMA_CONFIG3_DESTPERIPHERAL_Msk (0x7c0UL)
7301#define GPDMA_CONFIG3_TRANSFERTYPE_Pos (11UL)
7302#define GPDMA_CONFIG3_TRANSFERTYPE_Msk (0x3800UL)
7303#define GPDMA_CONFIG3_IE_Pos (14UL)
7304#define GPDMA_CONFIG3_IE_Msk (0x4000UL)
7305#define GPDMA_CONFIG3_ITC_Pos (15UL)
7306#define GPDMA_CONFIG3_ITC_Msk (0x8000UL)
7307#define GPDMA_CONFIG3_L_Pos (16UL)
7308#define GPDMA_CONFIG3_L_Msk (0x10000UL)
7309#define GPDMA_CONFIG3_A_Pos (17UL)
7310#define GPDMA_CONFIG3_A_Msk (0x20000UL)
7311#define GPDMA_CONFIG3_H_Pos (18UL)
7312#define GPDMA_CONFIG3_H_Msk (0x40000UL)
7313/* ======================================================== CONFIG4 ======================================================== */
7314#define GPDMA_CONFIG4_E_Pos (0UL)
7315#define GPDMA_CONFIG4_E_Msk (0x1UL)
7316#define GPDMA_CONFIG4_SRCPERIPHERAL_Pos (1UL)
7317#define GPDMA_CONFIG4_SRCPERIPHERAL_Msk (0x3eUL)
7318#define GPDMA_CONFIG4_DESTPERIPHERAL_Pos (6UL)
7319#define GPDMA_CONFIG4_DESTPERIPHERAL_Msk (0x7c0UL)
7320#define GPDMA_CONFIG4_TRANSFERTYPE_Pos (11UL)
7321#define GPDMA_CONFIG4_TRANSFERTYPE_Msk (0x3800UL)
7322#define GPDMA_CONFIG4_IE_Pos (14UL)
7323#define GPDMA_CONFIG4_IE_Msk (0x4000UL)
7324#define GPDMA_CONFIG4_ITC_Pos (15UL)
7325#define GPDMA_CONFIG4_ITC_Msk (0x8000UL)
7326#define GPDMA_CONFIG4_L_Pos (16UL)
7327#define GPDMA_CONFIG4_L_Msk (0x10000UL)
7328#define GPDMA_CONFIG4_A_Pos (17UL)
7329#define GPDMA_CONFIG4_A_Msk (0x20000UL)
7330#define GPDMA_CONFIG4_H_Pos (18UL)
7331#define GPDMA_CONFIG4_H_Msk (0x40000UL)
7332/* ======================================================== CONFIG5 ======================================================== */
7333#define GPDMA_CONFIG5_E_Pos (0UL)
7334#define GPDMA_CONFIG5_E_Msk (0x1UL)
7335#define GPDMA_CONFIG5_SRCPERIPHERAL_Pos (1UL)
7336#define GPDMA_CONFIG5_SRCPERIPHERAL_Msk (0x3eUL)
7337#define GPDMA_CONFIG5_DESTPERIPHERAL_Pos (6UL)
7338#define GPDMA_CONFIG5_DESTPERIPHERAL_Msk (0x7c0UL)
7339#define GPDMA_CONFIG5_TRANSFERTYPE_Pos (11UL)
7340#define GPDMA_CONFIG5_TRANSFERTYPE_Msk (0x3800UL)
7341#define GPDMA_CONFIG5_IE_Pos (14UL)
7342#define GPDMA_CONFIG5_IE_Msk (0x4000UL)
7343#define GPDMA_CONFIG5_ITC_Pos (15UL)
7344#define GPDMA_CONFIG5_ITC_Msk (0x8000UL)
7345#define GPDMA_CONFIG5_L_Pos (16UL)
7346#define GPDMA_CONFIG5_L_Msk (0x10000UL)
7347#define GPDMA_CONFIG5_A_Pos (17UL)
7348#define GPDMA_CONFIG5_A_Msk (0x20000UL)
7349#define GPDMA_CONFIG5_H_Pos (18UL)
7350#define GPDMA_CONFIG5_H_Msk (0x40000UL)
7351/* ======================================================== CONFIG6 ======================================================== */
7352#define GPDMA_CONFIG6_E_Pos (0UL)
7353#define GPDMA_CONFIG6_E_Msk (0x1UL)
7354#define GPDMA_CONFIG6_SRCPERIPHERAL_Pos (1UL)
7355#define GPDMA_CONFIG6_SRCPERIPHERAL_Msk (0x3eUL)
7356#define GPDMA_CONFIG6_DESTPERIPHERAL_Pos (6UL)
7357#define GPDMA_CONFIG6_DESTPERIPHERAL_Msk (0x7c0UL)
7358#define GPDMA_CONFIG6_TRANSFERTYPE_Pos (11UL)
7359#define GPDMA_CONFIG6_TRANSFERTYPE_Msk (0x3800UL)
7360#define GPDMA_CONFIG6_IE_Pos (14UL)
7361#define GPDMA_CONFIG6_IE_Msk (0x4000UL)
7362#define GPDMA_CONFIG6_ITC_Pos (15UL)
7363#define GPDMA_CONFIG6_ITC_Msk (0x8000UL)
7364#define GPDMA_CONFIG6_L_Pos (16UL)
7365#define GPDMA_CONFIG6_L_Msk (0x10000UL)
7366#define GPDMA_CONFIG6_A_Pos (17UL)
7367#define GPDMA_CONFIG6_A_Msk (0x20000UL)
7368#define GPDMA_CONFIG6_H_Pos (18UL)
7369#define GPDMA_CONFIG6_H_Msk (0x40000UL)
7370/* ======================================================== CONFIG7 ======================================================== */
7371#define GPDMA_CONFIG7_E_Pos (0UL)
7372#define GPDMA_CONFIG7_E_Msk (0x1UL)
7373#define GPDMA_CONFIG7_SRCPERIPHERAL_Pos (1UL)
7374#define GPDMA_CONFIG7_SRCPERIPHERAL_Msk (0x3eUL)
7375#define GPDMA_CONFIG7_DESTPERIPHERAL_Pos (6UL)
7376#define GPDMA_CONFIG7_DESTPERIPHERAL_Msk (0x7c0UL)
7377#define GPDMA_CONFIG7_TRANSFERTYPE_Pos (11UL)
7378#define GPDMA_CONFIG7_TRANSFERTYPE_Msk (0x3800UL)
7379#define GPDMA_CONFIG7_IE_Pos (14UL)
7380#define GPDMA_CONFIG7_IE_Msk (0x4000UL)
7381#define GPDMA_CONFIG7_ITC_Pos (15UL)
7382#define GPDMA_CONFIG7_ITC_Msk (0x8000UL)
7383#define GPDMA_CONFIG7_L_Pos (16UL)
7384#define GPDMA_CONFIG7_L_Msk (0x10000UL)
7385#define GPDMA_CONFIG7_A_Pos (17UL)
7386#define GPDMA_CONFIG7_A_Msk (0x20000UL)
7387#define GPDMA_CONFIG7_H_Pos (18UL)
7388#define GPDMA_CONFIG7_H_Msk (0x40000UL)
7391/* =========================================================================================================================== */
7392/* ================ LPC_USB ================ */
7393/* =========================================================================================================================== */
7394
7395/* ========================================================= INTST ========================================================= */
7396#define USB_INTST_TMR_Pos (0UL)
7397#define USB_INTST_TMR_Msk (0x1UL)
7398#define USB_INTST_REMOVE_PU_Pos (1UL)
7399#define USB_INTST_REMOVE_PU_Msk (0x2UL)
7400#define USB_INTST_HNP_FAILURE_Pos (2UL)
7401#define USB_INTST_HNP_FAILURE_Msk (0x4UL)
7402#define USB_INTST_HNP_SUCCESS_Pos (3UL)
7403#define USB_INTST_HNP_SUCCESS_Msk (0x8UL)
7404/* ========================================================= INTEN ========================================================= */
7405#define USB_INTEN_TMR_EN_Pos (0UL)
7406#define USB_INTEN_TMR_EN_Msk (0x1UL)
7407#define USB_INTEN_REMOVE_PU_EN_Pos (1UL)
7408#define USB_INTEN_REMOVE_PU_EN_Msk (0x2UL)
7409#define USB_INTEN_HNP_FAILURE_EN_Pos (2UL)
7410#define USB_INTEN_HNP_FAILURE_EN_Msk (0x4UL)
7411#define USB_INTEN_HNP_SUCCES_EN_Pos (3UL)
7412#define USB_INTEN_HNP_SUCCES_EN_Msk (0x8UL)
7413/* ======================================================== INTSET ========================================================= */
7414#define USB_INTSET_TMR_SET_Pos (0UL)
7415#define USB_INTSET_TMR_SET_Msk (0x1UL)
7416#define USB_INTSET_REMOVE_PU_SET_Pos (1UL)
7417#define USB_INTSET_REMOVE_PU_SET_Msk (0x2UL)
7418#define USB_INTSET_HNP_FAILURE_SET_Pos (2UL)
7419#define USB_INTSET_HNP_FAILURE_SET_Msk (0x4UL)
7420#define USB_INTSET_HNP_SUCCES_SET_Pos (3UL)
7421#define USB_INTSET_HNP_SUCCES_SET_Msk (0x8UL)
7422/* ======================================================== INTCLR ========================================================= */
7423#define USB_INTCLR_TMR_CLR_Pos (0UL)
7424#define USB_INTCLR_TMR_CLR_Msk (0x1UL)
7425#define USB_INTCLR_REMOVE_PU_CLR_Pos (1UL)
7426#define USB_INTCLR_REMOVE_PU_CLR_Msk (0x2UL)
7427#define USB_INTCLR_HNP_FAILURE_CLR_Pos (2UL)
7428#define USB_INTCLR_HNP_FAILURE_CLR_Msk (0x4UL)
7429#define USB_INTCLR_HNP_SUCCES_CLR_Pos (3UL)
7430#define USB_INTCLR_HNP_SUCCES_CLR_Msk (0x8UL)
7431/* ======================================================== STCTRL ========================================================= */
7432#define USB_STCTRL_PORT_FUNC_Pos (0UL)
7433#define USB_STCTRL_PORT_FUNC_Msk (0x3UL)
7434#define USB_STCTRL_TMR_SCALE_Pos (2UL)
7435#define USB_STCTRL_TMR_SCALE_Msk (0xcUL)
7436#define USB_STCTRL_TMR_MODE_Pos (4UL)
7437#define USB_STCTRL_TMR_MODE_Msk (0x10UL)
7438#define USB_STCTRL_TMR_EN_Pos (5UL)
7439#define USB_STCTRL_TMR_EN_Msk (0x20UL)
7440#define USB_STCTRL_TMR_RST_Pos (6UL)
7441#define USB_STCTRL_TMR_RST_Msk (0x40UL)
7442#define USB_STCTRL_B_HNP_TRACK_Pos (8UL)
7443#define USB_STCTRL_B_HNP_TRACK_Msk (0x100UL)
7444#define USB_STCTRL_A_HNP_TRACK_Pos (9UL)
7445#define USB_STCTRL_A_HNP_TRACK_Msk (0x200UL)
7446#define USB_STCTRL_PU_REMOVED_Pos (10UL)
7447#define USB_STCTRL_PU_REMOVED_Msk (0x400UL)
7448#define USB_STCTRL_TMR_CNT_Pos (16UL)
7449#define USB_STCTRL_TMR_CNT_Msk (0xffff0000UL)
7450/* ========================================================== TMR ========================================================== */
7451#define USB_TMR_TIMEOUT_CNT_Pos (0UL)
7452#define USB_TMR_TIMEOUT_CNT_Msk (0xffffUL)
7453/* ======================================================= DEVINTST ======================================================== */
7454#define USB_DEVINTST_FRAME_Pos (0UL)
7455#define USB_DEVINTST_FRAME_Msk (0x1UL)
7456#define USB_DEVINTST_EP_FAST_Pos (1UL)
7457#define USB_DEVINTST_EP_FAST_Msk (0x2UL)
7458#define USB_DEVINTST_EP_SLOW_Pos (2UL)
7459#define USB_DEVINTST_EP_SLOW_Msk (0x4UL)
7460#define USB_DEVINTST_DEV_STAT_Pos (3UL)
7461#define USB_DEVINTST_DEV_STAT_Msk (0x8UL)
7462#define USB_DEVINTST_CCEMPTY_Pos (4UL)
7463#define USB_DEVINTST_CCEMPTY_Msk (0x10UL)
7464#define USB_DEVINTST_CDFULL_Pos (5UL)
7465#define USB_DEVINTST_CDFULL_Msk (0x20UL)
7466#define USB_DEVINTST_RxENDPKT_Pos (6UL)
7467#define USB_DEVINTST_RxENDPKT_Msk (0x40UL)
7468#define USB_DEVINTST_TxENDPKT_Pos (7UL)
7469#define USB_DEVINTST_TxENDPKT_Msk (0x80UL)
7470#define USB_DEVINTST_EP_RLZED_Pos (8UL)
7471#define USB_DEVINTST_EP_RLZED_Msk (0x100UL)
7472#define USB_DEVINTST_ERR_INT_Pos (9UL)
7473#define USB_DEVINTST_ERR_INT_Msk (0x200UL)
7474/* ======================================================= DEVINTEN ======================================================== */
7475#define USB_DEVINTEN_FRAMEEN_Pos (0UL)
7476#define USB_DEVINTEN_FRAMEEN_Msk (0x1UL)
7477#define USB_DEVINTEN_EP_FASTEN_Pos (1UL)
7478#define USB_DEVINTEN_EP_FASTEN_Msk (0x2UL)
7479#define USB_DEVINTEN_EP_SLOWEN_Pos (2UL)
7480#define USB_DEVINTEN_EP_SLOWEN_Msk (0x4UL)
7481#define USB_DEVINTEN_DEV_STATEN_Pos (3UL)
7482#define USB_DEVINTEN_DEV_STATEN_Msk (0x8UL)
7483#define USB_DEVINTEN_CCEMPTYEN_Pos (4UL)
7484#define USB_DEVINTEN_CCEMPTYEN_Msk (0x10UL)
7485#define USB_DEVINTEN_CDFULLEN_Pos (5UL)
7486#define USB_DEVINTEN_CDFULLEN_Msk (0x20UL)
7487#define USB_DEVINTEN_RxENDPKTEN_Pos (6UL)
7488#define USB_DEVINTEN_RxENDPKTEN_Msk (0x40UL)
7489#define USB_DEVINTEN_TxENDPKTEN_Pos (7UL)
7490#define USB_DEVINTEN_TxENDPKTEN_Msk (0x80UL)
7491#define USB_DEVINTEN_EP_RLZEDEN_Pos (8UL)
7492#define USB_DEVINTEN_EP_RLZEDEN_Msk (0x100UL)
7493#define USB_DEVINTEN_ERR_INTEN_Pos (9UL)
7494#define USB_DEVINTEN_ERR_INTEN_Msk (0x200UL)
7495/* ======================================================= DEVINTCLR ======================================================= */
7496#define USB_DEVINTCLR_FRAMECLR_Pos (0UL)
7497#define USB_DEVINTCLR_FRAMECLR_Msk (0x1UL)
7498#define USB_DEVINTCLR_EP_FASTCLR_Pos (1UL)
7499#define USB_DEVINTCLR_EP_FASTCLR_Msk (0x2UL)
7500#define USB_DEVINTCLR_EP_SLOWCLR_Pos (2UL)
7501#define USB_DEVINTCLR_EP_SLOWCLR_Msk (0x4UL)
7502#define USB_DEVINTCLR_DEV_STATCLR_Pos (3UL)
7503#define USB_DEVINTCLR_DEV_STATCLR_Msk (0x8UL)
7504#define USB_DEVINTCLR_CCEMPTYCLR_Pos (4UL)
7505#define USB_DEVINTCLR_CCEMPTYCLR_Msk (0x10UL)
7506#define USB_DEVINTCLR_CDFULLCLR_Pos (5UL)
7507#define USB_DEVINTCLR_CDFULLCLR_Msk (0x20UL)
7508#define USB_DEVINTCLR_RxENDPKTCLR_Pos (6UL)
7509#define USB_DEVINTCLR_RxENDPKTCLR_Msk (0x40UL)
7510#define USB_DEVINTCLR_TxENDPKTCLR_Pos (7UL)
7511#define USB_DEVINTCLR_TxENDPKTCLR_Msk (0x80UL)
7512#define USB_DEVINTCLR_EP_RLZEDCLR_Pos (8UL)
7513#define USB_DEVINTCLR_EP_RLZEDCLR_Msk (0x100UL)
7514#define USB_DEVINTCLR_ERR_INTCLR_Pos (9UL)
7515#define USB_DEVINTCLR_ERR_INTCLR_Msk (0x200UL)
7516/* ======================================================= DEVINTSET ======================================================= */
7517#define USB_DEVINTSET_FRAMESET_Pos (0UL)
7518#define USB_DEVINTSET_FRAMESET_Msk (0x1UL)
7519#define USB_DEVINTSET_EP_FASTSET_Pos (1UL)
7520#define USB_DEVINTSET_EP_FASTSET_Msk (0x2UL)
7521#define USB_DEVINTSET_EP_SLOWSET_Pos (2UL)
7522#define USB_DEVINTSET_EP_SLOWSET_Msk (0x4UL)
7523#define USB_DEVINTSET_DEV_STATSET_Pos (3UL)
7524#define USB_DEVINTSET_DEV_STATSET_Msk (0x8UL)
7525#define USB_DEVINTSET_CCEMPTYSET_Pos (4UL)
7526#define USB_DEVINTSET_CCEMPTYSET_Msk (0x10UL)
7527#define USB_DEVINTSET_CDFULLSET_Pos (5UL)
7528#define USB_DEVINTSET_CDFULLSET_Msk (0x20UL)
7529#define USB_DEVINTSET_RxENDPKTSET_Pos (6UL)
7530#define USB_DEVINTSET_RxENDPKTSET_Msk (0x40UL)
7531#define USB_DEVINTSET_TxENDPKTSET_Pos (7UL)
7532#define USB_DEVINTSET_TxENDPKTSET_Msk (0x80UL)
7533#define USB_DEVINTSET_EP_RLZEDSET_Pos (8UL)
7534#define USB_DEVINTSET_EP_RLZEDSET_Msk (0x100UL)
7535#define USB_DEVINTSET_ERR_INTSET_Pos (9UL)
7536#define USB_DEVINTSET_ERR_INTSET_Msk (0x200UL)
7537/* ======================================================== CMDCODE ======================================================== */
7538#define USB_CMDCODE_CMD_PHASE_Pos (8UL)
7539#define USB_CMDCODE_CMD_PHASE_Msk (0xff00UL)
7540#define USB_CMDCODE_CMD_CODE_WDATA_Pos (16UL)
7541#define USB_CMDCODE_CMD_CODE_WDATA_Msk (0xff0000UL)
7542/* ======================================================== CMDDATA ======================================================== */
7543#define USB_CMDDATA_CMD_RDATA_Pos (0UL)
7544#define USB_CMDDATA_CMD_RDATA_Msk (0xffUL)
7545/* ======================================================== RXDATA ========================================================= */
7546#define USB_RXDATA_RX_DATA_Pos (0UL)
7547#define USB_RXDATA_RX_DATA_Msk (0xffffffffUL)
7548/* ======================================================== TXDATA ========================================================= */
7549#define USB_TXDATA_TX_DATA_Pos (0UL)
7550#define USB_TXDATA_TX_DATA_Msk (0xffffffffUL)
7551/* ======================================================== RXPLEN ========================================================= */
7552#define USB_RXPLEN_PKT_LNGTH_Pos (0UL)
7553#define USB_RXPLEN_PKT_LNGTH_Msk (0x3ffUL)
7554#define USB_RXPLEN_DV_Pos (10UL)
7555#define USB_RXPLEN_DV_Msk (0x400UL)
7556#define USB_RXPLEN_PKT_RDY_Pos (11UL)
7557#define USB_RXPLEN_PKT_RDY_Msk (0x800UL)
7558/* ======================================================== TXPLEN ========================================================= */
7559#define USB_TXPLEN_PKT_LNGTH_Pos (0UL)
7560#define USB_TXPLEN_PKT_LNGTH_Msk (0x3ffUL)
7561/* ========================================================= CTRL ========================================================== */
7562#define USB_CTRL_RD_EN_Pos (0UL)
7563#define USB_CTRL_RD_EN_Msk (0x1UL)
7564#define USB_CTRL_WR_EN_Pos (1UL)
7565#define USB_CTRL_WR_EN_Msk (0x2UL)
7566#define USB_CTRL_LOG_ENDPOINT_Pos (2UL)
7567#define USB_CTRL_LOG_ENDPOINT_Msk (0x3cUL)
7568/* ======================================================= DEVINTPRI ======================================================= */
7569#define USB_DEVINTPRI_FRAME_Pos (0UL)
7570#define USB_DEVINTPRI_FRAME_Msk (0x1UL)
7571#define USB_DEVINTPRI_EP_FAST_Pos (1UL)
7572#define USB_DEVINTPRI_EP_FAST_Msk (0x2UL)
7573/* ======================================================== EPINTST ======================================================== */
7574#define USB_EPINTST_EPST0_Pos (0UL)
7575#define USB_EPINTST_EPST0_Msk (0x1UL)
7576#define USB_EPINTST_EPST1_Pos (1UL)
7577#define USB_EPINTST_EPST1_Msk (0x2UL)
7578#define USB_EPINTST_EPST2_Pos (2UL)
7579#define USB_EPINTST_EPST2_Msk (0x4UL)
7580#define USB_EPINTST_EPST3_Pos (3UL)
7581#define USB_EPINTST_EPST3_Msk (0x8UL)
7582#define USB_EPINTST_EPST4_Pos (4UL)
7583#define USB_EPINTST_EPST4_Msk (0x10UL)
7584#define USB_EPINTST_EPST5_Pos (5UL)
7585#define USB_EPINTST_EPST5_Msk (0x20UL)
7586#define USB_EPINTST_EPST6_Pos (6UL)
7587#define USB_EPINTST_EPST6_Msk (0x40UL)
7588#define USB_EPINTST_EPST7_Pos (7UL)
7589#define USB_EPINTST_EPST7_Msk (0x80UL)
7590#define USB_EPINTST_EPST8_Pos (8UL)
7591#define USB_EPINTST_EPST8_Msk (0x100UL)
7592#define USB_EPINTST_EPST9_Pos (9UL)
7593#define USB_EPINTST_EPST9_Msk (0x200UL)
7594#define USB_EPINTST_EPST10_Pos (10UL)
7595#define USB_EPINTST_EPST10_Msk (0x400UL)
7596#define USB_EPINTST_EPST11_Pos (11UL)
7597#define USB_EPINTST_EPST11_Msk (0x800UL)
7598#define USB_EPINTST_EPST12_Pos (12UL)
7599#define USB_EPINTST_EPST12_Msk (0x1000UL)
7600#define USB_EPINTST_EPST13_Pos (13UL)
7601#define USB_EPINTST_EPST13_Msk (0x2000UL)
7602#define USB_EPINTST_EPST14_Pos (14UL)
7603#define USB_EPINTST_EPST14_Msk (0x4000UL)
7604#define USB_EPINTST_EPST15_Pos (15UL)
7605#define USB_EPINTST_EPST15_Msk (0x8000UL)
7606#define USB_EPINTST_EPST16_Pos (16UL)
7607#define USB_EPINTST_EPST16_Msk (0x10000UL)
7608#define USB_EPINTST_EPST17_Pos (17UL)
7609#define USB_EPINTST_EPST17_Msk (0x20000UL)
7610#define USB_EPINTST_EPST18_Pos (18UL)
7611#define USB_EPINTST_EPST18_Msk (0x40000UL)
7612#define USB_EPINTST_EPST19_Pos (19UL)
7613#define USB_EPINTST_EPST19_Msk (0x80000UL)
7614#define USB_EPINTST_EPST20_Pos (20UL)
7615#define USB_EPINTST_EPST20_Msk (0x100000UL)
7616#define USB_EPINTST_EPST21_Pos (21UL)
7617#define USB_EPINTST_EPST21_Msk (0x200000UL)
7618#define USB_EPINTST_EPST22_Pos (22UL)
7619#define USB_EPINTST_EPST22_Msk (0x400000UL)
7620#define USB_EPINTST_EPST23_Pos (23UL)
7621#define USB_EPINTST_EPST23_Msk (0x800000UL)
7622#define USB_EPINTST_EPST24_Pos (24UL)
7623#define USB_EPINTST_EPST24_Msk (0x1000000UL)
7624#define USB_EPINTST_EPST25_Pos (25UL)
7625#define USB_EPINTST_EPST25_Msk (0x2000000UL)
7626#define USB_EPINTST_EPST26_Pos (26UL)
7627#define USB_EPINTST_EPST26_Msk (0x4000000UL)
7628#define USB_EPINTST_EPST27_Pos (27UL)
7629#define USB_EPINTST_EPST27_Msk (0x8000000UL)
7630#define USB_EPINTST_EPST28_Pos (28UL)
7631#define USB_EPINTST_EPST28_Msk (0x10000000UL)
7632#define USB_EPINTST_EPST29_Pos (29UL)
7633#define USB_EPINTST_EPST29_Msk (0x20000000UL)
7634#define USB_EPINTST_EPST30_Pos (30UL)
7635#define USB_EPINTST_EPST30_Msk (0x40000000UL)
7636#define USB_EPINTST_EPST31_Pos (31UL)
7637#define USB_EPINTST_EPST31_Msk (0x80000000UL)
7638/* ======================================================== EPINTEN ======================================================== */
7639#define USB_EPINTEN_EPEN0_Pos (0UL)
7640#define USB_EPINTEN_EPEN0_Msk (0x1UL)
7641#define USB_EPINTEN_EPEN1_Pos (1UL)
7642#define USB_EPINTEN_EPEN1_Msk (0x2UL)
7643#define USB_EPINTEN_EPEN2_Pos (2UL)
7644#define USB_EPINTEN_EPEN2_Msk (0x4UL)
7645#define USB_EPINTEN_EPEN3_Pos (3UL)
7646#define USB_EPINTEN_EPEN3_Msk (0x8UL)
7647#define USB_EPINTEN_EPEN4_Pos (4UL)
7648#define USB_EPINTEN_EPEN4_Msk (0x10UL)
7649#define USB_EPINTEN_EPEN5_Pos (5UL)
7650#define USB_EPINTEN_EPEN5_Msk (0x20UL)
7651#define USB_EPINTEN_EPEN6_Pos (6UL)
7652#define USB_EPINTEN_EPEN6_Msk (0x40UL)
7653#define USB_EPINTEN_EPEN7_Pos (7UL)
7654#define USB_EPINTEN_EPEN7_Msk (0x80UL)
7655#define USB_EPINTEN_EPEN8_Pos (8UL)
7656#define USB_EPINTEN_EPEN8_Msk (0x100UL)
7657#define USB_EPINTEN_EPEN9_Pos (9UL)
7658#define USB_EPINTEN_EPEN9_Msk (0x200UL)
7659#define USB_EPINTEN_EPEN10_Pos (10UL)
7660#define USB_EPINTEN_EPEN10_Msk (0x400UL)
7661#define USB_EPINTEN_EPEN11_Pos (11UL)
7662#define USB_EPINTEN_EPEN11_Msk (0x800UL)
7663#define USB_EPINTEN_EPEN12_Pos (12UL)
7664#define USB_EPINTEN_EPEN12_Msk (0x1000UL)
7665#define USB_EPINTEN_EPEN13_Pos (13UL)
7666#define USB_EPINTEN_EPEN13_Msk (0x2000UL)
7667#define USB_EPINTEN_EPEN14_Pos (14UL)
7668#define USB_EPINTEN_EPEN14_Msk (0x4000UL)
7669#define USB_EPINTEN_EPEN15_Pos (15UL)
7670#define USB_EPINTEN_EPEN15_Msk (0x8000UL)
7671#define USB_EPINTEN_EPEN16_Pos (16UL)
7672#define USB_EPINTEN_EPEN16_Msk (0x10000UL)
7673#define USB_EPINTEN_EPEN17_Pos (17UL)
7674#define USB_EPINTEN_EPEN17_Msk (0x20000UL)
7675#define USB_EPINTEN_EPEN18_Pos (18UL)
7676#define USB_EPINTEN_EPEN18_Msk (0x40000UL)
7677#define USB_EPINTEN_EPEN19_Pos (19UL)
7678#define USB_EPINTEN_EPEN19_Msk (0x80000UL)
7679#define USB_EPINTEN_EPEN20_Pos (20UL)
7680#define USB_EPINTEN_EPEN20_Msk (0x100000UL)
7681#define USB_EPINTEN_EPEN21_Pos (21UL)
7682#define USB_EPINTEN_EPEN21_Msk (0x200000UL)
7683#define USB_EPINTEN_EPEN22_Pos (22UL)
7684#define USB_EPINTEN_EPEN22_Msk (0x400000UL)
7685#define USB_EPINTEN_EPEN23_Pos (23UL)
7686#define USB_EPINTEN_EPEN23_Msk (0x800000UL)
7687#define USB_EPINTEN_EPEN24_Pos (24UL)
7688#define USB_EPINTEN_EPEN24_Msk (0x1000000UL)
7689#define USB_EPINTEN_EPEN25_Pos (25UL)
7690#define USB_EPINTEN_EPEN25_Msk (0x2000000UL)
7691#define USB_EPINTEN_EPEN26_Pos (26UL)
7692#define USB_EPINTEN_EPEN26_Msk (0x4000000UL)
7693#define USB_EPINTEN_EPEN27_Pos (27UL)
7694#define USB_EPINTEN_EPEN27_Msk (0x8000000UL)
7695#define USB_EPINTEN_EPEN28_Pos (28UL)
7696#define USB_EPINTEN_EPEN28_Msk (0x10000000UL)
7697#define USB_EPINTEN_EPEN29_Pos (29UL)
7698#define USB_EPINTEN_EPEN29_Msk (0x20000000UL)
7699#define USB_EPINTEN_EPEN30_Pos (30UL)
7700#define USB_EPINTEN_EPEN30_Msk (0x40000000UL)
7701#define USB_EPINTEN_EPEN31_Pos (31UL)
7702#define USB_EPINTEN_EPEN31_Msk (0x80000000UL)
7703/* ======================================================= EPINTCLR ======================================================== */
7704#define USB_EPINTCLR_EPCLR0_Pos (0UL)
7705#define USB_EPINTCLR_EPCLR0_Msk (0x1UL)
7706#define USB_EPINTCLR_EPCLR1_Pos (1UL)
7707#define USB_EPINTCLR_EPCLR1_Msk (0x2UL)
7708#define USB_EPINTCLR_EPCLR2_Pos (2UL)
7709#define USB_EPINTCLR_EPCLR2_Msk (0x4UL)
7710#define USB_EPINTCLR_EPCLR3_Pos (3UL)
7711#define USB_EPINTCLR_EPCLR3_Msk (0x8UL)
7712#define USB_EPINTCLR_EPCLR4_Pos (4UL)
7713#define USB_EPINTCLR_EPCLR4_Msk (0x10UL)
7714#define USB_EPINTCLR_EPCLR5_Pos (5UL)
7715#define USB_EPINTCLR_EPCLR5_Msk (0x20UL)
7716#define USB_EPINTCLR_EPCLR6_Pos (6UL)
7717#define USB_EPINTCLR_EPCLR6_Msk (0x40UL)
7718#define USB_EPINTCLR_EPCLR7_Pos (7UL)
7719#define USB_EPINTCLR_EPCLR7_Msk (0x80UL)
7720#define USB_EPINTCLR_EPCLR8_Pos (8UL)
7721#define USB_EPINTCLR_EPCLR8_Msk (0x100UL)
7722#define USB_EPINTCLR_EPCLR9_Pos (9UL)
7723#define USB_EPINTCLR_EPCLR9_Msk (0x200UL)
7724#define USB_EPINTCLR_EPCLR10_Pos (10UL)
7725#define USB_EPINTCLR_EPCLR10_Msk (0x400UL)
7726#define USB_EPINTCLR_EPCLR11_Pos (11UL)
7727#define USB_EPINTCLR_EPCLR11_Msk (0x800UL)
7728#define USB_EPINTCLR_EPCLR12_Pos (12UL)
7729#define USB_EPINTCLR_EPCLR12_Msk (0x1000UL)
7730#define USB_EPINTCLR_EPCLR13_Pos (13UL)
7731#define USB_EPINTCLR_EPCLR13_Msk (0x2000UL)
7732#define USB_EPINTCLR_EPCLR14_Pos (14UL)
7733#define USB_EPINTCLR_EPCLR14_Msk (0x4000UL)
7734#define USB_EPINTCLR_EPCLR15_Pos (15UL)
7735#define USB_EPINTCLR_EPCLR15_Msk (0x8000UL)
7736#define USB_EPINTCLR_EPCLR16_Pos (16UL)
7737#define USB_EPINTCLR_EPCLR16_Msk (0x10000UL)
7738#define USB_EPINTCLR_EPCLR17_Pos (17UL)
7739#define USB_EPINTCLR_EPCLR17_Msk (0x20000UL)
7740#define USB_EPINTCLR_EPCLR18_Pos (18UL)
7741#define USB_EPINTCLR_EPCLR18_Msk (0x40000UL)
7742#define USB_EPINTCLR_EPCLR19_Pos (19UL)
7743#define USB_EPINTCLR_EPCLR19_Msk (0x80000UL)
7744#define USB_EPINTCLR_EPCLR20_Pos (20UL)
7745#define USB_EPINTCLR_EPCLR20_Msk (0x100000UL)
7746#define USB_EPINTCLR_EPCLR21_Pos (21UL)
7747#define USB_EPINTCLR_EPCLR21_Msk (0x200000UL)
7748#define USB_EPINTCLR_EPCLR22_Pos (22UL)
7749#define USB_EPINTCLR_EPCLR22_Msk (0x400000UL)
7750#define USB_EPINTCLR_EPCLR23_Pos (23UL)
7751#define USB_EPINTCLR_EPCLR23_Msk (0x800000UL)
7752#define USB_EPINTCLR_EPCLR24_Pos (24UL)
7753#define USB_EPINTCLR_EPCLR24_Msk (0x1000000UL)
7754#define USB_EPINTCLR_EPCLR25_Pos (25UL)
7755#define USB_EPINTCLR_EPCLR25_Msk (0x2000000UL)
7756#define USB_EPINTCLR_EPCLR26_Pos (26UL)
7757#define USB_EPINTCLR_EPCLR26_Msk (0x4000000UL)
7758#define USB_EPINTCLR_EPCLR27_Pos (27UL)
7759#define USB_EPINTCLR_EPCLR27_Msk (0x8000000UL)
7760#define USB_EPINTCLR_EPCLR28_Pos (28UL)
7761#define USB_EPINTCLR_EPCLR28_Msk (0x10000000UL)
7762#define USB_EPINTCLR_EPCLR29_Pos (29UL)
7763#define USB_EPINTCLR_EPCLR29_Msk (0x20000000UL)
7764#define USB_EPINTCLR_EPCLR30_Pos (30UL)
7765#define USB_EPINTCLR_EPCLR30_Msk (0x40000000UL)
7766#define USB_EPINTCLR_EPCLR31_Pos (31UL)
7767#define USB_EPINTCLR_EPCLR31_Msk (0x80000000UL)
7768/* ======================================================= EPINTSET ======================================================== */
7769#define USB_EPINTSET_EPSET0_Pos (0UL)
7770#define USB_EPINTSET_EPSET0_Msk (0x1UL)
7771#define USB_EPINTSET_EPSET1_Pos (1UL)
7772#define USB_EPINTSET_EPSET1_Msk (0x2UL)
7773#define USB_EPINTSET_EPSET2_Pos (2UL)
7774#define USB_EPINTSET_EPSET2_Msk (0x4UL)
7775#define USB_EPINTSET_EPSET3_Pos (3UL)
7776#define USB_EPINTSET_EPSET3_Msk (0x8UL)
7777#define USB_EPINTSET_EPSET4_Pos (4UL)
7778#define USB_EPINTSET_EPSET4_Msk (0x10UL)
7779#define USB_EPINTSET_EPSET5_Pos (5UL)
7780#define USB_EPINTSET_EPSET5_Msk (0x20UL)
7781#define USB_EPINTSET_EPSET6_Pos (6UL)
7782#define USB_EPINTSET_EPSET6_Msk (0x40UL)
7783#define USB_EPINTSET_EPSET7_Pos (7UL)
7784#define USB_EPINTSET_EPSET7_Msk (0x80UL)
7785#define USB_EPINTSET_EPSET8_Pos (8UL)
7786#define USB_EPINTSET_EPSET8_Msk (0x100UL)
7787#define USB_EPINTSET_EPSET9_Pos (9UL)
7788#define USB_EPINTSET_EPSET9_Msk (0x200UL)
7789#define USB_EPINTSET_EPSET10_Pos (10UL)
7790#define USB_EPINTSET_EPSET10_Msk (0x400UL)
7791#define USB_EPINTSET_EPSET11_Pos (11UL)
7792#define USB_EPINTSET_EPSET11_Msk (0x800UL)
7793#define USB_EPINTSET_EPSET12_Pos (12UL)
7794#define USB_EPINTSET_EPSET12_Msk (0x1000UL)
7795#define USB_EPINTSET_EPSET13_Pos (13UL)
7796#define USB_EPINTSET_EPSET13_Msk (0x2000UL)
7797#define USB_EPINTSET_EPSET14_Pos (14UL)
7798#define USB_EPINTSET_EPSET14_Msk (0x4000UL)
7799#define USB_EPINTSET_EPSET15_Pos (15UL)
7800#define USB_EPINTSET_EPSET15_Msk (0x8000UL)
7801#define USB_EPINTSET_EPSET16_Pos (16UL)
7802#define USB_EPINTSET_EPSET16_Msk (0x10000UL)
7803#define USB_EPINTSET_EPSET17_Pos (17UL)
7804#define USB_EPINTSET_EPSET17_Msk (0x20000UL)
7805#define USB_EPINTSET_EPSET18_Pos (18UL)
7806#define USB_EPINTSET_EPSET18_Msk (0x40000UL)
7807#define USB_EPINTSET_EPSET19_Pos (19UL)
7808#define USB_EPINTSET_EPSET19_Msk (0x80000UL)
7809#define USB_EPINTSET_EPSET20_Pos (20UL)
7810#define USB_EPINTSET_EPSET20_Msk (0x100000UL)
7811#define USB_EPINTSET_EPSET21_Pos (21UL)
7812#define USB_EPINTSET_EPSET21_Msk (0x200000UL)
7813#define USB_EPINTSET_EPSET22_Pos (22UL)
7814#define USB_EPINTSET_EPSET22_Msk (0x400000UL)
7815#define USB_EPINTSET_EPSET23_Pos (23UL)
7816#define USB_EPINTSET_EPSET23_Msk (0x800000UL)
7817#define USB_EPINTSET_EPSET24_Pos (24UL)
7818#define USB_EPINTSET_EPSET24_Msk (0x1000000UL)
7819#define USB_EPINTSET_EPSET25_Pos (25UL)
7820#define USB_EPINTSET_EPSET25_Msk (0x2000000UL)
7821#define USB_EPINTSET_EPSET26_Pos (26UL)
7822#define USB_EPINTSET_EPSET26_Msk (0x4000000UL)
7823#define USB_EPINTSET_EPSET27_Pos (27UL)
7824#define USB_EPINTSET_EPSET27_Msk (0x8000000UL)
7825#define USB_EPINTSET_EPSET28_Pos (28UL)
7826#define USB_EPINTSET_EPSET28_Msk (0x10000000UL)
7827#define USB_EPINTSET_EPSET29_Pos (29UL)
7828#define USB_EPINTSET_EPSET29_Msk (0x20000000UL)
7829#define USB_EPINTSET_EPSET30_Pos (30UL)
7830#define USB_EPINTSET_EPSET30_Msk (0x40000000UL)
7831#define USB_EPINTSET_EPSET31_Pos (31UL)
7832#define USB_EPINTSET_EPSET31_Msk (0x80000000UL)
7833/* ======================================================= EPINTPRI ======================================================== */
7834#define USB_EPINTPRI_EPPRI0_Pos (0UL)
7835#define USB_EPINTPRI_EPPRI0_Msk (0x1UL)
7836#define USB_EPINTPRI_EPPRI1_Pos (1UL)
7837#define USB_EPINTPRI_EPPRI1_Msk (0x2UL)
7838#define USB_EPINTPRI_EPPRI2_Pos (2UL)
7839#define USB_EPINTPRI_EPPRI2_Msk (0x4UL)
7840#define USB_EPINTPRI_EPPRI3_Pos (3UL)
7841#define USB_EPINTPRI_EPPRI3_Msk (0x8UL)
7842#define USB_EPINTPRI_EPPRI4_Pos (4UL)
7843#define USB_EPINTPRI_EPPRI4_Msk (0x10UL)
7844#define USB_EPINTPRI_EPPRI5_Pos (5UL)
7845#define USB_EPINTPRI_EPPRI5_Msk (0x20UL)
7846#define USB_EPINTPRI_EPPRI6_Pos (6UL)
7847#define USB_EPINTPRI_EPPRI6_Msk (0x40UL)
7848#define USB_EPINTPRI_EPPRI7_Pos (7UL)
7849#define USB_EPINTPRI_EPPRI7_Msk (0x80UL)
7850#define USB_EPINTPRI_EPPRI8_Pos (8UL)
7851#define USB_EPINTPRI_EPPRI8_Msk (0x100UL)
7852#define USB_EPINTPRI_EPPRI9_Pos (9UL)
7853#define USB_EPINTPRI_EPPRI9_Msk (0x200UL)
7854#define USB_EPINTPRI_EPPRI10_Pos (10UL)
7855#define USB_EPINTPRI_EPPRI10_Msk (0x400UL)
7856#define USB_EPINTPRI_EPPRI11_Pos (11UL)
7857#define USB_EPINTPRI_EPPRI11_Msk (0x800UL)
7858#define USB_EPINTPRI_EPPRI12_Pos (12UL)
7859#define USB_EPINTPRI_EPPRI12_Msk (0x1000UL)
7860#define USB_EPINTPRI_EPPRI13_Pos (13UL)
7861#define USB_EPINTPRI_EPPRI13_Msk (0x2000UL)
7862#define USB_EPINTPRI_EPPRI14_Pos (14UL)
7863#define USB_EPINTPRI_EPPRI14_Msk (0x4000UL)
7864#define USB_EPINTPRI_EPPRI15_Pos (15UL)
7865#define USB_EPINTPRI_EPPRI15_Msk (0x8000UL)
7866#define USB_EPINTPRI_EPPRI16_Pos (16UL)
7867#define USB_EPINTPRI_EPPRI16_Msk (0x10000UL)
7868#define USB_EPINTPRI_EPPRI17_Pos (17UL)
7869#define USB_EPINTPRI_EPPRI17_Msk (0x20000UL)
7870#define USB_EPINTPRI_EPPRI18_Pos (18UL)
7871#define USB_EPINTPRI_EPPRI18_Msk (0x40000UL)
7872#define USB_EPINTPRI_EPPRI19_Pos (19UL)
7873#define USB_EPINTPRI_EPPRI19_Msk (0x80000UL)
7874#define USB_EPINTPRI_EPPRI20_Pos (20UL)
7875#define USB_EPINTPRI_EPPRI20_Msk (0x100000UL)
7876#define USB_EPINTPRI_EPPRI21_Pos (21UL)
7877#define USB_EPINTPRI_EPPRI21_Msk (0x200000UL)
7878#define USB_EPINTPRI_EPPRI22_Pos (22UL)
7879#define USB_EPINTPRI_EPPRI22_Msk (0x400000UL)
7880#define USB_EPINTPRI_EPPRI23_Pos (23UL)
7881#define USB_EPINTPRI_EPPRI23_Msk (0x800000UL)
7882#define USB_EPINTPRI_EPPRI24_Pos (24UL)
7883#define USB_EPINTPRI_EPPRI24_Msk (0x1000000UL)
7884#define USB_EPINTPRI_EPPRI25_Pos (25UL)
7885#define USB_EPINTPRI_EPPRI25_Msk (0x2000000UL)
7886#define USB_EPINTPRI_EPPRI26_Pos (26UL)
7887#define USB_EPINTPRI_EPPRI26_Msk (0x4000000UL)
7888#define USB_EPINTPRI_EPPRI27_Pos (27UL)
7889#define USB_EPINTPRI_EPPRI27_Msk (0x8000000UL)
7890#define USB_EPINTPRI_EPPRI28_Pos (28UL)
7891#define USB_EPINTPRI_EPPRI28_Msk (0x10000000UL)
7892#define USB_EPINTPRI_EPPRI29_Pos (29UL)
7893#define USB_EPINTPRI_EPPRI29_Msk (0x20000000UL)
7894#define USB_EPINTPRI_EPPRI30_Pos (30UL)
7895#define USB_EPINTPRI_EPPRI30_Msk (0x40000000UL)
7896#define USB_EPINTPRI_EPPRI31_Pos (31UL)
7897#define USB_EPINTPRI_EPPRI31_Msk (0x80000000UL)
7898/* ========================================================= REEP ========================================================== */
7899#define USB_REEP_EPR0_Pos (0UL)
7900#define USB_REEP_EPR0_Msk (0x1UL)
7901#define USB_REEP_EPR1_Pos (1UL)
7902#define USB_REEP_EPR1_Msk (0x2UL)
7903#define USB_REEP_EPR2_Pos (2UL)
7904#define USB_REEP_EPR2_Msk (0x4UL)
7905#define USB_REEP_EPR3_Pos (3UL)
7906#define USB_REEP_EPR3_Msk (0x8UL)
7907#define USB_REEP_EPR4_Pos (4UL)
7908#define USB_REEP_EPR4_Msk (0x10UL)
7909#define USB_REEP_EPR5_Pos (5UL)
7910#define USB_REEP_EPR5_Msk (0x20UL)
7911#define USB_REEP_EPR6_Pos (6UL)
7912#define USB_REEP_EPR6_Msk (0x40UL)
7913#define USB_REEP_EPR7_Pos (7UL)
7914#define USB_REEP_EPR7_Msk (0x80UL)
7915#define USB_REEP_EPR8_Pos (8UL)
7916#define USB_REEP_EPR8_Msk (0x100UL)
7917#define USB_REEP_EPR9_Pos (9UL)
7918#define USB_REEP_EPR9_Msk (0x200UL)
7919#define USB_REEP_EPR10_Pos (10UL)
7920#define USB_REEP_EPR10_Msk (0x400UL)
7921#define USB_REEP_EPR11_Pos (11UL)
7922#define USB_REEP_EPR11_Msk (0x800UL)
7923#define USB_REEP_EPR12_Pos (12UL)
7924#define USB_REEP_EPR12_Msk (0x1000UL)
7925#define USB_REEP_EPR13_Pos (13UL)
7926#define USB_REEP_EPR13_Msk (0x2000UL)
7927#define USB_REEP_EPR14_Pos (14UL)
7928#define USB_REEP_EPR14_Msk (0x4000UL)
7929#define USB_REEP_EPR15_Pos (15UL)
7930#define USB_REEP_EPR15_Msk (0x8000UL)
7931#define USB_REEP_EPR16_Pos (16UL)
7932#define USB_REEP_EPR16_Msk (0x10000UL)
7933#define USB_REEP_EPR17_Pos (17UL)
7934#define USB_REEP_EPR17_Msk (0x20000UL)
7935#define USB_REEP_EPR18_Pos (18UL)
7936#define USB_REEP_EPR18_Msk (0x40000UL)
7937#define USB_REEP_EPR19_Pos (19UL)
7938#define USB_REEP_EPR19_Msk (0x80000UL)
7939#define USB_REEP_EPR20_Pos (20UL)
7940#define USB_REEP_EPR20_Msk (0x100000UL)
7941#define USB_REEP_EPR21_Pos (21UL)
7942#define USB_REEP_EPR21_Msk (0x200000UL)
7943#define USB_REEP_EPR22_Pos (22UL)
7944#define USB_REEP_EPR22_Msk (0x400000UL)
7945#define USB_REEP_EPR23_Pos (23UL)
7946#define USB_REEP_EPR23_Msk (0x800000UL)
7947#define USB_REEP_EPR24_Pos (24UL)
7948#define USB_REEP_EPR24_Msk (0x1000000UL)
7949#define USB_REEP_EPR25_Pos (25UL)
7950#define USB_REEP_EPR25_Msk (0x2000000UL)
7951#define USB_REEP_EPR26_Pos (26UL)
7952#define USB_REEP_EPR26_Msk (0x4000000UL)
7953#define USB_REEP_EPR27_Pos (27UL)
7954#define USB_REEP_EPR27_Msk (0x8000000UL)
7955#define USB_REEP_EPR28_Pos (28UL)
7956#define USB_REEP_EPR28_Msk (0x10000000UL)
7957#define USB_REEP_EPR29_Pos (29UL)
7958#define USB_REEP_EPR29_Msk (0x20000000UL)
7959#define USB_REEP_EPR30_Pos (30UL)
7960#define USB_REEP_EPR30_Msk (0x40000000UL)
7961#define USB_REEP_EPR31_Pos (31UL)
7962#define USB_REEP_EPR31_Msk (0x80000000UL)
7963/* ========================================================= EPIND ========================================================= */
7964#define USB_EPIND_PHY_EP_Pos (0UL)
7965#define USB_EPIND_PHY_EP_Msk (0x1fUL)
7966/* ======================================================= MAXPSIZE ======================================================== */
7967#define USB_MAXPSIZE_MPS_Pos (0UL)
7968#define USB_MAXPSIZE_MPS_Msk (0x3ffUL)
7969/* ======================================================== DMARST ========================================================= */
7970#define USB_DMARST_EPRST0_Pos (0UL)
7971#define USB_DMARST_EPRST0_Msk (0x1UL)
7972#define USB_DMARST_EPRST1_Pos (1UL)
7973#define USB_DMARST_EPRST1_Msk (0x2UL)
7974#define USB_DMARST_EPRST2_Pos (2UL)
7975#define USB_DMARST_EPRST2_Msk (0x4UL)
7976#define USB_DMARST_EPRST3_Pos (3UL)
7977#define USB_DMARST_EPRST3_Msk (0x8UL)
7978#define USB_DMARST_EPRST4_Pos (4UL)
7979#define USB_DMARST_EPRST4_Msk (0x10UL)
7980#define USB_DMARST_EPRST5_Pos (5UL)
7981#define USB_DMARST_EPRST5_Msk (0x20UL)
7982#define USB_DMARST_EPRST6_Pos (6UL)
7983#define USB_DMARST_EPRST6_Msk (0x40UL)
7984#define USB_DMARST_EPRST7_Pos (7UL)
7985#define USB_DMARST_EPRST7_Msk (0x80UL)
7986#define USB_DMARST_EPRST8_Pos (8UL)
7987#define USB_DMARST_EPRST8_Msk (0x100UL)
7988#define USB_DMARST_EPRST9_Pos (9UL)
7989#define USB_DMARST_EPRST9_Msk (0x200UL)
7990#define USB_DMARST_EPRST10_Pos (10UL)
7991#define USB_DMARST_EPRST10_Msk (0x400UL)
7992#define USB_DMARST_EPRST11_Pos (11UL)
7993#define USB_DMARST_EPRST11_Msk (0x800UL)
7994#define USB_DMARST_EPRST12_Pos (12UL)
7995#define USB_DMARST_EPRST12_Msk (0x1000UL)
7996#define USB_DMARST_EPRST13_Pos (13UL)
7997#define USB_DMARST_EPRST13_Msk (0x2000UL)
7998#define USB_DMARST_EPRST14_Pos (14UL)
7999#define USB_DMARST_EPRST14_Msk (0x4000UL)
8000#define USB_DMARST_EPRST15_Pos (15UL)
8001#define USB_DMARST_EPRST15_Msk (0x8000UL)
8002#define USB_DMARST_EPRST16_Pos (16UL)
8003#define USB_DMARST_EPRST16_Msk (0x10000UL)
8004#define USB_DMARST_EPRST17_Pos (17UL)
8005#define USB_DMARST_EPRST17_Msk (0x20000UL)
8006#define USB_DMARST_EPRST18_Pos (18UL)
8007#define USB_DMARST_EPRST18_Msk (0x40000UL)
8008#define USB_DMARST_EPRST19_Pos (19UL)
8009#define USB_DMARST_EPRST19_Msk (0x80000UL)
8010#define USB_DMARST_EPRST20_Pos (20UL)
8011#define USB_DMARST_EPRST20_Msk (0x100000UL)
8012#define USB_DMARST_EPRST21_Pos (21UL)
8013#define USB_DMARST_EPRST21_Msk (0x200000UL)
8014#define USB_DMARST_EPRST22_Pos (22UL)
8015#define USB_DMARST_EPRST22_Msk (0x400000UL)
8016#define USB_DMARST_EPRST23_Pos (23UL)
8017#define USB_DMARST_EPRST23_Msk (0x800000UL)
8018#define USB_DMARST_EPRST24_Pos (24UL)
8019#define USB_DMARST_EPRST24_Msk (0x1000000UL)
8020#define USB_DMARST_EPRST25_Pos (25UL)
8021#define USB_DMARST_EPRST25_Msk (0x2000000UL)
8022#define USB_DMARST_EPRST26_Pos (26UL)
8023#define USB_DMARST_EPRST26_Msk (0x4000000UL)
8024#define USB_DMARST_EPRST27_Pos (27UL)
8025#define USB_DMARST_EPRST27_Msk (0x8000000UL)
8026#define USB_DMARST_EPRST28_Pos (28UL)
8027#define USB_DMARST_EPRST28_Msk (0x10000000UL)
8028#define USB_DMARST_EPRST29_Pos (29UL)
8029#define USB_DMARST_EPRST29_Msk (0x20000000UL)
8030#define USB_DMARST_EPRST30_Pos (30UL)
8031#define USB_DMARST_EPRST30_Msk (0x40000000UL)
8032#define USB_DMARST_EPRST31_Pos (31UL)
8033#define USB_DMARST_EPRST31_Msk (0x80000000UL)
8034/* ======================================================== DMARCLR ======================================================== */
8035#define USB_DMARCLR_EPRCLR0_Pos (0UL)
8036#define USB_DMARCLR_EPRCLR0_Msk (0x1UL)
8037#define USB_DMARCLR_EPRCLR1_Pos (1UL)
8038#define USB_DMARCLR_EPRCLR1_Msk (0x2UL)
8039#define USB_DMARCLR_EPRCLR2_Pos (2UL)
8040#define USB_DMARCLR_EPRCLR2_Msk (0x4UL)
8041#define USB_DMARCLR_EPRCLR3_Pos (3UL)
8042#define USB_DMARCLR_EPRCLR3_Msk (0x8UL)
8043#define USB_DMARCLR_EPRCLR4_Pos (4UL)
8044#define USB_DMARCLR_EPRCLR4_Msk (0x10UL)
8045#define USB_DMARCLR_EPRCLR5_Pos (5UL)
8046#define USB_DMARCLR_EPRCLR5_Msk (0x20UL)
8047#define USB_DMARCLR_EPRCLR6_Pos (6UL)
8048#define USB_DMARCLR_EPRCLR6_Msk (0x40UL)
8049#define USB_DMARCLR_EPRCLR7_Pos (7UL)
8050#define USB_DMARCLR_EPRCLR7_Msk (0x80UL)
8051#define USB_DMARCLR_EPRCLR8_Pos (8UL)
8052#define USB_DMARCLR_EPRCLR8_Msk (0x100UL)
8053#define USB_DMARCLR_EPRCLR9_Pos (9UL)
8054#define USB_DMARCLR_EPRCLR9_Msk (0x200UL)
8055#define USB_DMARCLR_EPRCLR10_Pos (10UL)
8056#define USB_DMARCLR_EPRCLR10_Msk (0x400UL)
8057#define USB_DMARCLR_EPRCLR11_Pos (11UL)
8058#define USB_DMARCLR_EPRCLR11_Msk (0x800UL)
8059#define USB_DMARCLR_EPRCLR12_Pos (12UL)
8060#define USB_DMARCLR_EPRCLR12_Msk (0x1000UL)
8061#define USB_DMARCLR_EPRCLR13_Pos (13UL)
8062#define USB_DMARCLR_EPRCLR13_Msk (0x2000UL)
8063#define USB_DMARCLR_EPRCLR14_Pos (14UL)
8064#define USB_DMARCLR_EPRCLR14_Msk (0x4000UL)
8065#define USB_DMARCLR_EPRCLR15_Pos (15UL)
8066#define USB_DMARCLR_EPRCLR15_Msk (0x8000UL)
8067#define USB_DMARCLR_EPRCLR16_Pos (16UL)
8068#define USB_DMARCLR_EPRCLR16_Msk (0x10000UL)
8069#define USB_DMARCLR_EPRCLR17_Pos (17UL)
8070#define USB_DMARCLR_EPRCLR17_Msk (0x20000UL)
8071#define USB_DMARCLR_EPRCLR18_Pos (18UL)
8072#define USB_DMARCLR_EPRCLR18_Msk (0x40000UL)
8073#define USB_DMARCLR_EPRCLR19_Pos (19UL)
8074#define USB_DMARCLR_EPRCLR19_Msk (0x80000UL)
8075#define USB_DMARCLR_EPRCLR20_Pos (20UL)
8076#define USB_DMARCLR_EPRCLR20_Msk (0x100000UL)
8077#define USB_DMARCLR_EPRCLR21_Pos (21UL)
8078#define USB_DMARCLR_EPRCLR21_Msk (0x200000UL)
8079#define USB_DMARCLR_EPRCLR22_Pos (22UL)
8080#define USB_DMARCLR_EPRCLR22_Msk (0x400000UL)
8081#define USB_DMARCLR_EPRCLR23_Pos (23UL)
8082#define USB_DMARCLR_EPRCLR23_Msk (0x800000UL)
8083#define USB_DMARCLR_EPRCLR24_Pos (24UL)
8084#define USB_DMARCLR_EPRCLR24_Msk (0x1000000UL)
8085#define USB_DMARCLR_EPRCLR25_Pos (25UL)
8086#define USB_DMARCLR_EPRCLR25_Msk (0x2000000UL)
8087#define USB_DMARCLR_EPRCLR26_Pos (26UL)
8088#define USB_DMARCLR_EPRCLR26_Msk (0x4000000UL)
8089#define USB_DMARCLR_EPRCLR27_Pos (27UL)
8090#define USB_DMARCLR_EPRCLR27_Msk (0x8000000UL)
8091#define USB_DMARCLR_EPRCLR28_Pos (28UL)
8092#define USB_DMARCLR_EPRCLR28_Msk (0x10000000UL)
8093#define USB_DMARCLR_EPRCLR29_Pos (29UL)
8094#define USB_DMARCLR_EPRCLR29_Msk (0x20000000UL)
8095#define USB_DMARCLR_EPRCLR30_Pos (30UL)
8096#define USB_DMARCLR_EPRCLR30_Msk (0x40000000UL)
8097#define USB_DMARCLR_EPRCLR31_Pos (31UL)
8098#define USB_DMARCLR_EPRCLR31_Msk (0x80000000UL)
8099/* ======================================================== DMARSET ======================================================== */
8100#define USB_DMARSET_EPRSET0_Pos (0UL)
8101#define USB_DMARSET_EPRSET0_Msk (0x1UL)
8102#define USB_DMARSET_EPRSET1_Pos (1UL)
8103#define USB_DMARSET_EPRSET1_Msk (0x2UL)
8104#define USB_DMARSET_EPRSET2_Pos (2UL)
8105#define USB_DMARSET_EPRSET2_Msk (0x4UL)
8106#define USB_DMARSET_EPRSET3_Pos (3UL)
8107#define USB_DMARSET_EPRSET3_Msk (0x8UL)
8108#define USB_DMARSET_EPRSET4_Pos (4UL)
8109#define USB_DMARSET_EPRSET4_Msk (0x10UL)
8110#define USB_DMARSET_EPRSET5_Pos (5UL)
8111#define USB_DMARSET_EPRSET5_Msk (0x20UL)
8112#define USB_DMARSET_EPRSET6_Pos (6UL)
8113#define USB_DMARSET_EPRSET6_Msk (0x40UL)
8114#define USB_DMARSET_EPRSET7_Pos (7UL)
8115#define USB_DMARSET_EPRSET7_Msk (0x80UL)
8116#define USB_DMARSET_EPRSET8_Pos (8UL)
8117#define USB_DMARSET_EPRSET8_Msk (0x100UL)
8118#define USB_DMARSET_EPRSET9_Pos (9UL)
8119#define USB_DMARSET_EPRSET9_Msk (0x200UL)
8120#define USB_DMARSET_EPRSET10_Pos (10UL)
8121#define USB_DMARSET_EPRSET10_Msk (0x400UL)
8122#define USB_DMARSET_EPRSET11_Pos (11UL)
8123#define USB_DMARSET_EPRSET11_Msk (0x800UL)
8124#define USB_DMARSET_EPRSET12_Pos (12UL)
8125#define USB_DMARSET_EPRSET12_Msk (0x1000UL)
8126#define USB_DMARSET_EPRSET13_Pos (13UL)
8127#define USB_DMARSET_EPRSET13_Msk (0x2000UL)
8128#define USB_DMARSET_EPRSET14_Pos (14UL)
8129#define USB_DMARSET_EPRSET14_Msk (0x4000UL)
8130#define USB_DMARSET_EPRSET15_Pos (15UL)
8131#define USB_DMARSET_EPRSET15_Msk (0x8000UL)
8132#define USB_DMARSET_EPRSET16_Pos (16UL)
8133#define USB_DMARSET_EPRSET16_Msk (0x10000UL)
8134#define USB_DMARSET_EPRSET17_Pos (17UL)
8135#define USB_DMARSET_EPRSET17_Msk (0x20000UL)
8136#define USB_DMARSET_EPRSET18_Pos (18UL)
8137#define USB_DMARSET_EPRSET18_Msk (0x40000UL)
8138#define USB_DMARSET_EPRSET19_Pos (19UL)
8139#define USB_DMARSET_EPRSET19_Msk (0x80000UL)
8140#define USB_DMARSET_EPRSET20_Pos (20UL)
8141#define USB_DMARSET_EPRSET20_Msk (0x100000UL)
8142#define USB_DMARSET_EPRSET21_Pos (21UL)
8143#define USB_DMARSET_EPRSET21_Msk (0x200000UL)
8144#define USB_DMARSET_EPRSET22_Pos (22UL)
8145#define USB_DMARSET_EPRSET22_Msk (0x400000UL)
8146#define USB_DMARSET_EPRSET23_Pos (23UL)
8147#define USB_DMARSET_EPRSET23_Msk (0x800000UL)
8148#define USB_DMARSET_EPRSET24_Pos (24UL)
8149#define USB_DMARSET_EPRSET24_Msk (0x1000000UL)
8150#define USB_DMARSET_EPRSET25_Pos (25UL)
8151#define USB_DMARSET_EPRSET25_Msk (0x2000000UL)
8152#define USB_DMARSET_EPRSET26_Pos (26UL)
8153#define USB_DMARSET_EPRSET26_Msk (0x4000000UL)
8154#define USB_DMARSET_EPRSET27_Pos (27UL)
8155#define USB_DMARSET_EPRSET27_Msk (0x8000000UL)
8156#define USB_DMARSET_EPRSET28_Pos (28UL)
8157#define USB_DMARSET_EPRSET28_Msk (0x10000000UL)
8158#define USB_DMARSET_EPRSET29_Pos (29UL)
8159#define USB_DMARSET_EPRSET29_Msk (0x20000000UL)
8160#define USB_DMARSET_EPRSET30_Pos (30UL)
8161#define USB_DMARSET_EPRSET30_Msk (0x40000000UL)
8162#define USB_DMARSET_EPRSET31_Pos (31UL)
8163#define USB_DMARSET_EPRSET31_Msk (0x80000000UL)
8164/* ========================================================= UDCAH ========================================================= */
8165#define USB_UDCAH_UDCA_ADDR_Pos (7UL)
8166#define USB_UDCAH_UDCA_ADDR_Msk (0xffffff80UL)
8167/* ======================================================== EPDMAST ======================================================== */
8168#define USB_EPDMAST_EP_DMA_ST0_Pos (0UL)
8169#define USB_EPDMAST_EP_DMA_ST0_Msk (0x1UL)
8170#define USB_EPDMAST_EP_DMA_ST1_Pos (1UL)
8171#define USB_EPDMAST_EP_DMA_ST1_Msk (0x2UL)
8172#define USB_EPDMAST_EP_DMA_ST2_Pos (2UL)
8173#define USB_EPDMAST_EP_DMA_ST2_Msk (0x4UL)
8174#define USB_EPDMAST_EP_DMA_ST3_Pos (3UL)
8175#define USB_EPDMAST_EP_DMA_ST3_Msk (0x8UL)
8176#define USB_EPDMAST_EP_DMA_ST4_Pos (4UL)
8177#define USB_EPDMAST_EP_DMA_ST4_Msk (0x10UL)
8178#define USB_EPDMAST_EP_DMA_ST5_Pos (5UL)
8179#define USB_EPDMAST_EP_DMA_ST5_Msk (0x20UL)
8180#define USB_EPDMAST_EP_DMA_ST6_Pos (6UL)
8181#define USB_EPDMAST_EP_DMA_ST6_Msk (0x40UL)
8182#define USB_EPDMAST_EP_DMA_ST7_Pos (7UL)
8183#define USB_EPDMAST_EP_DMA_ST7_Msk (0x80UL)
8184#define USB_EPDMAST_EP_DMA_ST8_Pos (8UL)
8185#define USB_EPDMAST_EP_DMA_ST8_Msk (0x100UL)
8186#define USB_EPDMAST_EP_DMA_ST9_Pos (9UL)
8187#define USB_EPDMAST_EP_DMA_ST9_Msk (0x200UL)
8188#define USB_EPDMAST_EP_DMA_ST10_Pos (10UL)
8189#define USB_EPDMAST_EP_DMA_ST10_Msk (0x400UL)
8190#define USB_EPDMAST_EP_DMA_ST11_Pos (11UL)
8191#define USB_EPDMAST_EP_DMA_ST11_Msk (0x800UL)
8192#define USB_EPDMAST_EP_DMA_ST12_Pos (12UL)
8193#define USB_EPDMAST_EP_DMA_ST12_Msk (0x1000UL)
8194#define USB_EPDMAST_EP_DMA_ST13_Pos (13UL)
8195#define USB_EPDMAST_EP_DMA_ST13_Msk (0x2000UL)
8196#define USB_EPDMAST_EP_DMA_ST14_Pos (14UL)
8197#define USB_EPDMAST_EP_DMA_ST14_Msk (0x4000UL)
8198#define USB_EPDMAST_EP_DMA_ST15_Pos (15UL)
8199#define USB_EPDMAST_EP_DMA_ST15_Msk (0x8000UL)
8200#define USB_EPDMAST_EP_DMA_ST16_Pos (16UL)
8201#define USB_EPDMAST_EP_DMA_ST16_Msk (0x10000UL)
8202#define USB_EPDMAST_EP_DMA_ST17_Pos (17UL)
8203#define USB_EPDMAST_EP_DMA_ST17_Msk (0x20000UL)
8204#define USB_EPDMAST_EP_DMA_ST18_Pos (18UL)
8205#define USB_EPDMAST_EP_DMA_ST18_Msk (0x40000UL)
8206#define USB_EPDMAST_EP_DMA_ST19_Pos (19UL)
8207#define USB_EPDMAST_EP_DMA_ST19_Msk (0x80000UL)
8208#define USB_EPDMAST_EP_DMA_ST20_Pos (20UL)
8209#define USB_EPDMAST_EP_DMA_ST20_Msk (0x100000UL)
8210#define USB_EPDMAST_EP_DMA_ST21_Pos (21UL)
8211#define USB_EPDMAST_EP_DMA_ST21_Msk (0x200000UL)
8212#define USB_EPDMAST_EP_DMA_ST22_Pos (22UL)
8213#define USB_EPDMAST_EP_DMA_ST22_Msk (0x400000UL)
8214#define USB_EPDMAST_EP_DMA_ST23_Pos (23UL)
8215#define USB_EPDMAST_EP_DMA_ST23_Msk (0x800000UL)
8216#define USB_EPDMAST_EP_DMA_ST24_Pos (24UL)
8217#define USB_EPDMAST_EP_DMA_ST24_Msk (0x1000000UL)
8218#define USB_EPDMAST_EP_DMA_ST25_Pos (25UL)
8219#define USB_EPDMAST_EP_DMA_ST25_Msk (0x2000000UL)
8220#define USB_EPDMAST_EP_DMA_ST26_Pos (26UL)
8221#define USB_EPDMAST_EP_DMA_ST26_Msk (0x4000000UL)
8222#define USB_EPDMAST_EP_DMA_ST27_Pos (27UL)
8223#define USB_EPDMAST_EP_DMA_ST27_Msk (0x8000000UL)
8224#define USB_EPDMAST_EP_DMA_ST28_Pos (28UL)
8225#define USB_EPDMAST_EP_DMA_ST28_Msk (0x10000000UL)
8226#define USB_EPDMAST_EP_DMA_ST29_Pos (29UL)
8227#define USB_EPDMAST_EP_DMA_ST29_Msk (0x20000000UL)
8228#define USB_EPDMAST_EP_DMA_ST30_Pos (30UL)
8229#define USB_EPDMAST_EP_DMA_ST30_Msk (0x40000000UL)
8230#define USB_EPDMAST_EP_DMA_ST31_Pos (31UL)
8231#define USB_EPDMAST_EP_DMA_ST31_Msk (0x80000000UL)
8232/* ======================================================== EPDMAEN ======================================================== */
8233#define USB_EPDMAEN_EP_DMA_EN0_Pos (0UL)
8234#define USB_EPDMAEN_EP_DMA_EN0_Msk (0x1UL)
8235#define USB_EPDMAEN_EP_DMA_EN1_Pos (1UL)
8236#define USB_EPDMAEN_EP_DMA_EN1_Msk (0x2UL)
8237#define USB_EPDMAEN_EP_DMA_EN_Pos (2UL)
8238#define USB_EPDMAEN_EP_DMA_EN_Msk (0xfffffffcUL)
8239/* ======================================================= EPDMADIS ======================================================== */
8240#define USB_EPDMADIS_EP_DMA_DIS0_Pos (0UL)
8241#define USB_EPDMADIS_EP_DMA_DIS0_Msk (0x1UL)
8242#define USB_EPDMADIS_EP_DMA_DIS1_Pos (1UL)
8243#define USB_EPDMADIS_EP_DMA_DIS1_Msk (0x2UL)
8244#define USB_EPDMADIS_EP_DMA_DIS2_Pos (2UL)
8245#define USB_EPDMADIS_EP_DMA_DIS2_Msk (0x4UL)
8246#define USB_EPDMADIS_EP_DMA_DIS3_Pos (3UL)
8247#define USB_EPDMADIS_EP_DMA_DIS3_Msk (0x8UL)
8248#define USB_EPDMADIS_EP_DMA_DIS4_Pos (4UL)
8249#define USB_EPDMADIS_EP_DMA_DIS4_Msk (0x10UL)
8250#define USB_EPDMADIS_EP_DMA_DIS5_Pos (5UL)
8251#define USB_EPDMADIS_EP_DMA_DIS5_Msk (0x20UL)
8252#define USB_EPDMADIS_EP_DMA_DIS6_Pos (6UL)
8253#define USB_EPDMADIS_EP_DMA_DIS6_Msk (0x40UL)
8254#define USB_EPDMADIS_EP_DMA_DIS7_Pos (7UL)
8255#define USB_EPDMADIS_EP_DMA_DIS7_Msk (0x80UL)
8256#define USB_EPDMADIS_EP_DMA_DIS8_Pos (8UL)
8257#define USB_EPDMADIS_EP_DMA_DIS8_Msk (0x100UL)
8258#define USB_EPDMADIS_EP_DMA_DIS9_Pos (9UL)
8259#define USB_EPDMADIS_EP_DMA_DIS9_Msk (0x200UL)
8260#define USB_EPDMADIS_EP_DMA_DIS10_Pos (10UL)
8261#define USB_EPDMADIS_EP_DMA_DIS10_Msk (0x400UL)
8262#define USB_EPDMADIS_EP_DMA_DIS11_Pos (11UL)
8263#define USB_EPDMADIS_EP_DMA_DIS11_Msk (0x800UL)
8264#define USB_EPDMADIS_EP_DMA_DIS12_Pos (12UL)
8265#define USB_EPDMADIS_EP_DMA_DIS12_Msk (0x1000UL)
8266#define USB_EPDMADIS_EP_DMA_DIS13_Pos (13UL)
8267#define USB_EPDMADIS_EP_DMA_DIS13_Msk (0x2000UL)
8268#define USB_EPDMADIS_EP_DMA_DIS14_Pos (14UL)
8269#define USB_EPDMADIS_EP_DMA_DIS14_Msk (0x4000UL)
8270#define USB_EPDMADIS_EP_DMA_DIS15_Pos (15UL)
8271#define USB_EPDMADIS_EP_DMA_DIS15_Msk (0x8000UL)
8272#define USB_EPDMADIS_EP_DMA_DIS16_Pos (16UL)
8273#define USB_EPDMADIS_EP_DMA_DIS16_Msk (0x10000UL)
8274#define USB_EPDMADIS_EP_DMA_DIS17_Pos (17UL)
8275#define USB_EPDMADIS_EP_DMA_DIS17_Msk (0x20000UL)
8276#define USB_EPDMADIS_EP_DMA_DIS18_Pos (18UL)
8277#define USB_EPDMADIS_EP_DMA_DIS18_Msk (0x40000UL)
8278#define USB_EPDMADIS_EP_DMA_DIS19_Pos (19UL)
8279#define USB_EPDMADIS_EP_DMA_DIS19_Msk (0x80000UL)
8280#define USB_EPDMADIS_EP_DMA_DIS20_Pos (20UL)
8281#define USB_EPDMADIS_EP_DMA_DIS20_Msk (0x100000UL)
8282#define USB_EPDMADIS_EP_DMA_DIS21_Pos (21UL)
8283#define USB_EPDMADIS_EP_DMA_DIS21_Msk (0x200000UL)
8284#define USB_EPDMADIS_EP_DMA_DIS22_Pos (22UL)
8285#define USB_EPDMADIS_EP_DMA_DIS22_Msk (0x400000UL)
8286#define USB_EPDMADIS_EP_DMA_DIS23_Pos (23UL)
8287#define USB_EPDMADIS_EP_DMA_DIS23_Msk (0x800000UL)
8288#define USB_EPDMADIS_EP_DMA_DIS24_Pos (24UL)
8289#define USB_EPDMADIS_EP_DMA_DIS24_Msk (0x1000000UL)
8290#define USB_EPDMADIS_EP_DMA_DIS25_Pos (25UL)
8291#define USB_EPDMADIS_EP_DMA_DIS25_Msk (0x2000000UL)
8292#define USB_EPDMADIS_EP_DMA_DIS26_Pos (26UL)
8293#define USB_EPDMADIS_EP_DMA_DIS26_Msk (0x4000000UL)
8294#define USB_EPDMADIS_EP_DMA_DIS27_Pos (27UL)
8295#define USB_EPDMADIS_EP_DMA_DIS27_Msk (0x8000000UL)
8296#define USB_EPDMADIS_EP_DMA_DIS28_Pos (28UL)
8297#define USB_EPDMADIS_EP_DMA_DIS28_Msk (0x10000000UL)
8298#define USB_EPDMADIS_EP_DMA_DIS29_Pos (29UL)
8299#define USB_EPDMADIS_EP_DMA_DIS29_Msk (0x20000000UL)
8300#define USB_EPDMADIS_EP_DMA_DIS30_Pos (30UL)
8301#define USB_EPDMADIS_EP_DMA_DIS30_Msk (0x40000000UL)
8302#define USB_EPDMADIS_EP_DMA_DIS31_Pos (31UL)
8303#define USB_EPDMADIS_EP_DMA_DIS31_Msk (0x80000000UL)
8304/* ======================================================= DMAINTST ======================================================== */
8305#define USB_DMAINTST_EOT_Pos (0UL)
8306#define USB_DMAINTST_EOT_Msk (0x1UL)
8307#define USB_DMAINTST_NDDR_Pos (1UL)
8308#define USB_DMAINTST_NDDR_Msk (0x2UL)
8309#define USB_DMAINTST_ERR_Pos (2UL)
8310#define USB_DMAINTST_ERR_Msk (0x4UL)
8311/* ======================================================= DMAINTEN ======================================================== */
8312#define USB_DMAINTEN_EOT_Pos (0UL)
8313#define USB_DMAINTEN_EOT_Msk (0x1UL)
8314#define USB_DMAINTEN_NDDR_Pos (1UL)
8315#define USB_DMAINTEN_NDDR_Msk (0x2UL)
8316#define USB_DMAINTEN_ERR_Pos (2UL)
8317#define USB_DMAINTEN_ERR_Msk (0x4UL)
8318/* ======================================================= EOTINTST ======================================================== */
8319#define USB_EOTINTST_EPTXINTST0_Pos (0UL)
8320#define USB_EOTINTST_EPTXINTST0_Msk (0x1UL)
8321#define USB_EOTINTST_EPTXINTST1_Pos (1UL)
8322#define USB_EOTINTST_EPTXINTST1_Msk (0x2UL)
8323#define USB_EOTINTST_EPTXINTST2_Pos (2UL)
8324#define USB_EOTINTST_EPTXINTST2_Msk (0x4UL)
8325#define USB_EOTINTST_EPTXINTST3_Pos (3UL)
8326#define USB_EOTINTST_EPTXINTST3_Msk (0x8UL)
8327#define USB_EOTINTST_EPTXINTST4_Pos (4UL)
8328#define USB_EOTINTST_EPTXINTST4_Msk (0x10UL)
8329#define USB_EOTINTST_EPTXINTST5_Pos (5UL)
8330#define USB_EOTINTST_EPTXINTST5_Msk (0x20UL)
8331#define USB_EOTINTST_EPTXINTST6_Pos (6UL)
8332#define USB_EOTINTST_EPTXINTST6_Msk (0x40UL)
8333#define USB_EOTINTST_EPTXINTST7_Pos (7UL)
8334#define USB_EOTINTST_EPTXINTST7_Msk (0x80UL)
8335#define USB_EOTINTST_EPTXINTST8_Pos (8UL)
8336#define USB_EOTINTST_EPTXINTST8_Msk (0x100UL)
8337#define USB_EOTINTST_EPTXINTST9_Pos (9UL)
8338#define USB_EOTINTST_EPTXINTST9_Msk (0x200UL)
8339#define USB_EOTINTST_EPTXINTST10_Pos (10UL)
8340#define USB_EOTINTST_EPTXINTST10_Msk (0x400UL)
8341#define USB_EOTINTST_EPTXINTST11_Pos (11UL)
8342#define USB_EOTINTST_EPTXINTST11_Msk (0x800UL)
8343#define USB_EOTINTST_EPTXINTST12_Pos (12UL)
8344#define USB_EOTINTST_EPTXINTST12_Msk (0x1000UL)
8345#define USB_EOTINTST_EPTXINTST13_Pos (13UL)
8346#define USB_EOTINTST_EPTXINTST13_Msk (0x2000UL)
8347#define USB_EOTINTST_EPTXINTST14_Pos (14UL)
8348#define USB_EOTINTST_EPTXINTST14_Msk (0x4000UL)
8349#define USB_EOTINTST_EPTXINTST15_Pos (15UL)
8350#define USB_EOTINTST_EPTXINTST15_Msk (0x8000UL)
8351#define USB_EOTINTST_EPTXINTST16_Pos (16UL)
8352#define USB_EOTINTST_EPTXINTST16_Msk (0x10000UL)
8353#define USB_EOTINTST_EPTXINTST17_Pos (17UL)
8354#define USB_EOTINTST_EPTXINTST17_Msk (0x20000UL)
8355#define USB_EOTINTST_EPTXINTST18_Pos (18UL)
8356#define USB_EOTINTST_EPTXINTST18_Msk (0x40000UL)
8357#define USB_EOTINTST_EPTXINTST19_Pos (19UL)
8358#define USB_EOTINTST_EPTXINTST19_Msk (0x80000UL)
8359#define USB_EOTINTST_EPTXINTST20_Pos (20UL)
8360#define USB_EOTINTST_EPTXINTST20_Msk (0x100000UL)
8361#define USB_EOTINTST_EPTXINTST21_Pos (21UL)
8362#define USB_EOTINTST_EPTXINTST21_Msk (0x200000UL)
8363#define USB_EOTINTST_EPTXINTST22_Pos (22UL)
8364#define USB_EOTINTST_EPTXINTST22_Msk (0x400000UL)
8365#define USB_EOTINTST_EPTXINTST23_Pos (23UL)
8366#define USB_EOTINTST_EPTXINTST23_Msk (0x800000UL)
8367#define USB_EOTINTST_EPTXINTST24_Pos (24UL)
8368#define USB_EOTINTST_EPTXINTST24_Msk (0x1000000UL)
8369#define USB_EOTINTST_EPTXINTST25_Pos (25UL)
8370#define USB_EOTINTST_EPTXINTST25_Msk (0x2000000UL)
8371#define USB_EOTINTST_EPTXINTST26_Pos (26UL)
8372#define USB_EOTINTST_EPTXINTST26_Msk (0x4000000UL)
8373#define USB_EOTINTST_EPTXINTST27_Pos (27UL)
8374#define USB_EOTINTST_EPTXINTST27_Msk (0x8000000UL)
8375#define USB_EOTINTST_EPTXINTST28_Pos (28UL)
8376#define USB_EOTINTST_EPTXINTST28_Msk (0x10000000UL)
8377#define USB_EOTINTST_EPTXINTST29_Pos (29UL)
8378#define USB_EOTINTST_EPTXINTST29_Msk (0x20000000UL)
8379#define USB_EOTINTST_EPTXINTST30_Pos (30UL)
8380#define USB_EOTINTST_EPTXINTST30_Msk (0x40000000UL)
8381#define USB_EOTINTST_EPTXINTST31_Pos (31UL)
8382#define USB_EOTINTST_EPTXINTST31_Msk (0x80000000UL)
8383/* ======================================================= EOTINTCLR ======================================================= */
8384#define USB_EOTINTCLR_EPTXINTCLR0_Pos (0UL)
8385#define USB_EOTINTCLR_EPTXINTCLR0_Msk (0x1UL)
8386#define USB_EOTINTCLR_EPTXINTCLR1_Pos (1UL)
8387#define USB_EOTINTCLR_EPTXINTCLR1_Msk (0x2UL)
8388#define USB_EOTINTCLR_EPTXINTCLR2_Pos (2UL)
8389#define USB_EOTINTCLR_EPTXINTCLR2_Msk (0x4UL)
8390#define USB_EOTINTCLR_EPTXINTCLR3_Pos (3UL)
8391#define USB_EOTINTCLR_EPTXINTCLR3_Msk (0x8UL)
8392#define USB_EOTINTCLR_EPTXINTCLR4_Pos (4UL)
8393#define USB_EOTINTCLR_EPTXINTCLR4_Msk (0x10UL)
8394#define USB_EOTINTCLR_EPTXINTCLR5_Pos (5UL)
8395#define USB_EOTINTCLR_EPTXINTCLR5_Msk (0x20UL)
8396#define USB_EOTINTCLR_EPTXINTCLR6_Pos (6UL)
8397#define USB_EOTINTCLR_EPTXINTCLR6_Msk (0x40UL)
8398#define USB_EOTINTCLR_EPTXINTCLR7_Pos (7UL)
8399#define USB_EOTINTCLR_EPTXINTCLR7_Msk (0x80UL)
8400#define USB_EOTINTCLR_EPTXINTCLR8_Pos (8UL)
8401#define USB_EOTINTCLR_EPTXINTCLR8_Msk (0x100UL)
8402#define USB_EOTINTCLR_EPTXINTCLR9_Pos (9UL)
8403#define USB_EOTINTCLR_EPTXINTCLR9_Msk (0x200UL)
8404#define USB_EOTINTCLR_EPTXINTCLR10_Pos (10UL)
8405#define USB_EOTINTCLR_EPTXINTCLR10_Msk (0x400UL)
8406#define USB_EOTINTCLR_EPTXINTCLR11_Pos (11UL)
8407#define USB_EOTINTCLR_EPTXINTCLR11_Msk (0x800UL)
8408#define USB_EOTINTCLR_EPTXINTCLR12_Pos (12UL)
8409#define USB_EOTINTCLR_EPTXINTCLR12_Msk (0x1000UL)
8410#define USB_EOTINTCLR_EPTXINTCLR13_Pos (13UL)
8411#define USB_EOTINTCLR_EPTXINTCLR13_Msk (0x2000UL)
8412#define USB_EOTINTCLR_EPTXINTCLR14_Pos (14UL)
8413#define USB_EOTINTCLR_EPTXINTCLR14_Msk (0x4000UL)
8414#define USB_EOTINTCLR_EPTXINTCLR15_Pos (15UL)
8415#define USB_EOTINTCLR_EPTXINTCLR15_Msk (0x8000UL)
8416#define USB_EOTINTCLR_EPTXINTCLR16_Pos (16UL)
8417#define USB_EOTINTCLR_EPTXINTCLR16_Msk (0x10000UL)
8418#define USB_EOTINTCLR_EPTXINTCLR17_Pos (17UL)
8419#define USB_EOTINTCLR_EPTXINTCLR17_Msk (0x20000UL)
8420#define USB_EOTINTCLR_EPTXINTCLR18_Pos (18UL)
8421#define USB_EOTINTCLR_EPTXINTCLR18_Msk (0x40000UL)
8422#define USB_EOTINTCLR_EPTXINTCLR19_Pos (19UL)
8423#define USB_EOTINTCLR_EPTXINTCLR19_Msk (0x80000UL)
8424#define USB_EOTINTCLR_EPTXINTCLR20_Pos (20UL)
8425#define USB_EOTINTCLR_EPTXINTCLR20_Msk (0x100000UL)
8426#define USB_EOTINTCLR_EPTXINTCLR21_Pos (21UL)
8427#define USB_EOTINTCLR_EPTXINTCLR21_Msk (0x200000UL)
8428#define USB_EOTINTCLR_EPTXINTCLR22_Pos (22UL)
8429#define USB_EOTINTCLR_EPTXINTCLR22_Msk (0x400000UL)
8430#define USB_EOTINTCLR_EPTXINTCLR23_Pos (23UL)
8431#define USB_EOTINTCLR_EPTXINTCLR23_Msk (0x800000UL)
8432#define USB_EOTINTCLR_EPTXINTCLR24_Pos (24UL)
8433#define USB_EOTINTCLR_EPTXINTCLR24_Msk (0x1000000UL)
8434#define USB_EOTINTCLR_EPTXINTCLR25_Pos (25UL)
8435#define USB_EOTINTCLR_EPTXINTCLR25_Msk (0x2000000UL)
8436#define USB_EOTINTCLR_EPTXINTCLR26_Pos (26UL)
8437#define USB_EOTINTCLR_EPTXINTCLR26_Msk (0x4000000UL)
8438#define USB_EOTINTCLR_EPTXINTCLR27_Pos (27UL)
8439#define USB_EOTINTCLR_EPTXINTCLR27_Msk (0x8000000UL)
8440#define USB_EOTINTCLR_EPTXINTCLR28_Pos (28UL)
8441#define USB_EOTINTCLR_EPTXINTCLR28_Msk (0x10000000UL)
8442#define USB_EOTINTCLR_EPTXINTCLR29_Pos (29UL)
8443#define USB_EOTINTCLR_EPTXINTCLR29_Msk (0x20000000UL)
8444#define USB_EOTINTCLR_EPTXINTCLR30_Pos (30UL)
8445#define USB_EOTINTCLR_EPTXINTCLR30_Msk (0x40000000UL)
8446#define USB_EOTINTCLR_EPTXINTCLR31_Pos (31UL)
8447#define USB_EOTINTCLR_EPTXINTCLR31_Msk (0x80000000UL)
8448/* ======================================================= EOTINTSET ======================================================= */
8449#define USB_EOTINTSET_EPTXINTSET0_Pos (0UL)
8450#define USB_EOTINTSET_EPTXINTSET0_Msk (0x1UL)
8451#define USB_EOTINTSET_EPTXINTSET1_Pos (1UL)
8452#define USB_EOTINTSET_EPTXINTSET1_Msk (0x2UL)
8453#define USB_EOTINTSET_EPTXINTSET2_Pos (2UL)
8454#define USB_EOTINTSET_EPTXINTSET2_Msk (0x4UL)
8455#define USB_EOTINTSET_EPTXINTSET3_Pos (3UL)
8456#define USB_EOTINTSET_EPTXINTSET3_Msk (0x8UL)
8457#define USB_EOTINTSET_EPTXINTSET4_Pos (4UL)
8458#define USB_EOTINTSET_EPTXINTSET4_Msk (0x10UL)
8459#define USB_EOTINTSET_EPTXINTSET5_Pos (5UL)
8460#define USB_EOTINTSET_EPTXINTSET5_Msk (0x20UL)
8461#define USB_EOTINTSET_EPTXINTSET6_Pos (6UL)
8462#define USB_EOTINTSET_EPTXINTSET6_Msk (0x40UL)
8463#define USB_EOTINTSET_EPTXINTSET7_Pos (7UL)
8464#define USB_EOTINTSET_EPTXINTSET7_Msk (0x80UL)
8465#define USB_EOTINTSET_EPTXINTSET8_Pos (8UL)
8466#define USB_EOTINTSET_EPTXINTSET8_Msk (0x100UL)
8467#define USB_EOTINTSET_EPTXINTSET9_Pos (9UL)
8468#define USB_EOTINTSET_EPTXINTSET9_Msk (0x200UL)
8469#define USB_EOTINTSET_EPTXINTSET10_Pos (10UL)
8470#define USB_EOTINTSET_EPTXINTSET10_Msk (0x400UL)
8471#define USB_EOTINTSET_EPTXINTSET11_Pos (11UL)
8472#define USB_EOTINTSET_EPTXINTSET11_Msk (0x800UL)
8473#define USB_EOTINTSET_EPTXINTSET12_Pos (12UL)
8474#define USB_EOTINTSET_EPTXINTSET12_Msk (0x1000UL)
8475#define USB_EOTINTSET_EPTXINTSET13_Pos (13UL)
8476#define USB_EOTINTSET_EPTXINTSET13_Msk (0x2000UL)
8477#define USB_EOTINTSET_EPTXINTSET14_Pos (14UL)
8478#define USB_EOTINTSET_EPTXINTSET14_Msk (0x4000UL)
8479#define USB_EOTINTSET_EPTXINTSET15_Pos (15UL)
8480#define USB_EOTINTSET_EPTXINTSET15_Msk (0x8000UL)
8481#define USB_EOTINTSET_EPTXINTSET16_Pos (16UL)
8482#define USB_EOTINTSET_EPTXINTSET16_Msk (0x10000UL)
8483#define USB_EOTINTSET_EPTXINTSET17_Pos (17UL)
8484#define USB_EOTINTSET_EPTXINTSET17_Msk (0x20000UL)
8485#define USB_EOTINTSET_EPTXINTSET18_Pos (18UL)
8486#define USB_EOTINTSET_EPTXINTSET18_Msk (0x40000UL)
8487#define USB_EOTINTSET_EPTXINTSET19_Pos (19UL)
8488#define USB_EOTINTSET_EPTXINTSET19_Msk (0x80000UL)
8489#define USB_EOTINTSET_EPTXINTSET20_Pos (20UL)
8490#define USB_EOTINTSET_EPTXINTSET20_Msk (0x100000UL)
8491#define USB_EOTINTSET_EPTXINTSET21_Pos (21UL)
8492#define USB_EOTINTSET_EPTXINTSET21_Msk (0x200000UL)
8493#define USB_EOTINTSET_EPTXINTSET22_Pos (22UL)
8494#define USB_EOTINTSET_EPTXINTSET22_Msk (0x400000UL)
8495#define USB_EOTINTSET_EPTXINTSET23_Pos (23UL)
8496#define USB_EOTINTSET_EPTXINTSET23_Msk (0x800000UL)
8497#define USB_EOTINTSET_EPTXINTSET24_Pos (24UL)
8498#define USB_EOTINTSET_EPTXINTSET24_Msk (0x1000000UL)
8499#define USB_EOTINTSET_EPTXINTSET25_Pos (25UL)
8500#define USB_EOTINTSET_EPTXINTSET25_Msk (0x2000000UL)
8501#define USB_EOTINTSET_EPTXINTSET26_Pos (26UL)
8502#define USB_EOTINTSET_EPTXINTSET26_Msk (0x4000000UL)
8503#define USB_EOTINTSET_EPTXINTSET27_Pos (27UL)
8504#define USB_EOTINTSET_EPTXINTSET27_Msk (0x8000000UL)
8505#define USB_EOTINTSET_EPTXINTSET28_Pos (28UL)
8506#define USB_EOTINTSET_EPTXINTSET28_Msk (0x10000000UL)
8507#define USB_EOTINTSET_EPTXINTSET29_Pos (29UL)
8508#define USB_EOTINTSET_EPTXINTSET29_Msk (0x20000000UL)
8509#define USB_EOTINTSET_EPTXINTSET30_Pos (30UL)
8510#define USB_EOTINTSET_EPTXINTSET30_Msk (0x40000000UL)
8511#define USB_EOTINTSET_EPTXINTSET31_Pos (31UL)
8512#define USB_EOTINTSET_EPTXINTSET31_Msk (0x80000000UL)
8513/* ======================================================= NDDRINTST ======================================================= */
8514#define USB_NDDRINTST_EPNDDINTST0_Pos (0UL)
8515#define USB_NDDRINTST_EPNDDINTST0_Msk (0x1UL)
8516#define USB_NDDRINTST_EPNDDINTST1_Pos (1UL)
8517#define USB_NDDRINTST_EPNDDINTST1_Msk (0x2UL)
8518#define USB_NDDRINTST_EPNDDINTST2_Pos (2UL)
8519#define USB_NDDRINTST_EPNDDINTST2_Msk (0x4UL)
8520#define USB_NDDRINTST_EPNDDINTST3_Pos (3UL)
8521#define USB_NDDRINTST_EPNDDINTST3_Msk (0x8UL)
8522#define USB_NDDRINTST_EPNDDINTST4_Pos (4UL)
8523#define USB_NDDRINTST_EPNDDINTST4_Msk (0x10UL)
8524#define USB_NDDRINTST_EPNDDINTST5_Pos (5UL)
8525#define USB_NDDRINTST_EPNDDINTST5_Msk (0x20UL)
8526#define USB_NDDRINTST_EPNDDINTST6_Pos (6UL)
8527#define USB_NDDRINTST_EPNDDINTST6_Msk (0x40UL)
8528#define USB_NDDRINTST_EPNDDINTST7_Pos (7UL)
8529#define USB_NDDRINTST_EPNDDINTST7_Msk (0x80UL)
8530#define USB_NDDRINTST_EPNDDINTST8_Pos (8UL)
8531#define USB_NDDRINTST_EPNDDINTST8_Msk (0x100UL)
8532#define USB_NDDRINTST_EPNDDINTST9_Pos (9UL)
8533#define USB_NDDRINTST_EPNDDINTST9_Msk (0x200UL)
8534#define USB_NDDRINTST_EPNDDINTST10_Pos (10UL)
8535#define USB_NDDRINTST_EPNDDINTST10_Msk (0x400UL)
8536#define USB_NDDRINTST_EPNDDINTST11_Pos (11UL)
8537#define USB_NDDRINTST_EPNDDINTST11_Msk (0x800UL)
8538#define USB_NDDRINTST_EPNDDINTST12_Pos (12UL)
8539#define USB_NDDRINTST_EPNDDINTST12_Msk (0x1000UL)
8540#define USB_NDDRINTST_EPNDDINTST13_Pos (13UL)
8541#define USB_NDDRINTST_EPNDDINTST13_Msk (0x2000UL)
8542#define USB_NDDRINTST_EPNDDINTST14_Pos (14UL)
8543#define USB_NDDRINTST_EPNDDINTST14_Msk (0x4000UL)
8544#define USB_NDDRINTST_EPNDDINTST15_Pos (15UL)
8545#define USB_NDDRINTST_EPNDDINTST15_Msk (0x8000UL)
8546#define USB_NDDRINTST_EPNDDINTST16_Pos (16UL)
8547#define USB_NDDRINTST_EPNDDINTST16_Msk (0x10000UL)
8548#define USB_NDDRINTST_EPNDDINTST17_Pos (17UL)
8549#define USB_NDDRINTST_EPNDDINTST17_Msk (0x20000UL)
8550#define USB_NDDRINTST_EPNDDINTST18_Pos (18UL)
8551#define USB_NDDRINTST_EPNDDINTST18_Msk (0x40000UL)
8552#define USB_NDDRINTST_EPNDDINTST19_Pos (19UL)
8553#define USB_NDDRINTST_EPNDDINTST19_Msk (0x80000UL)
8554#define USB_NDDRINTST_EPNDDINTST20_Pos (20UL)
8555#define USB_NDDRINTST_EPNDDINTST20_Msk (0x100000UL)
8556#define USB_NDDRINTST_EPNDDINTST21_Pos (21UL)
8557#define USB_NDDRINTST_EPNDDINTST21_Msk (0x200000UL)
8558#define USB_NDDRINTST_EPNDDINTST22_Pos (22UL)
8559#define USB_NDDRINTST_EPNDDINTST22_Msk (0x400000UL)
8560#define USB_NDDRINTST_EPNDDINTST23_Pos (23UL)
8561#define USB_NDDRINTST_EPNDDINTST23_Msk (0x800000UL)
8562#define USB_NDDRINTST_EPNDDINTST24_Pos (24UL)
8563#define USB_NDDRINTST_EPNDDINTST24_Msk (0x1000000UL)
8564#define USB_NDDRINTST_EPNDDINTST25_Pos (25UL)
8565#define USB_NDDRINTST_EPNDDINTST25_Msk (0x2000000UL)
8566#define USB_NDDRINTST_EPNDDINTST26_Pos (26UL)
8567#define USB_NDDRINTST_EPNDDINTST26_Msk (0x4000000UL)
8568#define USB_NDDRINTST_EPNDDINTST27_Pos (27UL)
8569#define USB_NDDRINTST_EPNDDINTST27_Msk (0x8000000UL)
8570#define USB_NDDRINTST_EPNDDINTST28_Pos (28UL)
8571#define USB_NDDRINTST_EPNDDINTST28_Msk (0x10000000UL)
8572#define USB_NDDRINTST_EPNDDINTST29_Pos (29UL)
8573#define USB_NDDRINTST_EPNDDINTST29_Msk (0x20000000UL)
8574#define USB_NDDRINTST_EPNDDINTST30_Pos (30UL)
8575#define USB_NDDRINTST_EPNDDINTST30_Msk (0x40000000UL)
8576#define USB_NDDRINTST_EPNDDINTST31_Pos (31UL)
8577#define USB_NDDRINTST_EPNDDINTST31_Msk (0x80000000UL)
8578/* ====================================================== NDDRINTCLR ======================================================= */
8579#define USB_NDDRINTCLR_EPNDDINTCLR0_Pos (0UL)
8580#define USB_NDDRINTCLR_EPNDDINTCLR0_Msk (0x1UL)
8581#define USB_NDDRINTCLR_EPNDDINTCLR1_Pos (1UL)
8582#define USB_NDDRINTCLR_EPNDDINTCLR1_Msk (0x2UL)
8583#define USB_NDDRINTCLR_EPNDDINTCLR2_Pos (2UL)
8584#define USB_NDDRINTCLR_EPNDDINTCLR2_Msk (0x4UL)
8585#define USB_NDDRINTCLR_EPNDDINTCLR3_Pos (3UL)
8586#define USB_NDDRINTCLR_EPNDDINTCLR3_Msk (0x8UL)
8587#define USB_NDDRINTCLR_EPNDDINTCLR4_Pos (4UL)
8588#define USB_NDDRINTCLR_EPNDDINTCLR4_Msk (0x10UL)
8589#define USB_NDDRINTCLR_EPNDDINTCLR5_Pos (5UL)
8590#define USB_NDDRINTCLR_EPNDDINTCLR5_Msk (0x20UL)
8591#define USB_NDDRINTCLR_EPNDDINTCLR6_Pos (6UL)
8592#define USB_NDDRINTCLR_EPNDDINTCLR6_Msk (0x40UL)
8593#define USB_NDDRINTCLR_EPNDDINTCLR7_Pos (7UL)
8594#define USB_NDDRINTCLR_EPNDDINTCLR7_Msk (0x80UL)
8595#define USB_NDDRINTCLR_EPNDDINTCLR8_Pos (8UL)
8596#define USB_NDDRINTCLR_EPNDDINTCLR8_Msk (0x100UL)
8597#define USB_NDDRINTCLR_EPNDDINTCLR9_Pos (9UL)
8598#define USB_NDDRINTCLR_EPNDDINTCLR9_Msk (0x200UL)
8599#define USB_NDDRINTCLR_EPNDDINTCLR10_Pos (10UL)
8600#define USB_NDDRINTCLR_EPNDDINTCLR10_Msk (0x400UL)
8601#define USB_NDDRINTCLR_EPNDDINTCLR11_Pos (11UL)
8602#define USB_NDDRINTCLR_EPNDDINTCLR11_Msk (0x800UL)
8603#define USB_NDDRINTCLR_EPNDDINTCLR12_Pos (12UL)
8604#define USB_NDDRINTCLR_EPNDDINTCLR12_Msk (0x1000UL)
8605#define USB_NDDRINTCLR_EPNDDINTCLR13_Pos (13UL)
8606#define USB_NDDRINTCLR_EPNDDINTCLR13_Msk (0x2000UL)
8607#define USB_NDDRINTCLR_EPNDDINTCLR14_Pos (14UL)
8608#define USB_NDDRINTCLR_EPNDDINTCLR14_Msk (0x4000UL)
8609#define USB_NDDRINTCLR_EPNDDINTCLR15_Pos (15UL)
8610#define USB_NDDRINTCLR_EPNDDINTCLR15_Msk (0x8000UL)
8611#define USB_NDDRINTCLR_EPNDDINTCLR16_Pos (16UL)
8612#define USB_NDDRINTCLR_EPNDDINTCLR16_Msk (0x10000UL)
8613#define USB_NDDRINTCLR_EPNDDINTCLR17_Pos (17UL)
8614#define USB_NDDRINTCLR_EPNDDINTCLR17_Msk (0x20000UL)
8615#define USB_NDDRINTCLR_EPNDDINTCLR18_Pos (18UL)
8616#define USB_NDDRINTCLR_EPNDDINTCLR18_Msk (0x40000UL)
8617#define USB_NDDRINTCLR_EPNDDINTCLR19_Pos (19UL)
8618#define USB_NDDRINTCLR_EPNDDINTCLR19_Msk (0x80000UL)
8619#define USB_NDDRINTCLR_EPNDDINTCLR20_Pos (20UL)
8620#define USB_NDDRINTCLR_EPNDDINTCLR20_Msk (0x100000UL)
8621#define USB_NDDRINTCLR_EPNDDINTCLR21_Pos (21UL)
8622#define USB_NDDRINTCLR_EPNDDINTCLR21_Msk (0x200000UL)
8623#define USB_NDDRINTCLR_EPNDDINTCLR22_Pos (22UL)
8624#define USB_NDDRINTCLR_EPNDDINTCLR22_Msk (0x400000UL)
8625#define USB_NDDRINTCLR_EPNDDINTCLR23_Pos (23UL)
8626#define USB_NDDRINTCLR_EPNDDINTCLR23_Msk (0x800000UL)
8627#define USB_NDDRINTCLR_EPNDDINTCLR24_Pos (24UL)
8628#define USB_NDDRINTCLR_EPNDDINTCLR24_Msk (0x1000000UL)
8629#define USB_NDDRINTCLR_EPNDDINTCLR25_Pos (25UL)
8630#define USB_NDDRINTCLR_EPNDDINTCLR25_Msk (0x2000000UL)
8631#define USB_NDDRINTCLR_EPNDDINTCLR26_Pos (26UL)
8632#define USB_NDDRINTCLR_EPNDDINTCLR26_Msk (0x4000000UL)
8633#define USB_NDDRINTCLR_EPNDDINTCLR27_Pos (27UL)
8634#define USB_NDDRINTCLR_EPNDDINTCLR27_Msk (0x8000000UL)
8635#define USB_NDDRINTCLR_EPNDDINTCLR28_Pos (28UL)
8636#define USB_NDDRINTCLR_EPNDDINTCLR28_Msk (0x10000000UL)
8637#define USB_NDDRINTCLR_EPNDDINTCLR29_Pos (29UL)
8638#define USB_NDDRINTCLR_EPNDDINTCLR29_Msk (0x20000000UL)
8639#define USB_NDDRINTCLR_EPNDDINTCLR30_Pos (30UL)
8640#define USB_NDDRINTCLR_EPNDDINTCLR30_Msk (0x40000000UL)
8641#define USB_NDDRINTCLR_EPNDDINTCLR31_Pos (31UL)
8642#define USB_NDDRINTCLR_EPNDDINTCLR31_Msk (0x80000000UL)
8643/* ====================================================== NDDRINTSET ======================================================= */
8644#define USB_NDDRINTSET_EPNDDINTSET0_Pos (0UL)
8645#define USB_NDDRINTSET_EPNDDINTSET0_Msk (0x1UL)
8646#define USB_NDDRINTSET_EPNDDINTSET1_Pos (1UL)
8647#define USB_NDDRINTSET_EPNDDINTSET1_Msk (0x2UL)
8648#define USB_NDDRINTSET_EPNDDINTSET2_Pos (2UL)
8649#define USB_NDDRINTSET_EPNDDINTSET2_Msk (0x4UL)
8650#define USB_NDDRINTSET_EPNDDINTSET3_Pos (3UL)
8651#define USB_NDDRINTSET_EPNDDINTSET3_Msk (0x8UL)
8652#define USB_NDDRINTSET_EPNDDINTSET4_Pos (4UL)
8653#define USB_NDDRINTSET_EPNDDINTSET4_Msk (0x10UL)
8654#define USB_NDDRINTSET_EPNDDINTSET5_Pos (5UL)
8655#define USB_NDDRINTSET_EPNDDINTSET5_Msk (0x20UL)
8656#define USB_NDDRINTSET_EPNDDINTSET6_Pos (6UL)
8657#define USB_NDDRINTSET_EPNDDINTSET6_Msk (0x40UL)
8658#define USB_NDDRINTSET_EPNDDINTSET7_Pos (7UL)
8659#define USB_NDDRINTSET_EPNDDINTSET7_Msk (0x80UL)
8660#define USB_NDDRINTSET_EPNDDINTSET8_Pos (8UL)
8661#define USB_NDDRINTSET_EPNDDINTSET8_Msk (0x100UL)
8662#define USB_NDDRINTSET_EPNDDINTSET9_Pos (9UL)
8663#define USB_NDDRINTSET_EPNDDINTSET9_Msk (0x200UL)
8664#define USB_NDDRINTSET_EPNDDINTSET10_Pos (10UL)
8665#define USB_NDDRINTSET_EPNDDINTSET10_Msk (0x400UL)
8666#define USB_NDDRINTSET_EPNDDINTSET11_Pos (11UL)
8667#define USB_NDDRINTSET_EPNDDINTSET11_Msk (0x800UL)
8668#define USB_NDDRINTSET_EPNDDINTSET12_Pos (12UL)
8669#define USB_NDDRINTSET_EPNDDINTSET12_Msk (0x1000UL)
8670#define USB_NDDRINTSET_EPNDDINTSET13_Pos (13UL)
8671#define USB_NDDRINTSET_EPNDDINTSET13_Msk (0x2000UL)
8672#define USB_NDDRINTSET_EPNDDINTSET14_Pos (14UL)
8673#define USB_NDDRINTSET_EPNDDINTSET14_Msk (0x4000UL)
8674#define USB_NDDRINTSET_EPNDDINTSET15_Pos (15UL)
8675#define USB_NDDRINTSET_EPNDDINTSET15_Msk (0x8000UL)
8676#define USB_NDDRINTSET_EPNDDINTSET16_Pos (16UL)
8677#define USB_NDDRINTSET_EPNDDINTSET16_Msk (0x10000UL)
8678#define USB_NDDRINTSET_EPNDDINTSET17_Pos (17UL)
8679#define USB_NDDRINTSET_EPNDDINTSET17_Msk (0x20000UL)
8680#define USB_NDDRINTSET_EPNDDINTSET18_Pos (18UL)
8681#define USB_NDDRINTSET_EPNDDINTSET18_Msk (0x40000UL)
8682#define USB_NDDRINTSET_EPNDDINTSET19_Pos (19UL)
8683#define USB_NDDRINTSET_EPNDDINTSET19_Msk (0x80000UL)
8684#define USB_NDDRINTSET_EPNDDINTSET20_Pos (20UL)
8685#define USB_NDDRINTSET_EPNDDINTSET20_Msk (0x100000UL)
8686#define USB_NDDRINTSET_EPNDDINTSET21_Pos (21UL)
8687#define USB_NDDRINTSET_EPNDDINTSET21_Msk (0x200000UL)
8688#define USB_NDDRINTSET_EPNDDINTSET22_Pos (22UL)
8689#define USB_NDDRINTSET_EPNDDINTSET22_Msk (0x400000UL)
8690#define USB_NDDRINTSET_EPNDDINTSET23_Pos (23UL)
8691#define USB_NDDRINTSET_EPNDDINTSET23_Msk (0x800000UL)
8692#define USB_NDDRINTSET_EPNDDINTSET24_Pos (24UL)
8693#define USB_NDDRINTSET_EPNDDINTSET24_Msk (0x1000000UL)
8694#define USB_NDDRINTSET_EPNDDINTSET25_Pos (25UL)
8695#define USB_NDDRINTSET_EPNDDINTSET25_Msk (0x2000000UL)
8696#define USB_NDDRINTSET_EPNDDINTSET26_Pos (26UL)
8697#define USB_NDDRINTSET_EPNDDINTSET26_Msk (0x4000000UL)
8698#define USB_NDDRINTSET_EPNDDINTSET27_Pos (27UL)
8699#define USB_NDDRINTSET_EPNDDINTSET27_Msk (0x8000000UL)
8700#define USB_NDDRINTSET_EPNDDINTSET28_Pos (28UL)
8701#define USB_NDDRINTSET_EPNDDINTSET28_Msk (0x10000000UL)
8702#define USB_NDDRINTSET_EPNDDINTSET29_Pos (29UL)
8703#define USB_NDDRINTSET_EPNDDINTSET29_Msk (0x20000000UL)
8704#define USB_NDDRINTSET_EPNDDINTSET30_Pos (30UL)
8705#define USB_NDDRINTSET_EPNDDINTSET30_Msk (0x40000000UL)
8706#define USB_NDDRINTSET_EPNDDINTSET31_Pos (31UL)
8707#define USB_NDDRINTSET_EPNDDINTSET31_Msk (0x80000000UL)
8708/* ====================================================== SYSERRINTST ====================================================== */
8709#define USB_SYSERRINTST_EPERRINTST0_Pos (0UL)
8710#define USB_SYSERRINTST_EPERRINTST0_Msk (0x1UL)
8711#define USB_SYSERRINTST_EPERRINTST1_Pos (1UL)
8712#define USB_SYSERRINTST_EPERRINTST1_Msk (0x2UL)
8713#define USB_SYSERRINTST_EPERRINTST2_Pos (2UL)
8714#define USB_SYSERRINTST_EPERRINTST2_Msk (0x4UL)
8715#define USB_SYSERRINTST_EPERRINTST3_Pos (3UL)
8716#define USB_SYSERRINTST_EPERRINTST3_Msk (0x8UL)
8717#define USB_SYSERRINTST_EPERRINTST4_Pos (4UL)
8718#define USB_SYSERRINTST_EPERRINTST4_Msk (0x10UL)
8719#define USB_SYSERRINTST_EPERRINTST5_Pos (5UL)
8720#define USB_SYSERRINTST_EPERRINTST5_Msk (0x20UL)
8721#define USB_SYSERRINTST_EPERRINTST6_Pos (6UL)
8722#define USB_SYSERRINTST_EPERRINTST6_Msk (0x40UL)
8723#define USB_SYSERRINTST_EPERRINTST7_Pos (7UL)
8724#define USB_SYSERRINTST_EPERRINTST7_Msk (0x80UL)
8725#define USB_SYSERRINTST_EPERRINTST8_Pos (8UL)
8726#define USB_SYSERRINTST_EPERRINTST8_Msk (0x100UL)
8727#define USB_SYSERRINTST_EPERRINTST9_Pos (9UL)
8728#define USB_SYSERRINTST_EPERRINTST9_Msk (0x200UL)
8729#define USB_SYSERRINTST_EPERRINTST10_Pos (10UL)
8730#define USB_SYSERRINTST_EPERRINTST10_Msk (0x400UL)
8731#define USB_SYSERRINTST_EPERRINTST11_Pos (11UL)
8732#define USB_SYSERRINTST_EPERRINTST11_Msk (0x800UL)
8733#define USB_SYSERRINTST_EPERRINTST12_Pos (12UL)
8734#define USB_SYSERRINTST_EPERRINTST12_Msk (0x1000UL)
8735#define USB_SYSERRINTST_EPERRINTST13_Pos (13UL)
8736#define USB_SYSERRINTST_EPERRINTST13_Msk (0x2000UL)
8737#define USB_SYSERRINTST_EPERRINTST14_Pos (14UL)
8738#define USB_SYSERRINTST_EPERRINTST14_Msk (0x4000UL)
8739#define USB_SYSERRINTST_EPERRINTST15_Pos (15UL)
8740#define USB_SYSERRINTST_EPERRINTST15_Msk (0x8000UL)
8741#define USB_SYSERRINTST_EPERRINTST16_Pos (16UL)
8742#define USB_SYSERRINTST_EPERRINTST16_Msk (0x10000UL)
8743#define USB_SYSERRINTST_EPERRINTST17_Pos (17UL)
8744#define USB_SYSERRINTST_EPERRINTST17_Msk (0x20000UL)
8745#define USB_SYSERRINTST_EPERRINTST18_Pos (18UL)
8746#define USB_SYSERRINTST_EPERRINTST18_Msk (0x40000UL)
8747#define USB_SYSERRINTST_EPERRINTST19_Pos (19UL)
8748#define USB_SYSERRINTST_EPERRINTST19_Msk (0x80000UL)
8749#define USB_SYSERRINTST_EPERRINTST20_Pos (20UL)
8750#define USB_SYSERRINTST_EPERRINTST20_Msk (0x100000UL)
8751#define USB_SYSERRINTST_EPERRINTST21_Pos (21UL)
8752#define USB_SYSERRINTST_EPERRINTST21_Msk (0x200000UL)
8753#define USB_SYSERRINTST_EPERRINTST22_Pos (22UL)
8754#define USB_SYSERRINTST_EPERRINTST22_Msk (0x400000UL)
8755#define USB_SYSERRINTST_EPERRINTST23_Pos (23UL)
8756#define USB_SYSERRINTST_EPERRINTST23_Msk (0x800000UL)
8757#define USB_SYSERRINTST_EPERRINTST24_Pos (24UL)
8758#define USB_SYSERRINTST_EPERRINTST24_Msk (0x1000000UL)
8759#define USB_SYSERRINTST_EPERRINTST25_Pos (25UL)
8760#define USB_SYSERRINTST_EPERRINTST25_Msk (0x2000000UL)
8761#define USB_SYSERRINTST_EPERRINTST26_Pos (26UL)
8762#define USB_SYSERRINTST_EPERRINTST26_Msk (0x4000000UL)
8763#define USB_SYSERRINTST_EPERRINTST27_Pos (27UL)
8764#define USB_SYSERRINTST_EPERRINTST27_Msk (0x8000000UL)
8765#define USB_SYSERRINTST_EPERRINTST28_Pos (28UL)
8766#define USB_SYSERRINTST_EPERRINTST28_Msk (0x10000000UL)
8767#define USB_SYSERRINTST_EPERRINTST29_Pos (29UL)
8768#define USB_SYSERRINTST_EPERRINTST29_Msk (0x20000000UL)
8769#define USB_SYSERRINTST_EPERRINTST30_Pos (30UL)
8770#define USB_SYSERRINTST_EPERRINTST30_Msk (0x40000000UL)
8771#define USB_SYSERRINTST_EPERRINTST31_Pos (31UL)
8772#define USB_SYSERRINTST_EPERRINTST31_Msk (0x80000000UL)
8773/* ===================================================== SYSERRINTCLR ====================================================== */
8774#define USB_SYSERRINTCLR_EPERRINTCLR0_Pos (0UL)
8775#define USB_SYSERRINTCLR_EPERRINTCLR0_Msk (0x1UL)
8776#define USB_SYSERRINTCLR_EPERRINTCLR1_Pos (1UL)
8777#define USB_SYSERRINTCLR_EPERRINTCLR1_Msk (0x2UL)
8778#define USB_SYSERRINTCLR_EPERRINTCLR2_Pos (2UL)
8779#define USB_SYSERRINTCLR_EPERRINTCLR2_Msk (0x4UL)
8780#define USB_SYSERRINTCLR_EPERRINTCLR3_Pos (3UL)
8781#define USB_SYSERRINTCLR_EPERRINTCLR3_Msk (0x8UL)
8782#define USB_SYSERRINTCLR_EPERRINTCLR4_Pos (4UL)
8783#define USB_SYSERRINTCLR_EPERRINTCLR4_Msk (0x10UL)
8784#define USB_SYSERRINTCLR_EPERRINTCLR5_Pos (5UL)
8785#define USB_SYSERRINTCLR_EPERRINTCLR5_Msk (0x20UL)
8786#define USB_SYSERRINTCLR_EPERRINTCLR6_Pos (6UL)
8787#define USB_SYSERRINTCLR_EPERRINTCLR6_Msk (0x40UL)
8788#define USB_SYSERRINTCLR_EPERRINTCLR7_Pos (7UL)
8789#define USB_SYSERRINTCLR_EPERRINTCLR7_Msk (0x80UL)
8790#define USB_SYSERRINTCLR_EPERRINTCLR8_Pos (8UL)
8791#define USB_SYSERRINTCLR_EPERRINTCLR8_Msk (0x100UL)
8792#define USB_SYSERRINTCLR_EPERRINTCLR9_Pos (9UL)
8793#define USB_SYSERRINTCLR_EPERRINTCLR9_Msk (0x200UL)
8794#define USB_SYSERRINTCLR_EPERRINTCLR10_Pos (10UL)
8795#define USB_SYSERRINTCLR_EPERRINTCLR10_Msk (0x400UL)
8796#define USB_SYSERRINTCLR_EPERRINTCLR11_Pos (11UL)
8797#define USB_SYSERRINTCLR_EPERRINTCLR11_Msk (0x800UL)
8798#define USB_SYSERRINTCLR_EPERRINTCLR12_Pos (12UL)
8799#define USB_SYSERRINTCLR_EPERRINTCLR12_Msk (0x1000UL)
8800#define USB_SYSERRINTCLR_EPERRINTCLR13_Pos (13UL)
8801#define USB_SYSERRINTCLR_EPERRINTCLR13_Msk (0x2000UL)
8802#define USB_SYSERRINTCLR_EPERRINTCLR14_Pos (14UL)
8803#define USB_SYSERRINTCLR_EPERRINTCLR14_Msk (0x4000UL)
8804#define USB_SYSERRINTCLR_EPERRINTCLR15_Pos (15UL)
8805#define USB_SYSERRINTCLR_EPERRINTCLR15_Msk (0x8000UL)
8806#define USB_SYSERRINTCLR_EPERRINTCLR16_Pos (16UL)
8807#define USB_SYSERRINTCLR_EPERRINTCLR16_Msk (0x10000UL)
8808#define USB_SYSERRINTCLR_EPERRINTCLR17_Pos (17UL)
8809#define USB_SYSERRINTCLR_EPERRINTCLR17_Msk (0x20000UL)
8810#define USB_SYSERRINTCLR_EPERRINTCLR18_Pos (18UL)
8811#define USB_SYSERRINTCLR_EPERRINTCLR18_Msk (0x40000UL)
8812#define USB_SYSERRINTCLR_EPERRINTCLR19_Pos (19UL)
8813#define USB_SYSERRINTCLR_EPERRINTCLR19_Msk (0x80000UL)
8814#define USB_SYSERRINTCLR_EPERRINTCLR20_Pos (20UL)
8815#define USB_SYSERRINTCLR_EPERRINTCLR20_Msk (0x100000UL)
8816#define USB_SYSERRINTCLR_EPERRINTCLR21_Pos (21UL)
8817#define USB_SYSERRINTCLR_EPERRINTCLR21_Msk (0x200000UL)
8818#define USB_SYSERRINTCLR_EPERRINTCLR22_Pos (22UL)
8819#define USB_SYSERRINTCLR_EPERRINTCLR22_Msk (0x400000UL)
8820#define USB_SYSERRINTCLR_EPERRINTCLR23_Pos (23UL)
8821#define USB_SYSERRINTCLR_EPERRINTCLR23_Msk (0x800000UL)
8822#define USB_SYSERRINTCLR_EPERRINTCLR24_Pos (24UL)
8823#define USB_SYSERRINTCLR_EPERRINTCLR24_Msk (0x1000000UL)
8824#define USB_SYSERRINTCLR_EPERRINTCLR25_Pos (25UL)
8825#define USB_SYSERRINTCLR_EPERRINTCLR25_Msk (0x2000000UL)
8826#define USB_SYSERRINTCLR_EPERRINTCLR26_Pos (26UL)
8827#define USB_SYSERRINTCLR_EPERRINTCLR26_Msk (0x4000000UL)
8828#define USB_SYSERRINTCLR_EPERRINTCLR27_Pos (27UL)
8829#define USB_SYSERRINTCLR_EPERRINTCLR27_Msk (0x8000000UL)
8830#define USB_SYSERRINTCLR_EPERRINTCLR28_Pos (28UL)
8831#define USB_SYSERRINTCLR_EPERRINTCLR28_Msk (0x10000000UL)
8832#define USB_SYSERRINTCLR_EPERRINTCLR29_Pos (29UL)
8833#define USB_SYSERRINTCLR_EPERRINTCLR29_Msk (0x20000000UL)
8834#define USB_SYSERRINTCLR_EPERRINTCLR30_Pos (30UL)
8835#define USB_SYSERRINTCLR_EPERRINTCLR30_Msk (0x40000000UL)
8836#define USB_SYSERRINTCLR_EPERRINTCLR31_Pos (31UL)
8837#define USB_SYSERRINTCLR_EPERRINTCLR31_Msk (0x80000000UL)
8838/* ===================================================== SYSERRINTSET ====================================================== */
8839#define USB_SYSERRINTSET_EPERRINTSET0_Pos (0UL)
8840#define USB_SYSERRINTSET_EPERRINTSET0_Msk (0x1UL)
8841#define USB_SYSERRINTSET_EPERRINTSET1_Pos (1UL)
8842#define USB_SYSERRINTSET_EPERRINTSET1_Msk (0x2UL)
8843#define USB_SYSERRINTSET_EPERRINTSET2_Pos (2UL)
8844#define USB_SYSERRINTSET_EPERRINTSET2_Msk (0x4UL)
8845#define USB_SYSERRINTSET_EPERRINTSET3_Pos (3UL)
8846#define USB_SYSERRINTSET_EPERRINTSET3_Msk (0x8UL)
8847#define USB_SYSERRINTSET_EPERRINTSET4_Pos (4UL)
8848#define USB_SYSERRINTSET_EPERRINTSET4_Msk (0x10UL)
8849#define USB_SYSERRINTSET_EPERRINTSET5_Pos (5UL)
8850#define USB_SYSERRINTSET_EPERRINTSET5_Msk (0x20UL)
8851#define USB_SYSERRINTSET_EPERRINTSET6_Pos (6UL)
8852#define USB_SYSERRINTSET_EPERRINTSET6_Msk (0x40UL)
8853#define USB_SYSERRINTSET_EPERRINTSET7_Pos (7UL)
8854#define USB_SYSERRINTSET_EPERRINTSET7_Msk (0x80UL)
8855#define USB_SYSERRINTSET_EPERRINTSET8_Pos (8UL)
8856#define USB_SYSERRINTSET_EPERRINTSET8_Msk (0x100UL)
8857#define USB_SYSERRINTSET_EPERRINTSET9_Pos (9UL)
8858#define USB_SYSERRINTSET_EPERRINTSET9_Msk (0x200UL)
8859#define USB_SYSERRINTSET_EPERRINTSET10_Pos (10UL)
8860#define USB_SYSERRINTSET_EPERRINTSET10_Msk (0x400UL)
8861#define USB_SYSERRINTSET_EPERRINTSET11_Pos (11UL)
8862#define USB_SYSERRINTSET_EPERRINTSET11_Msk (0x800UL)
8863#define USB_SYSERRINTSET_EPERRINTSET12_Pos (12UL)
8864#define USB_SYSERRINTSET_EPERRINTSET12_Msk (0x1000UL)
8865#define USB_SYSERRINTSET_EPERRINTSET13_Pos (13UL)
8866#define USB_SYSERRINTSET_EPERRINTSET13_Msk (0x2000UL)
8867#define USB_SYSERRINTSET_EPERRINTSET14_Pos (14UL)
8868#define USB_SYSERRINTSET_EPERRINTSET14_Msk (0x4000UL)
8869#define USB_SYSERRINTSET_EPERRINTSET15_Pos (15UL)
8870#define USB_SYSERRINTSET_EPERRINTSET15_Msk (0x8000UL)
8871#define USB_SYSERRINTSET_EPERRINTSET16_Pos (16UL)
8872#define USB_SYSERRINTSET_EPERRINTSET16_Msk (0x10000UL)
8873#define USB_SYSERRINTSET_EPERRINTSET17_Pos (17UL)
8874#define USB_SYSERRINTSET_EPERRINTSET17_Msk (0x20000UL)
8875#define USB_SYSERRINTSET_EPERRINTSET18_Pos (18UL)
8876#define USB_SYSERRINTSET_EPERRINTSET18_Msk (0x40000UL)
8877#define USB_SYSERRINTSET_EPERRINTSET19_Pos (19UL)
8878#define USB_SYSERRINTSET_EPERRINTSET19_Msk (0x80000UL)
8879#define USB_SYSERRINTSET_EPERRINTSET20_Pos (20UL)
8880#define USB_SYSERRINTSET_EPERRINTSET20_Msk (0x100000UL)
8881#define USB_SYSERRINTSET_EPERRINTSET21_Pos (21UL)
8882#define USB_SYSERRINTSET_EPERRINTSET21_Msk (0x200000UL)
8883#define USB_SYSERRINTSET_EPERRINTSET22_Pos (22UL)
8884#define USB_SYSERRINTSET_EPERRINTSET22_Msk (0x400000UL)
8885#define USB_SYSERRINTSET_EPERRINTSET23_Pos (23UL)
8886#define USB_SYSERRINTSET_EPERRINTSET23_Msk (0x800000UL)
8887#define USB_SYSERRINTSET_EPERRINTSET24_Pos (24UL)
8888#define USB_SYSERRINTSET_EPERRINTSET24_Msk (0x1000000UL)
8889#define USB_SYSERRINTSET_EPERRINTSET25_Pos (25UL)
8890#define USB_SYSERRINTSET_EPERRINTSET25_Msk (0x2000000UL)
8891#define USB_SYSERRINTSET_EPERRINTSET26_Pos (26UL)
8892#define USB_SYSERRINTSET_EPERRINTSET26_Msk (0x4000000UL)
8893#define USB_SYSERRINTSET_EPERRINTSET27_Pos (27UL)
8894#define USB_SYSERRINTSET_EPERRINTSET27_Msk (0x8000000UL)
8895#define USB_SYSERRINTSET_EPERRINTSET28_Pos (28UL)
8896#define USB_SYSERRINTSET_EPERRINTSET28_Msk (0x10000000UL)
8897#define USB_SYSERRINTSET_EPERRINTSET29_Pos (29UL)
8898#define USB_SYSERRINTSET_EPERRINTSET29_Msk (0x20000000UL)
8899#define USB_SYSERRINTSET_EPERRINTSET30_Pos (30UL)
8900#define USB_SYSERRINTSET_EPERRINTSET30_Msk (0x40000000UL)
8901#define USB_SYSERRINTSET_EPERRINTSET31_Pos (31UL)
8902#define USB_SYSERRINTSET_EPERRINTSET31_Msk (0x80000000UL)
8903/* ======================================================== I2C_RX ========================================================= */
8904#define USB_I2C_RX_RXDATA_Pos (0UL)
8905#define USB_I2C_RX_RXDATA_Msk (0xffUL)
8906/* ======================================================== I2C_WO ========================================================= */
8907#define USB_I2C_WO_TXDATA_Pos (0UL)
8908#define USB_I2C_WO_TXDATA_Msk (0xffUL)
8909#define USB_I2C_WO_START_Pos (8UL)
8910#define USB_I2C_WO_START_Msk (0x100UL)
8911#define USB_I2C_WO_STOP_Pos (9UL)
8912#define USB_I2C_WO_STOP_Msk (0x200UL)
8913/* ======================================================== I2C_STS ======================================================== */
8914#define USB_I2C_STS_TDI_Pos (0UL)
8915#define USB_I2C_STS_TDI_Msk (0x1UL)
8916#define USB_I2C_STS_AFI_Pos (1UL)
8917#define USB_I2C_STS_AFI_Msk (0x2UL)
8918#define USB_I2C_STS_NAI_Pos (2UL)
8919#define USB_I2C_STS_NAI_Msk (0x4UL)
8920#define USB_I2C_STS_DRMI_Pos (3UL)
8921#define USB_I2C_STS_DRMI_Msk (0x8UL)
8922#define USB_I2C_STS_DRSI_Pos (4UL)
8923#define USB_I2C_STS_DRSI_Msk (0x10UL)
8924#define USB_I2C_STS_Active_Pos (5UL)
8925#define USB_I2C_STS_Active_Msk (0x20UL)
8926#define USB_I2C_STS_SCL_Pos (6UL)
8927#define USB_I2C_STS_SCL_Msk (0x40UL)
8928#define USB_I2C_STS_SDA_Pos (7UL)
8929#define USB_I2C_STS_SDA_Msk (0x80UL)
8930#define USB_I2C_STS_RFF_Pos (8UL)
8931#define USB_I2C_STS_RFF_Msk (0x100UL)
8932#define USB_I2C_STS_RFE_Pos (9UL)
8933#define USB_I2C_STS_RFE_Msk (0x200UL)
8934#define USB_I2C_STS_TFF_Pos (10UL)
8935#define USB_I2C_STS_TFF_Msk (0x400UL)
8936#define USB_I2C_STS_TFE_Pos (11UL)
8937#define USB_I2C_STS_TFE_Msk (0x800UL)
8938/* ======================================================== I2C_CTL ======================================================== */
8939#define USB_I2C_CTL_TDIE_Pos (0UL)
8940#define USB_I2C_CTL_TDIE_Msk (0x1UL)
8941#define USB_I2C_CTL_AFIE_Pos (1UL)
8942#define USB_I2C_CTL_AFIE_Msk (0x2UL)
8943#define USB_I2C_CTL_NAIE_Pos (2UL)
8944#define USB_I2C_CTL_NAIE_Msk (0x4UL)
8945#define USB_I2C_CTL_DRMIE_Pos (3UL)
8946#define USB_I2C_CTL_DRMIE_Msk (0x8UL)
8947#define USB_I2C_CTL_DRSIE_Pos (4UL)
8948#define USB_I2C_CTL_DRSIE_Msk (0x10UL)
8949#define USB_I2C_CTL_REFIE_Pos (5UL)
8950#define USB_I2C_CTL_REFIE_Msk (0x20UL)
8951#define USB_I2C_CTL_RFDAIE_Pos (6UL)
8952#define USB_I2C_CTL_RFDAIE_Msk (0x40UL)
8953#define USB_I2C_CTL_TFFIE_Pos (7UL)
8954#define USB_I2C_CTL_TFFIE_Msk (0x80UL)
8955#define USB_I2C_CTL_SRST_Pos (8UL)
8956#define USB_I2C_CTL_SRST_Msk (0x100UL)
8957/* ======================================================= I2C_CLKHI ======================================================= */
8958#define USB_I2C_CLKHI_CDHI_Pos (0UL)
8959#define USB_I2C_CLKHI_CDHI_Msk (0xffUL)
8960/* ======================================================= I2C_CLKLO ======================================================= */
8961#define USB_I2C_CLKLO_CDLO_Pos (0UL)
8962#define USB_I2C_CLKLO_CDLO_Msk (0xffUL)
8963/* ====================================================== USBCLKCTRL ======================================================= */
8964#define USB_USBCLKCTRL_DEV_CLK_EN_Pos (1UL)
8965#define USB_USBCLKCTRL_DEV_CLK_EN_Msk (0x2UL)
8966#define USB_USBCLKCTRL_PORTSEL_CLK_EN_Pos (3UL)
8967#define USB_USBCLKCTRL_PORTSEL_CLK_EN_Msk (0x8UL)
8968#define USB_USBCLKCTRL_AHB_CLK_EN_Pos (4UL)
8969#define USB_USBCLKCTRL_AHB_CLK_EN_Msk (0x10UL)
8970/* ====================================================== OTGCLKCTRL ======================================================= */
8971#define USB_OTGCLKCTRL_HOST_CLK_EN_Pos (0UL)
8972#define USB_OTGCLKCTRL_HOST_CLK_EN_Msk (0x1UL)
8973#define USB_OTGCLKCTRL_DEV_CLK_EN_Pos (1UL)
8974#define USB_OTGCLKCTRL_DEV_CLK_EN_Msk (0x2UL)
8975#define USB_OTGCLKCTRL_I2C_CLK_EN_Pos (2UL)
8976#define USB_OTGCLKCTRL_I2C_CLK_EN_Msk (0x4UL)
8977#define USB_OTGCLKCTRL_OTG_CLK_EN_Pos (3UL)
8978#define USB_OTGCLKCTRL_OTG_CLK_EN_Msk (0x8UL)
8979#define USB_OTGCLKCTRL_AHB_CLK_EN_Pos (4UL)
8980#define USB_OTGCLKCTRL_AHB_CLK_EN_Msk (0x10UL)
8981/* ======================================================= USBCLKST ======================================================== */
8982#define USB_USBCLKST_DEV_CLK_ON_Pos (1UL)
8983#define USB_USBCLKST_DEV_CLK_ON_Msk (0x2UL)
8984#define USB_USBCLKST_PORTSEL_CLK_ON_Pos (3UL)
8985#define USB_USBCLKST_PORTSEL_CLK_ON_Msk (0x8UL)
8986#define USB_USBCLKST_AHB_CLK_ON_Pos (4UL)
8987#define USB_USBCLKST_AHB_CLK_ON_Msk (0x10UL)
8988/* ======================================================= OTGCLKST ======================================================== */
8989#define USB_OTGCLKST_HOST_CLK_ON_Pos (0UL)
8990#define USB_OTGCLKST_HOST_CLK_ON_Msk (0x1UL)
8991#define USB_OTGCLKST_DEV_CLK_ON_Pos (1UL)
8992#define USB_OTGCLKST_DEV_CLK_ON_Msk (0x2UL)
8993#define USB_OTGCLKST_I2C_CLK_ON_Pos (2UL)
8994#define USB_OTGCLKST_I2C_CLK_ON_Msk (0x4UL)
8995#define USB_OTGCLKST_OTG_CLK_ON_Pos (3UL)
8996#define USB_OTGCLKST_OTG_CLK_ON_Msk (0x8UL)
8997#define USB_OTGCLKST_AHB_CLK_ON_Pos (4UL)
8998#define USB_OTGCLKST_AHB_CLK_ON_Msk (0x10UL)
9001/* =========================================================================================================================== */
9002/* ================ LPC_GPIO ================ */
9003/* =========================================================================================================================== */
9004
9005/* ========================================================= DIR0 ========================================================== */
9006#define GPIO_DIR0_PINDIR0_Pos (0UL)
9007#define GPIO_DIR0_PINDIR0_Msk (0x1UL)
9008#define GPIO_DIR0_PINDIR1_Pos (1UL)
9009#define GPIO_DIR0_PINDIR1_Msk (0x2UL)
9010#define GPIO_DIR0_PINDIR2_Pos (2UL)
9011#define GPIO_DIR0_PINDIR2_Msk (0x4UL)
9012#define GPIO_DIR0_PINDIR3_Pos (3UL)
9013#define GPIO_DIR0_PINDIR3_Msk (0x8UL)
9014#define GPIO_DIR0_PINDIR4_Pos (4UL)
9015#define GPIO_DIR0_PINDIR4_Msk (0x10UL)
9016#define GPIO_DIR0_PINDIR5_Pos (5UL)
9017#define GPIO_DIR0_PINDIR5_Msk (0x20UL)
9018#define GPIO_DIR0_PINDIR6_Pos (6UL)
9019#define GPIO_DIR0_PINDIR6_Msk (0x40UL)
9020#define GPIO_DIR0_PINDIR7_Pos (7UL)
9021#define GPIO_DIR0_PINDIR7_Msk (0x80UL)
9022#define GPIO_DIR0_PINDIR8_Pos (8UL)
9023#define GPIO_DIR0_PINDIR8_Msk (0x100UL)
9024#define GPIO_DIR0_PINDIR9_Pos (9UL)
9025#define GPIO_DIR0_PINDIR9_Msk (0x200UL)
9026#define GPIO_DIR0_PINDIR10_Pos (10UL)
9027#define GPIO_DIR0_PINDIR10_Msk (0x400UL)
9028#define GPIO_DIR0_PINDIR11_Pos (11UL)
9029#define GPIO_DIR0_PINDIR11_Msk (0x800UL)
9030#define GPIO_DIR0_PINDIR12_Pos (12UL)
9031#define GPIO_DIR0_PINDIR12_Msk (0x1000UL)
9032#define GPIO_DIR0_PINDIR13_Pos (13UL)
9033#define GPIO_DIR0_PINDIR13_Msk (0x2000UL)
9034#define GPIO_DIR0_PINDIR14_Pos (14UL)
9035#define GPIO_DIR0_PINDIR14_Msk (0x4000UL)
9036#define GPIO_DIR0_PINDIR15_Pos (15UL)
9037#define GPIO_DIR0_PINDIR15_Msk (0x8000UL)
9038#define GPIO_DIR0_PINDIR16_Pos (16UL)
9039#define GPIO_DIR0_PINDIR16_Msk (0x10000UL)
9040#define GPIO_DIR0_PINDIR17_Pos (17UL)
9041#define GPIO_DIR0_PINDIR17_Msk (0x20000UL)
9042#define GPIO_DIR0_PINDIR18_Pos (18UL)
9043#define GPIO_DIR0_PINDIR18_Msk (0x40000UL)
9044#define GPIO_DIR0_PINDIR19_Pos (19UL)
9045#define GPIO_DIR0_PINDIR19_Msk (0x80000UL)
9046#define GPIO_DIR0_PINDIR20_Pos (20UL)
9047#define GPIO_DIR0_PINDIR20_Msk (0x100000UL)
9048#define GPIO_DIR0_PINDIR21_Pos (21UL)
9049#define GPIO_DIR0_PINDIR21_Msk (0x200000UL)
9050#define GPIO_DIR0_PINDIR22_Pos (22UL)
9051#define GPIO_DIR0_PINDIR22_Msk (0x400000UL)
9052#define GPIO_DIR0_PINDIR23_Pos (23UL)
9053#define GPIO_DIR0_PINDIR23_Msk (0x800000UL)
9054#define GPIO_DIR0_PINDIR24_Pos (24UL)
9055#define GPIO_DIR0_PINDIR24_Msk (0x1000000UL)
9056#define GPIO_DIR0_PINDIR25_Pos (25UL)
9057#define GPIO_DIR0_PINDIR25_Msk (0x2000000UL)
9058#define GPIO_DIR0_PINDIR26_Pos (26UL)
9059#define GPIO_DIR0_PINDIR26_Msk (0x4000000UL)
9060#define GPIO_DIR0_PINDIR27_Pos (27UL)
9061#define GPIO_DIR0_PINDIR27_Msk (0x8000000UL)
9062#define GPIO_DIR0_PINDIR28_Pos (28UL)
9063#define GPIO_DIR0_PINDIR28_Msk (0x10000000UL)
9064#define GPIO_DIR0_PINDIR29_Pos (29UL)
9065#define GPIO_DIR0_PINDIR29_Msk (0x20000000UL)
9066#define GPIO_DIR0_PINDIR30_Pos (30UL)
9067#define GPIO_DIR0_PINDIR30_Msk (0x40000000UL)
9068#define GPIO_DIR0_PINDIR31_Pos (31UL)
9069#define GPIO_DIR0_PINDIR31_Msk (0x80000000UL)
9070/* ========================================================= DIR1 ========================================================== */
9071#define GPIO_DIR1_PINDIR0_Pos (0UL)
9072#define GPIO_DIR1_PINDIR0_Msk (0x1UL)
9073#define GPIO_DIR1_PINDIR1_Pos (1UL)
9074#define GPIO_DIR1_PINDIR1_Msk (0x2UL)
9075#define GPIO_DIR1_PINDIR2_Pos (2UL)
9076#define GPIO_DIR1_PINDIR2_Msk (0x4UL)
9077#define GPIO_DIR1_PINDIR3_Pos (3UL)
9078#define GPIO_DIR1_PINDIR3_Msk (0x8UL)
9079#define GPIO_DIR1_PINDIR4_Pos (4UL)
9080#define GPIO_DIR1_PINDIR4_Msk (0x10UL)
9081#define GPIO_DIR1_PINDIR5_Pos (5UL)
9082#define GPIO_DIR1_PINDIR5_Msk (0x20UL)
9083#define GPIO_DIR1_PINDIR6_Pos (6UL)
9084#define GPIO_DIR1_PINDIR6_Msk (0x40UL)
9085#define GPIO_DIR1_PINDIR7_Pos (7UL)
9086#define GPIO_DIR1_PINDIR7_Msk (0x80UL)
9087#define GPIO_DIR1_PINDIR8_Pos (8UL)
9088#define GPIO_DIR1_PINDIR8_Msk (0x100UL)
9089#define GPIO_DIR1_PINDIR9_Pos (9UL)
9090#define GPIO_DIR1_PINDIR9_Msk (0x200UL)
9091#define GPIO_DIR1_PINDIR10_Pos (10UL)
9092#define GPIO_DIR1_PINDIR10_Msk (0x400UL)
9093#define GPIO_DIR1_PINDIR11_Pos (11UL)
9094#define GPIO_DIR1_PINDIR11_Msk (0x800UL)
9095#define GPIO_DIR1_PINDIR12_Pos (12UL)
9096#define GPIO_DIR1_PINDIR12_Msk (0x1000UL)
9097#define GPIO_DIR1_PINDIR13_Pos (13UL)
9098#define GPIO_DIR1_PINDIR13_Msk (0x2000UL)
9099#define GPIO_DIR1_PINDIR14_Pos (14UL)
9100#define GPIO_DIR1_PINDIR14_Msk (0x4000UL)
9101#define GPIO_DIR1_PINDIR15_Pos (15UL)
9102#define GPIO_DIR1_PINDIR15_Msk (0x8000UL)
9103#define GPIO_DIR1_PINDIR16_Pos (16UL)
9104#define GPIO_DIR1_PINDIR16_Msk (0x10000UL)
9105#define GPIO_DIR1_PINDIR17_Pos (17UL)
9106#define GPIO_DIR1_PINDIR17_Msk (0x20000UL)
9107#define GPIO_DIR1_PINDIR18_Pos (18UL)
9108#define GPIO_DIR1_PINDIR18_Msk (0x40000UL)
9109#define GPIO_DIR1_PINDIR19_Pos (19UL)
9110#define GPIO_DIR1_PINDIR19_Msk (0x80000UL)
9111#define GPIO_DIR1_PINDIR20_Pos (20UL)
9112#define GPIO_DIR1_PINDIR20_Msk (0x100000UL)
9113#define GPIO_DIR1_PINDIR21_Pos (21UL)
9114#define GPIO_DIR1_PINDIR21_Msk (0x200000UL)
9115#define GPIO_DIR1_PINDIR22_Pos (22UL)
9116#define GPIO_DIR1_PINDIR22_Msk (0x400000UL)
9117#define GPIO_DIR1_PINDIR23_Pos (23UL)
9118#define GPIO_DIR1_PINDIR23_Msk (0x800000UL)
9119#define GPIO_DIR1_PINDIR24_Pos (24UL)
9120#define GPIO_DIR1_PINDIR24_Msk (0x1000000UL)
9121#define GPIO_DIR1_PINDIR25_Pos (25UL)
9122#define GPIO_DIR1_PINDIR25_Msk (0x2000000UL)
9123#define GPIO_DIR1_PINDIR26_Pos (26UL)
9124#define GPIO_DIR1_PINDIR26_Msk (0x4000000UL)
9125#define GPIO_DIR1_PINDIR27_Pos (27UL)
9126#define GPIO_DIR1_PINDIR27_Msk (0x8000000UL)
9127#define GPIO_DIR1_PINDIR28_Pos (28UL)
9128#define GPIO_DIR1_PINDIR28_Msk (0x10000000UL)
9129#define GPIO_DIR1_PINDIR29_Pos (29UL)
9130#define GPIO_DIR1_PINDIR29_Msk (0x20000000UL)
9131#define GPIO_DIR1_PINDIR30_Pos (30UL)
9132#define GPIO_DIR1_PINDIR30_Msk (0x40000000UL)
9133#define GPIO_DIR1_PINDIR31_Pos (31UL)
9134#define GPIO_DIR1_PINDIR31_Msk (0x80000000UL)
9135/* ========================================================= DIR2 ========================================================== */
9136#define GPIO_DIR2_PINDIR0_Pos (0UL)
9137#define GPIO_DIR2_PINDIR0_Msk (0x1UL)
9138#define GPIO_DIR2_PINDIR1_Pos (1UL)
9139#define GPIO_DIR2_PINDIR1_Msk (0x2UL)
9140#define GPIO_DIR2_PINDIR2_Pos (2UL)
9141#define GPIO_DIR2_PINDIR2_Msk (0x4UL)
9142#define GPIO_DIR2_PINDIR3_Pos (3UL)
9143#define GPIO_DIR2_PINDIR3_Msk (0x8UL)
9144#define GPIO_DIR2_PINDIR4_Pos (4UL)
9145#define GPIO_DIR2_PINDIR4_Msk (0x10UL)
9146#define GPIO_DIR2_PINDIR5_Pos (5UL)
9147#define GPIO_DIR2_PINDIR5_Msk (0x20UL)
9148#define GPIO_DIR2_PINDIR6_Pos (6UL)
9149#define GPIO_DIR2_PINDIR6_Msk (0x40UL)
9150#define GPIO_DIR2_PINDIR7_Pos (7UL)
9151#define GPIO_DIR2_PINDIR7_Msk (0x80UL)
9152#define GPIO_DIR2_PINDIR8_Pos (8UL)
9153#define GPIO_DIR2_PINDIR8_Msk (0x100UL)
9154#define GPIO_DIR2_PINDIR9_Pos (9UL)
9155#define GPIO_DIR2_PINDIR9_Msk (0x200UL)
9156#define GPIO_DIR2_PINDIR10_Pos (10UL)
9157#define GPIO_DIR2_PINDIR10_Msk (0x400UL)
9158#define GPIO_DIR2_PINDIR11_Pos (11UL)
9159#define GPIO_DIR2_PINDIR11_Msk (0x800UL)
9160#define GPIO_DIR2_PINDIR12_Pos (12UL)
9161#define GPIO_DIR2_PINDIR12_Msk (0x1000UL)
9162#define GPIO_DIR2_PINDIR13_Pos (13UL)
9163#define GPIO_DIR2_PINDIR13_Msk (0x2000UL)
9164#define GPIO_DIR2_PINDIR14_Pos (14UL)
9165#define GPIO_DIR2_PINDIR14_Msk (0x4000UL)
9166#define GPIO_DIR2_PINDIR15_Pos (15UL)
9167#define GPIO_DIR2_PINDIR15_Msk (0x8000UL)
9168#define GPIO_DIR2_PINDIR16_Pos (16UL)
9169#define GPIO_DIR2_PINDIR16_Msk (0x10000UL)
9170#define GPIO_DIR2_PINDIR17_Pos (17UL)
9171#define GPIO_DIR2_PINDIR17_Msk (0x20000UL)
9172#define GPIO_DIR2_PINDIR18_Pos (18UL)
9173#define GPIO_DIR2_PINDIR18_Msk (0x40000UL)
9174#define GPIO_DIR2_PINDIR19_Pos (19UL)
9175#define GPIO_DIR2_PINDIR19_Msk (0x80000UL)
9176#define GPIO_DIR2_PINDIR20_Pos (20UL)
9177#define GPIO_DIR2_PINDIR20_Msk (0x100000UL)
9178#define GPIO_DIR2_PINDIR21_Pos (21UL)
9179#define GPIO_DIR2_PINDIR21_Msk (0x200000UL)
9180#define GPIO_DIR2_PINDIR22_Pos (22UL)
9181#define GPIO_DIR2_PINDIR22_Msk (0x400000UL)
9182#define GPIO_DIR2_PINDIR23_Pos (23UL)
9183#define GPIO_DIR2_PINDIR23_Msk (0x800000UL)
9184#define GPIO_DIR2_PINDIR24_Pos (24UL)
9185#define GPIO_DIR2_PINDIR24_Msk (0x1000000UL)
9186#define GPIO_DIR2_PINDIR25_Pos (25UL)
9187#define GPIO_DIR2_PINDIR25_Msk (0x2000000UL)
9188#define GPIO_DIR2_PINDIR26_Pos (26UL)
9189#define GPIO_DIR2_PINDIR26_Msk (0x4000000UL)
9190#define GPIO_DIR2_PINDIR27_Pos (27UL)
9191#define GPIO_DIR2_PINDIR27_Msk (0x8000000UL)
9192#define GPIO_DIR2_PINDIR28_Pos (28UL)
9193#define GPIO_DIR2_PINDIR28_Msk (0x10000000UL)
9194#define GPIO_DIR2_PINDIR29_Pos (29UL)
9195#define GPIO_DIR2_PINDIR29_Msk (0x20000000UL)
9196#define GPIO_DIR2_PINDIR30_Pos (30UL)
9197#define GPIO_DIR2_PINDIR30_Msk (0x40000000UL)
9198#define GPIO_DIR2_PINDIR31_Pos (31UL)
9199#define GPIO_DIR2_PINDIR31_Msk (0x80000000UL)
9200/* ========================================================= DIR3 ========================================================== */
9201#define GPIO_DIR3_PINDIR0_Pos (0UL)
9202#define GPIO_DIR3_PINDIR0_Msk (0x1UL)
9203#define GPIO_DIR3_PINDIR1_Pos (1UL)
9204#define GPIO_DIR3_PINDIR1_Msk (0x2UL)
9205#define GPIO_DIR3_PINDIR2_Pos (2UL)
9206#define GPIO_DIR3_PINDIR2_Msk (0x4UL)
9207#define GPIO_DIR3_PINDIR3_Pos (3UL)
9208#define GPIO_DIR3_PINDIR3_Msk (0x8UL)
9209#define GPIO_DIR3_PINDIR4_Pos (4UL)
9210#define GPIO_DIR3_PINDIR4_Msk (0x10UL)
9211#define GPIO_DIR3_PINDIR5_Pos (5UL)
9212#define GPIO_DIR3_PINDIR5_Msk (0x20UL)
9213#define GPIO_DIR3_PINDIR6_Pos (6UL)
9214#define GPIO_DIR3_PINDIR6_Msk (0x40UL)
9215#define GPIO_DIR3_PINDIR7_Pos (7UL)
9216#define GPIO_DIR3_PINDIR7_Msk (0x80UL)
9217#define GPIO_DIR3_PINDIR8_Pos (8UL)
9218#define GPIO_DIR3_PINDIR8_Msk (0x100UL)
9219#define GPIO_DIR3_PINDIR9_Pos (9UL)
9220#define GPIO_DIR3_PINDIR9_Msk (0x200UL)
9221#define GPIO_DIR3_PINDIR10_Pos (10UL)
9222#define GPIO_DIR3_PINDIR10_Msk (0x400UL)
9223#define GPIO_DIR3_PINDIR11_Pos (11UL)
9224#define GPIO_DIR3_PINDIR11_Msk (0x800UL)
9225#define GPIO_DIR3_PINDIR12_Pos (12UL)
9226#define GPIO_DIR3_PINDIR12_Msk (0x1000UL)
9227#define GPIO_DIR3_PINDIR13_Pos (13UL)
9228#define GPIO_DIR3_PINDIR13_Msk (0x2000UL)
9229#define GPIO_DIR3_PINDIR14_Pos (14UL)
9230#define GPIO_DIR3_PINDIR14_Msk (0x4000UL)
9231#define GPIO_DIR3_PINDIR15_Pos (15UL)
9232#define GPIO_DIR3_PINDIR15_Msk (0x8000UL)
9233#define GPIO_DIR3_PINDIR16_Pos (16UL)
9234#define GPIO_DIR3_PINDIR16_Msk (0x10000UL)
9235#define GPIO_DIR3_PINDIR17_Pos (17UL)
9236#define GPIO_DIR3_PINDIR17_Msk (0x20000UL)
9237#define GPIO_DIR3_PINDIR18_Pos (18UL)
9238#define GPIO_DIR3_PINDIR18_Msk (0x40000UL)
9239#define GPIO_DIR3_PINDIR19_Pos (19UL)
9240#define GPIO_DIR3_PINDIR19_Msk (0x80000UL)
9241#define GPIO_DIR3_PINDIR20_Pos (20UL)
9242#define GPIO_DIR3_PINDIR20_Msk (0x100000UL)
9243#define GPIO_DIR3_PINDIR21_Pos (21UL)
9244#define GPIO_DIR3_PINDIR21_Msk (0x200000UL)
9245#define GPIO_DIR3_PINDIR22_Pos (22UL)
9246#define GPIO_DIR3_PINDIR22_Msk (0x400000UL)
9247#define GPIO_DIR3_PINDIR23_Pos (23UL)
9248#define GPIO_DIR3_PINDIR23_Msk (0x800000UL)
9249#define GPIO_DIR3_PINDIR24_Pos (24UL)
9250#define GPIO_DIR3_PINDIR24_Msk (0x1000000UL)
9251#define GPIO_DIR3_PINDIR25_Pos (25UL)
9252#define GPIO_DIR3_PINDIR25_Msk (0x2000000UL)
9253#define GPIO_DIR3_PINDIR26_Pos (26UL)
9254#define GPIO_DIR3_PINDIR26_Msk (0x4000000UL)
9255#define GPIO_DIR3_PINDIR27_Pos (27UL)
9256#define GPIO_DIR3_PINDIR27_Msk (0x8000000UL)
9257#define GPIO_DIR3_PINDIR28_Pos (28UL)
9258#define GPIO_DIR3_PINDIR28_Msk (0x10000000UL)
9259#define GPIO_DIR3_PINDIR29_Pos (29UL)
9260#define GPIO_DIR3_PINDIR29_Msk (0x20000000UL)
9261#define GPIO_DIR3_PINDIR30_Pos (30UL)
9262#define GPIO_DIR3_PINDIR30_Msk (0x40000000UL)
9263#define GPIO_DIR3_PINDIR31_Pos (31UL)
9264#define GPIO_DIR3_PINDIR31_Msk (0x80000000UL)
9265/* ========================================================= DIR4 ========================================================== */
9266#define GPIO_DIR4_PINDIR0_Pos (0UL)
9267#define GPIO_DIR4_PINDIR0_Msk (0x1UL)
9268#define GPIO_DIR4_PINDIR1_Pos (1UL)
9269#define GPIO_DIR4_PINDIR1_Msk (0x2UL)
9270#define GPIO_DIR4_PINDIR2_Pos (2UL)
9271#define GPIO_DIR4_PINDIR2_Msk (0x4UL)
9272#define GPIO_DIR4_PINDIR3_Pos (3UL)
9273#define GPIO_DIR4_PINDIR3_Msk (0x8UL)
9274#define GPIO_DIR4_PINDIR4_Pos (4UL)
9275#define GPIO_DIR4_PINDIR4_Msk (0x10UL)
9276#define GPIO_DIR4_PINDIR5_Pos (5UL)
9277#define GPIO_DIR4_PINDIR5_Msk (0x20UL)
9278#define GPIO_DIR4_PINDIR6_Pos (6UL)
9279#define GPIO_DIR4_PINDIR6_Msk (0x40UL)
9280#define GPIO_DIR4_PINDIR7_Pos (7UL)
9281#define GPIO_DIR4_PINDIR7_Msk (0x80UL)
9282#define GPIO_DIR4_PINDIR8_Pos (8UL)
9283#define GPIO_DIR4_PINDIR8_Msk (0x100UL)
9284#define GPIO_DIR4_PINDIR9_Pos (9UL)
9285#define GPIO_DIR4_PINDIR9_Msk (0x200UL)
9286#define GPIO_DIR4_PINDIR10_Pos (10UL)
9287#define GPIO_DIR4_PINDIR10_Msk (0x400UL)
9288#define GPIO_DIR4_PINDIR11_Pos (11UL)
9289#define GPIO_DIR4_PINDIR11_Msk (0x800UL)
9290#define GPIO_DIR4_PINDIR12_Pos (12UL)
9291#define GPIO_DIR4_PINDIR12_Msk (0x1000UL)
9292#define GPIO_DIR4_PINDIR13_Pos (13UL)
9293#define GPIO_DIR4_PINDIR13_Msk (0x2000UL)
9294#define GPIO_DIR4_PINDIR14_Pos (14UL)
9295#define GPIO_DIR4_PINDIR14_Msk (0x4000UL)
9296#define GPIO_DIR4_PINDIR15_Pos (15UL)
9297#define GPIO_DIR4_PINDIR15_Msk (0x8000UL)
9298#define GPIO_DIR4_PINDIR16_Pos (16UL)
9299#define GPIO_DIR4_PINDIR16_Msk (0x10000UL)
9300#define GPIO_DIR4_PINDIR17_Pos (17UL)
9301#define GPIO_DIR4_PINDIR17_Msk (0x20000UL)
9302#define GPIO_DIR4_PINDIR18_Pos (18UL)
9303#define GPIO_DIR4_PINDIR18_Msk (0x40000UL)
9304#define GPIO_DIR4_PINDIR19_Pos (19UL)
9305#define GPIO_DIR4_PINDIR19_Msk (0x80000UL)
9306#define GPIO_DIR4_PINDIR20_Pos (20UL)
9307#define GPIO_DIR4_PINDIR20_Msk (0x100000UL)
9308#define GPIO_DIR4_PINDIR21_Pos (21UL)
9309#define GPIO_DIR4_PINDIR21_Msk (0x200000UL)
9310#define GPIO_DIR4_PINDIR22_Pos (22UL)
9311#define GPIO_DIR4_PINDIR22_Msk (0x400000UL)
9312#define GPIO_DIR4_PINDIR23_Pos (23UL)
9313#define GPIO_DIR4_PINDIR23_Msk (0x800000UL)
9314#define GPIO_DIR4_PINDIR24_Pos (24UL)
9315#define GPIO_DIR4_PINDIR24_Msk (0x1000000UL)
9316#define GPIO_DIR4_PINDIR25_Pos (25UL)
9317#define GPIO_DIR4_PINDIR25_Msk (0x2000000UL)
9318#define GPIO_DIR4_PINDIR26_Pos (26UL)
9319#define GPIO_DIR4_PINDIR26_Msk (0x4000000UL)
9320#define GPIO_DIR4_PINDIR27_Pos (27UL)
9321#define GPIO_DIR4_PINDIR27_Msk (0x8000000UL)
9322#define GPIO_DIR4_PINDIR28_Pos (28UL)
9323#define GPIO_DIR4_PINDIR28_Msk (0x10000000UL)
9324#define GPIO_DIR4_PINDIR29_Pos (29UL)
9325#define GPIO_DIR4_PINDIR29_Msk (0x20000000UL)
9326#define GPIO_DIR4_PINDIR30_Pos (30UL)
9327#define GPIO_DIR4_PINDIR30_Msk (0x40000000UL)
9328#define GPIO_DIR4_PINDIR31_Pos (31UL)
9329#define GPIO_DIR4_PINDIR31_Msk (0x80000000UL)
9330/* ========================================================= MASK0 ========================================================= */
9331#define GPIO_MASK0_PINMASK0_Pos (0UL)
9332#define GPIO_MASK0_PINMASK0_Msk (0x1UL)
9333#define GPIO_MASK0_PINMASK1_Pos (1UL)
9334#define GPIO_MASK0_PINMASK1_Msk (0x2UL)
9335#define GPIO_MASK0_PINMASK2_Pos (2UL)
9336#define GPIO_MASK0_PINMASK2_Msk (0x4UL)
9337#define GPIO_MASK0_PINMASK3_Pos (3UL)
9338#define GPIO_MASK0_PINMASK3_Msk (0x8UL)
9339#define GPIO_MASK0_PINMASK4_Pos (4UL)
9340#define GPIO_MASK0_PINMASK4_Msk (0x10UL)
9341#define GPIO_MASK0_PINMASK5_Pos (5UL)
9342#define GPIO_MASK0_PINMASK5_Msk (0x20UL)
9343#define GPIO_MASK0_PINMASK6_Pos (6UL)
9344#define GPIO_MASK0_PINMASK6_Msk (0x40UL)
9345#define GPIO_MASK0_PINMASK7_Pos (7UL)
9346#define GPIO_MASK0_PINMASK7_Msk (0x80UL)
9347#define GPIO_MASK0_PINMASK8_Pos (8UL)
9348#define GPIO_MASK0_PINMASK8_Msk (0x100UL)
9349#define GPIO_MASK0_PINMASK9_Pos (9UL)
9350#define GPIO_MASK0_PINMASK9_Msk (0x200UL)
9351#define GPIO_MASK0_PINMASK10_Pos (10UL)
9352#define GPIO_MASK0_PINMASK10_Msk (0x400UL)
9353#define GPIO_MASK0_PINMASK11_Pos (11UL)
9354#define GPIO_MASK0_PINMASK11_Msk (0x800UL)
9355#define GPIO_MASK0_PINMASK12_Pos (12UL)
9356#define GPIO_MASK0_PINMASK12_Msk (0x1000UL)
9357#define GPIO_MASK0_PINMASK13_Pos (13UL)
9358#define GPIO_MASK0_PINMASK13_Msk (0x2000UL)
9359#define GPIO_MASK0_PINMASK14_Pos (14UL)
9360#define GPIO_MASK0_PINMASK14_Msk (0x4000UL)
9361#define GPIO_MASK0_PINMASK15_Pos (15UL)
9362#define GPIO_MASK0_PINMASK15_Msk (0x8000UL)
9363#define GPIO_MASK0_PINMASK16_Pos (16UL)
9364#define GPIO_MASK0_PINMASK16_Msk (0x10000UL)
9365#define GPIO_MASK0_PINMASK17_Pos (17UL)
9366#define GPIO_MASK0_PINMASK17_Msk (0x20000UL)
9367#define GPIO_MASK0_PINMASK18_Pos (18UL)
9368#define GPIO_MASK0_PINMASK18_Msk (0x40000UL)
9369#define GPIO_MASK0_PINMASK19_Pos (19UL)
9370#define GPIO_MASK0_PINMASK19_Msk (0x80000UL)
9371#define GPIO_MASK0_PINMASK20_Pos (20UL)
9372#define GPIO_MASK0_PINMASK20_Msk (0x100000UL)
9373#define GPIO_MASK0_PINMASK21_Pos (21UL)
9374#define GPIO_MASK0_PINMASK21_Msk (0x200000UL)
9375#define GPIO_MASK0_PINMASK22_Pos (22UL)
9376#define GPIO_MASK0_PINMASK22_Msk (0x400000UL)
9377#define GPIO_MASK0_PINMASK23_Pos (23UL)
9378#define GPIO_MASK0_PINMASK23_Msk (0x800000UL)
9379#define GPIO_MASK0_PINMASK24_Pos (24UL)
9380#define GPIO_MASK0_PINMASK24_Msk (0x1000000UL)
9381#define GPIO_MASK0_PINMASK25_Pos (25UL)
9382#define GPIO_MASK0_PINMASK25_Msk (0x2000000UL)
9383#define GPIO_MASK0_PINMASK26_Pos (26UL)
9384#define GPIO_MASK0_PINMASK26_Msk (0x4000000UL)
9385#define GPIO_MASK0_PINMASK27_Pos (27UL)
9386#define GPIO_MASK0_PINMASK27_Msk (0x8000000UL)
9387#define GPIO_MASK0_PINMASK28_Pos (28UL)
9388#define GPIO_MASK0_PINMASK28_Msk (0x10000000UL)
9389#define GPIO_MASK0_PINMASK29_Pos (29UL)
9390#define GPIO_MASK0_PINMASK29_Msk (0x20000000UL)
9391#define GPIO_MASK0_PINMASK30_Pos (30UL)
9392#define GPIO_MASK0_PINMASK30_Msk (0x40000000UL)
9393#define GPIO_MASK0_PINMASK31_Pos (31UL)
9394#define GPIO_MASK0_PINMASK31_Msk (0x80000000UL)
9395/* ========================================================= MASK1 ========================================================= */
9396#define GPIO_MASK1_PINMASK0_Pos (0UL)
9397#define GPIO_MASK1_PINMASK0_Msk (0x1UL)
9398#define GPIO_MASK1_PINMASK1_Pos (1UL)
9399#define GPIO_MASK1_PINMASK1_Msk (0x2UL)
9400#define GPIO_MASK1_PINMASK2_Pos (2UL)
9401#define GPIO_MASK1_PINMASK2_Msk (0x4UL)
9402#define GPIO_MASK1_PINMASK3_Pos (3UL)
9403#define GPIO_MASK1_PINMASK3_Msk (0x8UL)
9404#define GPIO_MASK1_PINMASK4_Pos (4UL)
9405#define GPIO_MASK1_PINMASK4_Msk (0x10UL)
9406#define GPIO_MASK1_PINMASK5_Pos (5UL)
9407#define GPIO_MASK1_PINMASK5_Msk (0x20UL)
9408#define GPIO_MASK1_PINMASK6_Pos (6UL)
9409#define GPIO_MASK1_PINMASK6_Msk (0x40UL)
9410#define GPIO_MASK1_PINMASK7_Pos (7UL)
9411#define GPIO_MASK1_PINMASK7_Msk (0x80UL)
9412#define GPIO_MASK1_PINMASK8_Pos (8UL)
9413#define GPIO_MASK1_PINMASK8_Msk (0x100UL)
9414#define GPIO_MASK1_PINMASK9_Pos (9UL)
9415#define GPIO_MASK1_PINMASK9_Msk (0x200UL)
9416#define GPIO_MASK1_PINMASK10_Pos (10UL)
9417#define GPIO_MASK1_PINMASK10_Msk (0x400UL)
9418#define GPIO_MASK1_PINMASK11_Pos (11UL)
9419#define GPIO_MASK1_PINMASK11_Msk (0x800UL)
9420#define GPIO_MASK1_PINMASK12_Pos (12UL)
9421#define GPIO_MASK1_PINMASK12_Msk (0x1000UL)
9422#define GPIO_MASK1_PINMASK13_Pos (13UL)
9423#define GPIO_MASK1_PINMASK13_Msk (0x2000UL)
9424#define GPIO_MASK1_PINMASK14_Pos (14UL)
9425#define GPIO_MASK1_PINMASK14_Msk (0x4000UL)
9426#define GPIO_MASK1_PINMASK15_Pos (15UL)
9427#define GPIO_MASK1_PINMASK15_Msk (0x8000UL)
9428#define GPIO_MASK1_PINMASK16_Pos (16UL)
9429#define GPIO_MASK1_PINMASK16_Msk (0x10000UL)
9430#define GPIO_MASK1_PINMASK17_Pos (17UL)
9431#define GPIO_MASK1_PINMASK17_Msk (0x20000UL)
9432#define GPIO_MASK1_PINMASK18_Pos (18UL)
9433#define GPIO_MASK1_PINMASK18_Msk (0x40000UL)
9434#define GPIO_MASK1_PINMASK19_Pos (19UL)
9435#define GPIO_MASK1_PINMASK19_Msk (0x80000UL)
9436#define GPIO_MASK1_PINMASK20_Pos (20UL)
9437#define GPIO_MASK1_PINMASK20_Msk (0x100000UL)
9438#define GPIO_MASK1_PINMASK21_Pos (21UL)
9439#define GPIO_MASK1_PINMASK21_Msk (0x200000UL)
9440#define GPIO_MASK1_PINMASK22_Pos (22UL)
9441#define GPIO_MASK1_PINMASK22_Msk (0x400000UL)
9442#define GPIO_MASK1_PINMASK23_Pos (23UL)
9443#define GPIO_MASK1_PINMASK23_Msk (0x800000UL)
9444#define GPIO_MASK1_PINMASK24_Pos (24UL)
9445#define GPIO_MASK1_PINMASK24_Msk (0x1000000UL)
9446#define GPIO_MASK1_PINMASK25_Pos (25UL)
9447#define GPIO_MASK1_PINMASK25_Msk (0x2000000UL)
9448#define GPIO_MASK1_PINMASK26_Pos (26UL)
9449#define GPIO_MASK1_PINMASK26_Msk (0x4000000UL)
9450#define GPIO_MASK1_PINMASK27_Pos (27UL)
9451#define GPIO_MASK1_PINMASK27_Msk (0x8000000UL)
9452#define GPIO_MASK1_PINMASK28_Pos (28UL)
9453#define GPIO_MASK1_PINMASK28_Msk (0x10000000UL)
9454#define GPIO_MASK1_PINMASK29_Pos (29UL)
9455#define GPIO_MASK1_PINMASK29_Msk (0x20000000UL)
9456#define GPIO_MASK1_PINMASK30_Pos (30UL)
9457#define GPIO_MASK1_PINMASK30_Msk (0x40000000UL)
9458#define GPIO_MASK1_PINMASK31_Pos (31UL)
9459#define GPIO_MASK1_PINMASK31_Msk (0x80000000UL)
9460/* ========================================================= MASK2 ========================================================= */
9461#define GPIO_MASK2_PINMASK0_Pos (0UL)
9462#define GPIO_MASK2_PINMASK0_Msk (0x1UL)
9463#define GPIO_MASK2_PINMASK1_Pos (1UL)
9464#define GPIO_MASK2_PINMASK1_Msk (0x2UL)
9465#define GPIO_MASK2_PINMASK2_Pos (2UL)
9466#define GPIO_MASK2_PINMASK2_Msk (0x4UL)
9467#define GPIO_MASK2_PINMASK3_Pos (3UL)
9468#define GPIO_MASK2_PINMASK3_Msk (0x8UL)
9469#define GPIO_MASK2_PINMASK4_Pos (4UL)
9470#define GPIO_MASK2_PINMASK4_Msk (0x10UL)
9471#define GPIO_MASK2_PINMASK5_Pos (5UL)
9472#define GPIO_MASK2_PINMASK5_Msk (0x20UL)
9473#define GPIO_MASK2_PINMASK6_Pos (6UL)
9474#define GPIO_MASK2_PINMASK6_Msk (0x40UL)
9475#define GPIO_MASK2_PINMASK7_Pos (7UL)
9476#define GPIO_MASK2_PINMASK7_Msk (0x80UL)
9477#define GPIO_MASK2_PINMASK8_Pos (8UL)
9478#define GPIO_MASK2_PINMASK8_Msk (0x100UL)
9479#define GPIO_MASK2_PINMASK9_Pos (9UL)
9480#define GPIO_MASK2_PINMASK9_Msk (0x200UL)
9481#define GPIO_MASK2_PINMASK10_Pos (10UL)
9482#define GPIO_MASK2_PINMASK10_Msk (0x400UL)
9483#define GPIO_MASK2_PINMASK11_Pos (11UL)
9484#define GPIO_MASK2_PINMASK11_Msk (0x800UL)
9485#define GPIO_MASK2_PINMASK12_Pos (12UL)
9486#define GPIO_MASK2_PINMASK12_Msk (0x1000UL)
9487#define GPIO_MASK2_PINMASK13_Pos (13UL)
9488#define GPIO_MASK2_PINMASK13_Msk (0x2000UL)
9489#define GPIO_MASK2_PINMASK14_Pos (14UL)
9490#define GPIO_MASK2_PINMASK14_Msk (0x4000UL)
9491#define GPIO_MASK2_PINMASK15_Pos (15UL)
9492#define GPIO_MASK2_PINMASK15_Msk (0x8000UL)
9493#define GPIO_MASK2_PINMASK16_Pos (16UL)
9494#define GPIO_MASK2_PINMASK16_Msk (0x10000UL)
9495#define GPIO_MASK2_PINMASK17_Pos (17UL)
9496#define GPIO_MASK2_PINMASK17_Msk (0x20000UL)
9497#define GPIO_MASK2_PINMASK18_Pos (18UL)
9498#define GPIO_MASK2_PINMASK18_Msk (0x40000UL)
9499#define GPIO_MASK2_PINMASK19_Pos (19UL)
9500#define GPIO_MASK2_PINMASK19_Msk (0x80000UL)
9501#define GPIO_MASK2_PINMASK20_Pos (20UL)
9502#define GPIO_MASK2_PINMASK20_Msk (0x100000UL)
9503#define GPIO_MASK2_PINMASK21_Pos (21UL)
9504#define GPIO_MASK2_PINMASK21_Msk (0x200000UL)
9505#define GPIO_MASK2_PINMASK22_Pos (22UL)
9506#define GPIO_MASK2_PINMASK22_Msk (0x400000UL)
9507#define GPIO_MASK2_PINMASK23_Pos (23UL)
9508#define GPIO_MASK2_PINMASK23_Msk (0x800000UL)
9509#define GPIO_MASK2_PINMASK24_Pos (24UL)
9510#define GPIO_MASK2_PINMASK24_Msk (0x1000000UL)
9511#define GPIO_MASK2_PINMASK25_Pos (25UL)
9512#define GPIO_MASK2_PINMASK25_Msk (0x2000000UL)
9513#define GPIO_MASK2_PINMASK26_Pos (26UL)
9514#define GPIO_MASK2_PINMASK26_Msk (0x4000000UL)
9515#define GPIO_MASK2_PINMASK27_Pos (27UL)
9516#define GPIO_MASK2_PINMASK27_Msk (0x8000000UL)
9517#define GPIO_MASK2_PINMASK28_Pos (28UL)
9518#define GPIO_MASK2_PINMASK28_Msk (0x10000000UL)
9519#define GPIO_MASK2_PINMASK29_Pos (29UL)
9520#define GPIO_MASK2_PINMASK29_Msk (0x20000000UL)
9521#define GPIO_MASK2_PINMASK30_Pos (30UL)
9522#define GPIO_MASK2_PINMASK30_Msk (0x40000000UL)
9523#define GPIO_MASK2_PINMASK31_Pos (31UL)
9524#define GPIO_MASK2_PINMASK31_Msk (0x80000000UL)
9525/* ========================================================= MASK3 ========================================================= */
9526#define GPIO_MASK3_PINMASK0_Pos (0UL)
9527#define GPIO_MASK3_PINMASK0_Msk (0x1UL)
9528#define GPIO_MASK3_PINMASK1_Pos (1UL)
9529#define GPIO_MASK3_PINMASK1_Msk (0x2UL)
9530#define GPIO_MASK3_PINMASK2_Pos (2UL)
9531#define GPIO_MASK3_PINMASK2_Msk (0x4UL)
9532#define GPIO_MASK3_PINMASK3_Pos (3UL)
9533#define GPIO_MASK3_PINMASK3_Msk (0x8UL)
9534#define GPIO_MASK3_PINMASK4_Pos (4UL)
9535#define GPIO_MASK3_PINMASK4_Msk (0x10UL)
9536#define GPIO_MASK3_PINMASK5_Pos (5UL)
9537#define GPIO_MASK3_PINMASK5_Msk (0x20UL)
9538#define GPIO_MASK3_PINMASK6_Pos (6UL)
9539#define GPIO_MASK3_PINMASK6_Msk (0x40UL)
9540#define GPIO_MASK3_PINMASK7_Pos (7UL)
9541#define GPIO_MASK3_PINMASK7_Msk (0x80UL)
9542#define GPIO_MASK3_PINMASK8_Pos (8UL)
9543#define GPIO_MASK3_PINMASK8_Msk (0x100UL)
9544#define GPIO_MASK3_PINMASK9_Pos (9UL)
9545#define GPIO_MASK3_PINMASK9_Msk (0x200UL)
9546#define GPIO_MASK3_PINMASK10_Pos (10UL)
9547#define GPIO_MASK3_PINMASK10_Msk (0x400UL)
9548#define GPIO_MASK3_PINMASK11_Pos (11UL)
9549#define GPIO_MASK3_PINMASK11_Msk (0x800UL)
9550#define GPIO_MASK3_PINMASK12_Pos (12UL)
9551#define GPIO_MASK3_PINMASK12_Msk (0x1000UL)
9552#define GPIO_MASK3_PINMASK13_Pos (13UL)
9553#define GPIO_MASK3_PINMASK13_Msk (0x2000UL)
9554#define GPIO_MASK3_PINMASK14_Pos (14UL)
9555#define GPIO_MASK3_PINMASK14_Msk (0x4000UL)
9556#define GPIO_MASK3_PINMASK15_Pos (15UL)
9557#define GPIO_MASK3_PINMASK15_Msk (0x8000UL)
9558#define GPIO_MASK3_PINMASK16_Pos (16UL)
9559#define GPIO_MASK3_PINMASK16_Msk (0x10000UL)
9560#define GPIO_MASK3_PINMASK17_Pos (17UL)
9561#define GPIO_MASK3_PINMASK17_Msk (0x20000UL)
9562#define GPIO_MASK3_PINMASK18_Pos (18UL)
9563#define GPIO_MASK3_PINMASK18_Msk (0x40000UL)
9564#define GPIO_MASK3_PINMASK19_Pos (19UL)
9565#define GPIO_MASK3_PINMASK19_Msk (0x80000UL)
9566#define GPIO_MASK3_PINMASK20_Pos (20UL)
9567#define GPIO_MASK3_PINMASK20_Msk (0x100000UL)
9568#define GPIO_MASK3_PINMASK21_Pos (21UL)
9569#define GPIO_MASK3_PINMASK21_Msk (0x200000UL)
9570#define GPIO_MASK3_PINMASK22_Pos (22UL)
9571#define GPIO_MASK3_PINMASK22_Msk (0x400000UL)
9572#define GPIO_MASK3_PINMASK23_Pos (23UL)
9573#define GPIO_MASK3_PINMASK23_Msk (0x800000UL)
9574#define GPIO_MASK3_PINMASK24_Pos (24UL)
9575#define GPIO_MASK3_PINMASK24_Msk (0x1000000UL)
9576#define GPIO_MASK3_PINMASK25_Pos (25UL)
9577#define GPIO_MASK3_PINMASK25_Msk (0x2000000UL)
9578#define GPIO_MASK3_PINMASK26_Pos (26UL)
9579#define GPIO_MASK3_PINMASK26_Msk (0x4000000UL)
9580#define GPIO_MASK3_PINMASK27_Pos (27UL)
9581#define GPIO_MASK3_PINMASK27_Msk (0x8000000UL)
9582#define GPIO_MASK3_PINMASK28_Pos (28UL)
9583#define GPIO_MASK3_PINMASK28_Msk (0x10000000UL)
9584#define GPIO_MASK3_PINMASK29_Pos (29UL)
9585#define GPIO_MASK3_PINMASK29_Msk (0x20000000UL)
9586#define GPIO_MASK3_PINMASK30_Pos (30UL)
9587#define GPIO_MASK3_PINMASK30_Msk (0x40000000UL)
9588#define GPIO_MASK3_PINMASK31_Pos (31UL)
9589#define GPIO_MASK3_PINMASK31_Msk (0x80000000UL)
9590/* ========================================================= MASK4 ========================================================= */
9591#define GPIO_MASK4_PINMASK0_Pos (0UL)
9592#define GPIO_MASK4_PINMASK0_Msk (0x1UL)
9593#define GPIO_MASK4_PINMASK1_Pos (1UL)
9594#define GPIO_MASK4_PINMASK1_Msk (0x2UL)
9595#define GPIO_MASK4_PINMASK2_Pos (2UL)
9596#define GPIO_MASK4_PINMASK2_Msk (0x4UL)
9597#define GPIO_MASK4_PINMASK3_Pos (3UL)
9598#define GPIO_MASK4_PINMASK3_Msk (0x8UL)
9599#define GPIO_MASK4_PINMASK4_Pos (4UL)
9600#define GPIO_MASK4_PINMASK4_Msk (0x10UL)
9601#define GPIO_MASK4_PINMASK5_Pos (5UL)
9602#define GPIO_MASK4_PINMASK5_Msk (0x20UL)
9603#define GPIO_MASK4_PINMASK6_Pos (6UL)
9604#define GPIO_MASK4_PINMASK6_Msk (0x40UL)
9605#define GPIO_MASK4_PINMASK7_Pos (7UL)
9606#define GPIO_MASK4_PINMASK7_Msk (0x80UL)
9607#define GPIO_MASK4_PINMASK8_Pos (8UL)
9608#define GPIO_MASK4_PINMASK8_Msk (0x100UL)
9609#define GPIO_MASK4_PINMASK9_Pos (9UL)
9610#define GPIO_MASK4_PINMASK9_Msk (0x200UL)
9611#define GPIO_MASK4_PINMASK10_Pos (10UL)
9612#define GPIO_MASK4_PINMASK10_Msk (0x400UL)
9613#define GPIO_MASK4_PINMASK11_Pos (11UL)
9614#define GPIO_MASK4_PINMASK11_Msk (0x800UL)
9615#define GPIO_MASK4_PINMASK12_Pos (12UL)
9616#define GPIO_MASK4_PINMASK12_Msk (0x1000UL)
9617#define GPIO_MASK4_PINMASK13_Pos (13UL)
9618#define GPIO_MASK4_PINMASK13_Msk (0x2000UL)
9619#define GPIO_MASK4_PINMASK14_Pos (14UL)
9620#define GPIO_MASK4_PINMASK14_Msk (0x4000UL)
9621#define GPIO_MASK4_PINMASK15_Pos (15UL)
9622#define GPIO_MASK4_PINMASK15_Msk (0x8000UL)
9623#define GPIO_MASK4_PINMASK16_Pos (16UL)
9624#define GPIO_MASK4_PINMASK16_Msk (0x10000UL)
9625#define GPIO_MASK4_PINMASK17_Pos (17UL)
9626#define GPIO_MASK4_PINMASK17_Msk (0x20000UL)
9627#define GPIO_MASK4_PINMASK18_Pos (18UL)
9628#define GPIO_MASK4_PINMASK18_Msk (0x40000UL)
9629#define GPIO_MASK4_PINMASK19_Pos (19UL)
9630#define GPIO_MASK4_PINMASK19_Msk (0x80000UL)
9631#define GPIO_MASK4_PINMASK20_Pos (20UL)
9632#define GPIO_MASK4_PINMASK20_Msk (0x100000UL)
9633#define GPIO_MASK4_PINMASK21_Pos (21UL)
9634#define GPIO_MASK4_PINMASK21_Msk (0x200000UL)
9635#define GPIO_MASK4_PINMASK22_Pos (22UL)
9636#define GPIO_MASK4_PINMASK22_Msk (0x400000UL)
9637#define GPIO_MASK4_PINMASK23_Pos (23UL)
9638#define GPIO_MASK4_PINMASK23_Msk (0x800000UL)
9639#define GPIO_MASK4_PINMASK24_Pos (24UL)
9640#define GPIO_MASK4_PINMASK24_Msk (0x1000000UL)
9641#define GPIO_MASK4_PINMASK25_Pos (25UL)
9642#define GPIO_MASK4_PINMASK25_Msk (0x2000000UL)
9643#define GPIO_MASK4_PINMASK26_Pos (26UL)
9644#define GPIO_MASK4_PINMASK26_Msk (0x4000000UL)
9645#define GPIO_MASK4_PINMASK27_Pos (27UL)
9646#define GPIO_MASK4_PINMASK27_Msk (0x8000000UL)
9647#define GPIO_MASK4_PINMASK28_Pos (28UL)
9648#define GPIO_MASK4_PINMASK28_Msk (0x10000000UL)
9649#define GPIO_MASK4_PINMASK29_Pos (29UL)
9650#define GPIO_MASK4_PINMASK29_Msk (0x20000000UL)
9651#define GPIO_MASK4_PINMASK30_Pos (30UL)
9652#define GPIO_MASK4_PINMASK30_Msk (0x40000000UL)
9653#define GPIO_MASK4_PINMASK31_Pos (31UL)
9654#define GPIO_MASK4_PINMASK31_Msk (0x80000000UL)
9655/* ========================================================= PIN0 ========================================================== */
9656#define GPIO_PIN0_PINVAL0_Pos (0UL)
9657#define GPIO_PIN0_PINVAL0_Msk (0x1UL)
9658#define GPIO_PIN0_PINVAL1_Pos (1UL)
9659#define GPIO_PIN0_PINVAL1_Msk (0x2UL)
9660#define GPIO_PIN0_PINVAL2_Pos (2UL)
9661#define GPIO_PIN0_PINVAL2_Msk (0x4UL)
9662#define GPIO_PIN0_PINVAL3_Pos (3UL)
9663#define GPIO_PIN0_PINVAL3_Msk (0x8UL)
9664#define GPIO_PIN0_PINVAL4_Pos (4UL)
9665#define GPIO_PIN0_PINVAL4_Msk (0x10UL)
9666#define GPIO_PIN0_PINVAL5_Pos (5UL)
9667#define GPIO_PIN0_PINVAL5_Msk (0x20UL)
9668#define GPIO_PIN0_PINVAL6_Pos (6UL)
9669#define GPIO_PIN0_PINVAL6_Msk (0x40UL)
9670#define GPIO_PIN0_PINVAL7_Pos (7UL)
9671#define GPIO_PIN0_PINVAL7_Msk (0x80UL)
9672#define GPIO_PIN0_PINVAL8_Pos (8UL)
9673#define GPIO_PIN0_PINVAL8_Msk (0x100UL)
9674#define GPIO_PIN0_PINVAL9_Pos (9UL)
9675#define GPIO_PIN0_PINVAL9_Msk (0x200UL)
9676#define GPIO_PIN0_PINVAL10_Pos (10UL)
9677#define GPIO_PIN0_PINVAL10_Msk (0x400UL)
9678#define GPIO_PIN0_PINVAL11_Pos (11UL)
9679#define GPIO_PIN0_PINVAL11_Msk (0x800UL)
9680#define GPIO_PIN0_PINVAL12_Pos (12UL)
9681#define GPIO_PIN0_PINVAL12_Msk (0x1000UL)
9682#define GPIO_PIN0_PINVAL13_Pos (13UL)
9683#define GPIO_PIN0_PINVAL13_Msk (0x2000UL)
9684#define GPIO_PIN0_PINVAL14_Pos (14UL)
9685#define GPIO_PIN0_PINVAL14_Msk (0x4000UL)
9686#define GPIO_PIN0_PINVAL15_Pos (15UL)
9687#define GPIO_PIN0_PINVAL15_Msk (0x8000UL)
9688#define GPIO_PIN0_PINVAL16_Pos (16UL)
9689#define GPIO_PIN0_PINVAL16_Msk (0x10000UL)
9690#define GPIO_PIN0_PINVAL17_Pos (17UL)
9691#define GPIO_PIN0_PINVAL17_Msk (0x20000UL)
9692#define GPIO_PIN0_PINVAL18_Pos (18UL)
9693#define GPIO_PIN0_PINVAL18_Msk (0x40000UL)
9694#define GPIO_PIN0_PINVAL19_Pos (19UL)
9695#define GPIO_PIN0_PINVAL19_Msk (0x80000UL)
9696#define GPIO_PIN0_PINVAL20_Pos (20UL)
9697#define GPIO_PIN0_PINVAL20_Msk (0x100000UL)
9698#define GPIO_PIN0_PINVAL21_Pos (21UL)
9699#define GPIO_PIN0_PINVAL21_Msk (0x200000UL)
9700#define GPIO_PIN0_PINVAL22_Pos (22UL)
9701#define GPIO_PIN0_PINVAL22_Msk (0x400000UL)
9702#define GPIO_PIN0_PINVAL23_Pos (23UL)
9703#define GPIO_PIN0_PINVAL23_Msk (0x800000UL)
9704#define GPIO_PIN0_PINVAL24_Pos (24UL)
9705#define GPIO_PIN0_PINVAL24_Msk (0x1000000UL)
9706#define GPIO_PIN0_PINVAL25_Pos (25UL)
9707#define GPIO_PIN0_PINVAL25_Msk (0x2000000UL)
9708#define GPIO_PIN0_PINVAL26_Pos (26UL)
9709#define GPIO_PIN0_PINVAL26_Msk (0x4000000UL)
9710#define GPIO_PIN0_PINVAL27_Pos (27UL)
9711#define GPIO_PIN0_PINVAL27_Msk (0x8000000UL)
9712#define GPIO_PIN0_PINVAL28_Pos (28UL)
9713#define GPIO_PIN0_PINVAL28_Msk (0x10000000UL)
9714#define GPIO_PIN0_PINVAL29_Pos (29UL)
9715#define GPIO_PIN0_PINVAL29_Msk (0x20000000UL)
9716#define GPIO_PIN0_PINVAL30_Pos (30UL)
9717#define GPIO_PIN0_PINVAL30_Msk (0x40000000UL)
9718#define GPIO_PIN0_PINVAL31_Pos (31UL)
9719#define GPIO_PIN0_PINVAL31_Msk (0x80000000UL)
9720/* ========================================================= PIN1 ========================================================== */
9721#define GPIO_PIN1_PINVAL0_Pos (0UL)
9722#define GPIO_PIN1_PINVAL0_Msk (0x1UL)
9723#define GPIO_PIN1_PINVAL1_Pos (1UL)
9724#define GPIO_PIN1_PINVAL1_Msk (0x2UL)
9725#define GPIO_PIN1_PINVAL2_Pos (2UL)
9726#define GPIO_PIN1_PINVAL2_Msk (0x4UL)
9727#define GPIO_PIN1_PINVAL3_Pos (3UL)
9728#define GPIO_PIN1_PINVAL3_Msk (0x8UL)
9729#define GPIO_PIN1_PINVAL4_Pos (4UL)
9730#define GPIO_PIN1_PINVAL4_Msk (0x10UL)
9731#define GPIO_PIN1_PINVAL5_Pos (5UL)
9732#define GPIO_PIN1_PINVAL5_Msk (0x20UL)
9733#define GPIO_PIN1_PINVAL6_Pos (6UL)
9734#define GPIO_PIN1_PINVAL6_Msk (0x40UL)
9735#define GPIO_PIN1_PINVAL7_Pos (7UL)
9736#define GPIO_PIN1_PINVAL7_Msk (0x80UL)
9737#define GPIO_PIN1_PINVAL8_Pos (8UL)
9738#define GPIO_PIN1_PINVAL8_Msk (0x100UL)
9739#define GPIO_PIN1_PINVAL9_Pos (9UL)
9740#define GPIO_PIN1_PINVAL9_Msk (0x200UL)
9741#define GPIO_PIN1_PINVAL10_Pos (10UL)
9742#define GPIO_PIN1_PINVAL10_Msk (0x400UL)
9743#define GPIO_PIN1_PINVAL11_Pos (11UL)
9744#define GPIO_PIN1_PINVAL11_Msk (0x800UL)
9745#define GPIO_PIN1_PINVAL12_Pos (12UL)
9746#define GPIO_PIN1_PINVAL12_Msk (0x1000UL)
9747#define GPIO_PIN1_PINVAL13_Pos (13UL)
9748#define GPIO_PIN1_PINVAL13_Msk (0x2000UL)
9749#define GPIO_PIN1_PINVAL14_Pos (14UL)
9750#define GPIO_PIN1_PINVAL14_Msk (0x4000UL)
9751#define GPIO_PIN1_PINVAL15_Pos (15UL)
9752#define GPIO_PIN1_PINVAL15_Msk (0x8000UL)
9753#define GPIO_PIN1_PINVAL16_Pos (16UL)
9754#define GPIO_PIN1_PINVAL16_Msk (0x10000UL)
9755#define GPIO_PIN1_PINVAL17_Pos (17UL)
9756#define GPIO_PIN1_PINVAL17_Msk (0x20000UL)
9757#define GPIO_PIN1_PINVAL18_Pos (18UL)
9758#define GPIO_PIN1_PINVAL18_Msk (0x40000UL)
9759#define GPIO_PIN1_PINVAL19_Pos (19UL)
9760#define GPIO_PIN1_PINVAL19_Msk (0x80000UL)
9761#define GPIO_PIN1_PINVAL20_Pos (20UL)
9762#define GPIO_PIN1_PINVAL20_Msk (0x100000UL)
9763#define GPIO_PIN1_PINVAL21_Pos (21UL)
9764#define GPIO_PIN1_PINVAL21_Msk (0x200000UL)
9765#define GPIO_PIN1_PINVAL22_Pos (22UL)
9766#define GPIO_PIN1_PINVAL22_Msk (0x400000UL)
9767#define GPIO_PIN1_PINVAL23_Pos (23UL)
9768#define GPIO_PIN1_PINVAL23_Msk (0x800000UL)
9769#define GPIO_PIN1_PINVAL24_Pos (24UL)
9770#define GPIO_PIN1_PINVAL24_Msk (0x1000000UL)
9771#define GPIO_PIN1_PINVAL25_Pos (25UL)
9772#define GPIO_PIN1_PINVAL25_Msk (0x2000000UL)
9773#define GPIO_PIN1_PINVAL26_Pos (26UL)
9774#define GPIO_PIN1_PINVAL26_Msk (0x4000000UL)
9775#define GPIO_PIN1_PINVAL27_Pos (27UL)
9776#define GPIO_PIN1_PINVAL27_Msk (0x8000000UL)
9777#define GPIO_PIN1_PINVAL28_Pos (28UL)
9778#define GPIO_PIN1_PINVAL28_Msk (0x10000000UL)
9779#define GPIO_PIN1_PINVAL29_Pos (29UL)
9780#define GPIO_PIN1_PINVAL29_Msk (0x20000000UL)
9781#define GPIO_PIN1_PINVAL30_Pos (30UL)
9782#define GPIO_PIN1_PINVAL30_Msk (0x40000000UL)
9783#define GPIO_PIN1_PINVAL31_Pos (31UL)
9784#define GPIO_PIN1_PINVAL31_Msk (0x80000000UL)
9785/* ========================================================= PIN2 ========================================================== */
9786#define GPIO_PIN2_PINVAL0_Pos (0UL)
9787#define GPIO_PIN2_PINVAL0_Msk (0x1UL)
9788#define GPIO_PIN2_PINVAL1_Pos (1UL)
9789#define GPIO_PIN2_PINVAL1_Msk (0x2UL)
9790#define GPIO_PIN2_PINVAL2_Pos (2UL)
9791#define GPIO_PIN2_PINVAL2_Msk (0x4UL)
9792#define GPIO_PIN2_PINVAL3_Pos (3UL)
9793#define GPIO_PIN2_PINVAL3_Msk (0x8UL)
9794#define GPIO_PIN2_PINVAL4_Pos (4UL)
9795#define GPIO_PIN2_PINVAL4_Msk (0x10UL)
9796#define GPIO_PIN2_PINVAL5_Pos (5UL)
9797#define GPIO_PIN2_PINVAL5_Msk (0x20UL)
9798#define GPIO_PIN2_PINVAL6_Pos (6UL)
9799#define GPIO_PIN2_PINVAL6_Msk (0x40UL)
9800#define GPIO_PIN2_PINVAL7_Pos (7UL)
9801#define GPIO_PIN2_PINVAL7_Msk (0x80UL)
9802#define GPIO_PIN2_PINVAL8_Pos (8UL)
9803#define GPIO_PIN2_PINVAL8_Msk (0x100UL)
9804#define GPIO_PIN2_PINVAL9_Pos (9UL)
9805#define GPIO_PIN2_PINVAL9_Msk (0x200UL)
9806#define GPIO_PIN2_PINVAL10_Pos (10UL)
9807#define GPIO_PIN2_PINVAL10_Msk (0x400UL)
9808#define GPIO_PIN2_PINVAL11_Pos (11UL)
9809#define GPIO_PIN2_PINVAL11_Msk (0x800UL)
9810#define GPIO_PIN2_PINVAL12_Pos (12UL)
9811#define GPIO_PIN2_PINVAL12_Msk (0x1000UL)
9812#define GPIO_PIN2_PINVAL13_Pos (13UL)
9813#define GPIO_PIN2_PINVAL13_Msk (0x2000UL)
9814#define GPIO_PIN2_PINVAL14_Pos (14UL)
9815#define GPIO_PIN2_PINVAL14_Msk (0x4000UL)
9816#define GPIO_PIN2_PINVAL15_Pos (15UL)
9817#define GPIO_PIN2_PINVAL15_Msk (0x8000UL)
9818#define GPIO_PIN2_PINVAL16_Pos (16UL)
9819#define GPIO_PIN2_PINVAL16_Msk (0x10000UL)
9820#define GPIO_PIN2_PINVAL17_Pos (17UL)
9821#define GPIO_PIN2_PINVAL17_Msk (0x20000UL)
9822#define GPIO_PIN2_PINVAL18_Pos (18UL)
9823#define GPIO_PIN2_PINVAL18_Msk (0x40000UL)
9824#define GPIO_PIN2_PINVAL19_Pos (19UL)
9825#define GPIO_PIN2_PINVAL19_Msk (0x80000UL)
9826#define GPIO_PIN2_PINVAL20_Pos (20UL)
9827#define GPIO_PIN2_PINVAL20_Msk (0x100000UL)
9828#define GPIO_PIN2_PINVAL21_Pos (21UL)
9829#define GPIO_PIN2_PINVAL21_Msk (0x200000UL)
9830#define GPIO_PIN2_PINVAL22_Pos (22UL)
9831#define GPIO_PIN2_PINVAL22_Msk (0x400000UL)
9832#define GPIO_PIN2_PINVAL23_Pos (23UL)
9833#define GPIO_PIN2_PINVAL23_Msk (0x800000UL)
9834#define GPIO_PIN2_PINVAL24_Pos (24UL)
9835#define GPIO_PIN2_PINVAL24_Msk (0x1000000UL)
9836#define GPIO_PIN2_PINVAL25_Pos (25UL)
9837#define GPIO_PIN2_PINVAL25_Msk (0x2000000UL)
9838#define GPIO_PIN2_PINVAL26_Pos (26UL)
9839#define GPIO_PIN2_PINVAL26_Msk (0x4000000UL)
9840#define GPIO_PIN2_PINVAL27_Pos (27UL)
9841#define GPIO_PIN2_PINVAL27_Msk (0x8000000UL)
9842#define GPIO_PIN2_PINVAL28_Pos (28UL)
9843#define GPIO_PIN2_PINVAL28_Msk (0x10000000UL)
9844#define GPIO_PIN2_PINVAL29_Pos (29UL)
9845#define GPIO_PIN2_PINVAL29_Msk (0x20000000UL)
9846#define GPIO_PIN2_PINVAL30_Pos (30UL)
9847#define GPIO_PIN2_PINVAL30_Msk (0x40000000UL)
9848#define GPIO_PIN2_PINVAL31_Pos (31UL)
9849#define GPIO_PIN2_PINVAL31_Msk (0x80000000UL)
9850/* ========================================================= PIN3 ========================================================== */
9851#define GPIO_PIN3_PINVAL0_Pos (0UL)
9852#define GPIO_PIN3_PINVAL0_Msk (0x1UL)
9853#define GPIO_PIN3_PINVAL1_Pos (1UL)
9854#define GPIO_PIN3_PINVAL1_Msk (0x2UL)
9855#define GPIO_PIN3_PINVAL2_Pos (2UL)
9856#define GPIO_PIN3_PINVAL2_Msk (0x4UL)
9857#define GPIO_PIN3_PINVAL3_Pos (3UL)
9858#define GPIO_PIN3_PINVAL3_Msk (0x8UL)
9859#define GPIO_PIN3_PINVAL4_Pos (4UL)
9860#define GPIO_PIN3_PINVAL4_Msk (0x10UL)
9861#define GPIO_PIN3_PINVAL5_Pos (5UL)
9862#define GPIO_PIN3_PINVAL5_Msk (0x20UL)
9863#define GPIO_PIN3_PINVAL6_Pos (6UL)
9864#define GPIO_PIN3_PINVAL6_Msk (0x40UL)
9865#define GPIO_PIN3_PINVAL7_Pos (7UL)
9866#define GPIO_PIN3_PINVAL7_Msk (0x80UL)
9867#define GPIO_PIN3_PINVAL8_Pos (8UL)
9868#define GPIO_PIN3_PINVAL8_Msk (0x100UL)
9869#define GPIO_PIN3_PINVAL9_Pos (9UL)
9870#define GPIO_PIN3_PINVAL9_Msk (0x200UL)
9871#define GPIO_PIN3_PINVAL10_Pos (10UL)
9872#define GPIO_PIN3_PINVAL10_Msk (0x400UL)
9873#define GPIO_PIN3_PINVAL11_Pos (11UL)
9874#define GPIO_PIN3_PINVAL11_Msk (0x800UL)
9875#define GPIO_PIN3_PINVAL12_Pos (12UL)
9876#define GPIO_PIN3_PINVAL12_Msk (0x1000UL)
9877#define GPIO_PIN3_PINVAL13_Pos (13UL)
9878#define GPIO_PIN3_PINVAL13_Msk (0x2000UL)
9879#define GPIO_PIN3_PINVAL14_Pos (14UL)
9880#define GPIO_PIN3_PINVAL14_Msk (0x4000UL)
9881#define GPIO_PIN3_PINVAL15_Pos (15UL)
9882#define GPIO_PIN3_PINVAL15_Msk (0x8000UL)
9883#define GPIO_PIN3_PINVAL16_Pos (16UL)
9884#define GPIO_PIN3_PINVAL16_Msk (0x10000UL)
9885#define GPIO_PIN3_PINVAL17_Pos (17UL)
9886#define GPIO_PIN3_PINVAL17_Msk (0x20000UL)
9887#define GPIO_PIN3_PINVAL18_Pos (18UL)
9888#define GPIO_PIN3_PINVAL18_Msk (0x40000UL)
9889#define GPIO_PIN3_PINVAL19_Pos (19UL)
9890#define GPIO_PIN3_PINVAL19_Msk (0x80000UL)
9891#define GPIO_PIN3_PINVAL20_Pos (20UL)
9892#define GPIO_PIN3_PINVAL20_Msk (0x100000UL)
9893#define GPIO_PIN3_PINVAL21_Pos (21UL)
9894#define GPIO_PIN3_PINVAL21_Msk (0x200000UL)
9895#define GPIO_PIN3_PINVAL22_Pos (22UL)
9896#define GPIO_PIN3_PINVAL22_Msk (0x400000UL)
9897#define GPIO_PIN3_PINVAL23_Pos (23UL)
9898#define GPIO_PIN3_PINVAL23_Msk (0x800000UL)
9899#define GPIO_PIN3_PINVAL24_Pos (24UL)
9900#define GPIO_PIN3_PINVAL24_Msk (0x1000000UL)
9901#define GPIO_PIN3_PINVAL25_Pos (25UL)
9902#define GPIO_PIN3_PINVAL25_Msk (0x2000000UL)
9903#define GPIO_PIN3_PINVAL26_Pos (26UL)
9904#define GPIO_PIN3_PINVAL26_Msk (0x4000000UL)
9905#define GPIO_PIN3_PINVAL27_Pos (27UL)
9906#define GPIO_PIN3_PINVAL27_Msk (0x8000000UL)
9907#define GPIO_PIN3_PINVAL28_Pos (28UL)
9908#define GPIO_PIN3_PINVAL28_Msk (0x10000000UL)
9909#define GPIO_PIN3_PINVAL29_Pos (29UL)
9910#define GPIO_PIN3_PINVAL29_Msk (0x20000000UL)
9911#define GPIO_PIN3_PINVAL30_Pos (30UL)
9912#define GPIO_PIN3_PINVAL30_Msk (0x40000000UL)
9913#define GPIO_PIN3_PINVAL31_Pos (31UL)
9914#define GPIO_PIN3_PINVAL31_Msk (0x80000000UL)
9915/* ========================================================= PIN4 ========================================================== */
9916#define GPIO_PIN4_PINVAL0_Pos (0UL)
9917#define GPIO_PIN4_PINVAL0_Msk (0x1UL)
9918#define GPIO_PIN4_PINVAL1_Pos (1UL)
9919#define GPIO_PIN4_PINVAL1_Msk (0x2UL)
9920#define GPIO_PIN4_PINVAL2_Pos (2UL)
9921#define GPIO_PIN4_PINVAL2_Msk (0x4UL)
9922#define GPIO_PIN4_PINVAL3_Pos (3UL)
9923#define GPIO_PIN4_PINVAL3_Msk (0x8UL)
9924#define GPIO_PIN4_PINVAL4_Pos (4UL)
9925#define GPIO_PIN4_PINVAL4_Msk (0x10UL)
9926#define GPIO_PIN4_PINVAL5_Pos (5UL)
9927#define GPIO_PIN4_PINVAL5_Msk (0x20UL)
9928#define GPIO_PIN4_PINVAL6_Pos (6UL)
9929#define GPIO_PIN4_PINVAL6_Msk (0x40UL)
9930#define GPIO_PIN4_PINVAL7_Pos (7UL)
9931#define GPIO_PIN4_PINVAL7_Msk (0x80UL)
9932#define GPIO_PIN4_PINVAL8_Pos (8UL)
9933#define GPIO_PIN4_PINVAL8_Msk (0x100UL)
9934#define GPIO_PIN4_PINVAL9_Pos (9UL)
9935#define GPIO_PIN4_PINVAL9_Msk (0x200UL)
9936#define GPIO_PIN4_PINVAL10_Pos (10UL)
9937#define GPIO_PIN4_PINVAL10_Msk (0x400UL)
9938#define GPIO_PIN4_PINVAL11_Pos (11UL)
9939#define GPIO_PIN4_PINVAL11_Msk (0x800UL)
9940#define GPIO_PIN4_PINVAL12_Pos (12UL)
9941#define GPIO_PIN4_PINVAL12_Msk (0x1000UL)
9942#define GPIO_PIN4_PINVAL13_Pos (13UL)
9943#define GPIO_PIN4_PINVAL13_Msk (0x2000UL)
9944#define GPIO_PIN4_PINVAL14_Pos (14UL)
9945#define GPIO_PIN4_PINVAL14_Msk (0x4000UL)
9946#define GPIO_PIN4_PINVAL15_Pos (15UL)
9947#define GPIO_PIN4_PINVAL15_Msk (0x8000UL)
9948#define GPIO_PIN4_PINVAL16_Pos (16UL)
9949#define GPIO_PIN4_PINVAL16_Msk (0x10000UL)
9950#define GPIO_PIN4_PINVAL17_Pos (17UL)
9951#define GPIO_PIN4_PINVAL17_Msk (0x20000UL)
9952#define GPIO_PIN4_PINVAL18_Pos (18UL)
9953#define GPIO_PIN4_PINVAL18_Msk (0x40000UL)
9954#define GPIO_PIN4_PINVAL19_Pos (19UL)
9955#define GPIO_PIN4_PINVAL19_Msk (0x80000UL)
9956#define GPIO_PIN4_PINVAL20_Pos (20UL)
9957#define GPIO_PIN4_PINVAL20_Msk (0x100000UL)
9958#define GPIO_PIN4_PINVAL21_Pos (21UL)
9959#define GPIO_PIN4_PINVAL21_Msk (0x200000UL)
9960#define GPIO_PIN4_PINVAL22_Pos (22UL)
9961#define GPIO_PIN4_PINVAL22_Msk (0x400000UL)
9962#define GPIO_PIN4_PINVAL23_Pos (23UL)
9963#define GPIO_PIN4_PINVAL23_Msk (0x800000UL)
9964#define GPIO_PIN4_PINVAL24_Pos (24UL)
9965#define GPIO_PIN4_PINVAL24_Msk (0x1000000UL)
9966#define GPIO_PIN4_PINVAL25_Pos (25UL)
9967#define GPIO_PIN4_PINVAL25_Msk (0x2000000UL)
9968#define GPIO_PIN4_PINVAL26_Pos (26UL)
9969#define GPIO_PIN4_PINVAL26_Msk (0x4000000UL)
9970#define GPIO_PIN4_PINVAL27_Pos (27UL)
9971#define GPIO_PIN4_PINVAL27_Msk (0x8000000UL)
9972#define GPIO_PIN4_PINVAL28_Pos (28UL)
9973#define GPIO_PIN4_PINVAL28_Msk (0x10000000UL)
9974#define GPIO_PIN4_PINVAL29_Pos (29UL)
9975#define GPIO_PIN4_PINVAL29_Msk (0x20000000UL)
9976#define GPIO_PIN4_PINVAL30_Pos (30UL)
9977#define GPIO_PIN4_PINVAL30_Msk (0x40000000UL)
9978#define GPIO_PIN4_PINVAL31_Pos (31UL)
9979#define GPIO_PIN4_PINVAL31_Msk (0x80000000UL)
9980/* ========================================================= SET0 ========================================================== */
9981#define GPIO_SET0_PINSET0_Pos (0UL)
9982#define GPIO_SET0_PINSET0_Msk (0x1UL)
9983#define GPIO_SET0_PINSET1_Pos (1UL)
9984#define GPIO_SET0_PINSET1_Msk (0x2UL)
9985#define GPIO_SET0_PINSET2_Pos (2UL)
9986#define GPIO_SET0_PINSET2_Msk (0x4UL)
9987#define GPIO_SET0_PINSET3_Pos (3UL)
9988#define GPIO_SET0_PINSET3_Msk (0x8UL)
9989#define GPIO_SET0_PINSET4_Pos (4UL)
9990#define GPIO_SET0_PINSET4_Msk (0x10UL)
9991#define GPIO_SET0_PINSET5_Pos (5UL)
9992#define GPIO_SET0_PINSET5_Msk (0x20UL)
9993#define GPIO_SET0_PINSET6_Pos (6UL)
9994#define GPIO_SET0_PINSET6_Msk (0x40UL)
9995#define GPIO_SET0_PINSET7_Pos (7UL)
9996#define GPIO_SET0_PINSET7_Msk (0x80UL)
9997#define GPIO_SET0_PINSET8_Pos (8UL)
9998#define GPIO_SET0_PINSET8_Msk (0x100UL)
9999#define GPIO_SET0_PINSET9_Pos (9UL)
10000#define GPIO_SET0_PINSET9_Msk (0x200UL)
10001#define GPIO_SET0_PINSET10_Pos (10UL)
10002#define GPIO_SET0_PINSET10_Msk (0x400UL)
10003#define GPIO_SET0_PINSET11_Pos (11UL)
10004#define GPIO_SET0_PINSET11_Msk (0x800UL)
10005#define GPIO_SET0_PINSET12_Pos (12UL)
10006#define GPIO_SET0_PINSET12_Msk (0x1000UL)
10007#define GPIO_SET0_PINSET13_Pos (13UL)
10008#define GPIO_SET0_PINSET13_Msk (0x2000UL)
10009#define GPIO_SET0_PINSET14_Pos (14UL)
10010#define GPIO_SET0_PINSET14_Msk (0x4000UL)
10011#define GPIO_SET0_PINSET15_Pos (15UL)
10012#define GPIO_SET0_PINSET15_Msk (0x8000UL)
10013#define GPIO_SET0_PINSET16_Pos (16UL)
10014#define GPIO_SET0_PINSET16_Msk (0x10000UL)
10015#define GPIO_SET0_PINSET17_Pos (17UL)
10016#define GPIO_SET0_PINSET17_Msk (0x20000UL)
10017#define GPIO_SET0_PINSET18_Pos (18UL)
10018#define GPIO_SET0_PINSET18_Msk (0x40000UL)
10019#define GPIO_SET0_PINSET19_Pos (19UL)
10020#define GPIO_SET0_PINSET19_Msk (0x80000UL)
10021#define GPIO_SET0_PINSET20_Pos (20UL)
10022#define GPIO_SET0_PINSET20_Msk (0x100000UL)
10023#define GPIO_SET0_PINSET21_Pos (21UL)
10024#define GPIO_SET0_PINSET21_Msk (0x200000UL)
10025#define GPIO_SET0_PINSET22_Pos (22UL)
10026#define GPIO_SET0_PINSET22_Msk (0x400000UL)
10027#define GPIO_SET0_PINSET23_Pos (23UL)
10028#define GPIO_SET0_PINSET23_Msk (0x800000UL)
10029#define GPIO_SET0_PINSET24_Pos (24UL)
10030#define GPIO_SET0_PINSET24_Msk (0x1000000UL)
10031#define GPIO_SET0_PINSET25_Pos (25UL)
10032#define GPIO_SET0_PINSET25_Msk (0x2000000UL)
10033#define GPIO_SET0_PINSET26_Pos (26UL)
10034#define GPIO_SET0_PINSET26_Msk (0x4000000UL)
10035#define GPIO_SET0_PINSET27_Pos (27UL)
10036#define GPIO_SET0_PINSET27_Msk (0x8000000UL)
10037#define GPIO_SET0_PINSET28_Pos (28UL)
10038#define GPIO_SET0_PINSET28_Msk (0x10000000UL)
10039#define GPIO_SET0_PINSET29_Pos (29UL)
10040#define GPIO_SET0_PINSET29_Msk (0x20000000UL)
10041#define GPIO_SET0_PINSET30_Pos (30UL)
10042#define GPIO_SET0_PINSET30_Msk (0x40000000UL)
10043#define GPIO_SET0_PINSET31_Pos (31UL)
10044#define GPIO_SET0_PINSET31_Msk (0x80000000UL)
10045/* ========================================================= SET1 ========================================================== */
10046#define GPIO_SET1_PINSET0_Pos (0UL)
10047#define GPIO_SET1_PINSET0_Msk (0x1UL)
10048#define GPIO_SET1_PINSET1_Pos (1UL)
10049#define GPIO_SET1_PINSET1_Msk (0x2UL)
10050#define GPIO_SET1_PINSET2_Pos (2UL)
10051#define GPIO_SET1_PINSET2_Msk (0x4UL)
10052#define GPIO_SET1_PINSET3_Pos (3UL)
10053#define GPIO_SET1_PINSET3_Msk (0x8UL)
10054#define GPIO_SET1_PINSET4_Pos (4UL)
10055#define GPIO_SET1_PINSET4_Msk (0x10UL)
10056#define GPIO_SET1_PINSET5_Pos (5UL)
10057#define GPIO_SET1_PINSET5_Msk (0x20UL)
10058#define GPIO_SET1_PINSET6_Pos (6UL)
10059#define GPIO_SET1_PINSET6_Msk (0x40UL)
10060#define GPIO_SET1_PINSET7_Pos (7UL)
10061#define GPIO_SET1_PINSET7_Msk (0x80UL)
10062#define GPIO_SET1_PINSET8_Pos (8UL)
10063#define GPIO_SET1_PINSET8_Msk (0x100UL)
10064#define GPIO_SET1_PINSET9_Pos (9UL)
10065#define GPIO_SET1_PINSET9_Msk (0x200UL)
10066#define GPIO_SET1_PINSET10_Pos (10UL)
10067#define GPIO_SET1_PINSET10_Msk (0x400UL)
10068#define GPIO_SET1_PINSET11_Pos (11UL)
10069#define GPIO_SET1_PINSET11_Msk (0x800UL)
10070#define GPIO_SET1_PINSET12_Pos (12UL)
10071#define GPIO_SET1_PINSET12_Msk (0x1000UL)
10072#define GPIO_SET1_PINSET13_Pos (13UL)
10073#define GPIO_SET1_PINSET13_Msk (0x2000UL)
10074#define GPIO_SET1_PINSET14_Pos (14UL)
10075#define GPIO_SET1_PINSET14_Msk (0x4000UL)
10076#define GPIO_SET1_PINSET15_Pos (15UL)
10077#define GPIO_SET1_PINSET15_Msk (0x8000UL)
10078#define GPIO_SET1_PINSET16_Pos (16UL)
10079#define GPIO_SET1_PINSET16_Msk (0x10000UL)
10080#define GPIO_SET1_PINSET17_Pos (17UL)
10081#define GPIO_SET1_PINSET17_Msk (0x20000UL)
10082#define GPIO_SET1_PINSET18_Pos (18UL)
10083#define GPIO_SET1_PINSET18_Msk (0x40000UL)
10084#define GPIO_SET1_PINSET19_Pos (19UL)
10085#define GPIO_SET1_PINSET19_Msk (0x80000UL)
10086#define GPIO_SET1_PINSET20_Pos (20UL)
10087#define GPIO_SET1_PINSET20_Msk (0x100000UL)
10088#define GPIO_SET1_PINSET21_Pos (21UL)
10089#define GPIO_SET1_PINSET21_Msk (0x200000UL)
10090#define GPIO_SET1_PINSET22_Pos (22UL)
10091#define GPIO_SET1_PINSET22_Msk (0x400000UL)
10092#define GPIO_SET1_PINSET23_Pos (23UL)
10093#define GPIO_SET1_PINSET23_Msk (0x800000UL)
10094#define GPIO_SET1_PINSET24_Pos (24UL)
10095#define GPIO_SET1_PINSET24_Msk (0x1000000UL)
10096#define GPIO_SET1_PINSET25_Pos (25UL)
10097#define GPIO_SET1_PINSET25_Msk (0x2000000UL)
10098#define GPIO_SET1_PINSET26_Pos (26UL)
10099#define GPIO_SET1_PINSET26_Msk (0x4000000UL)
10100#define GPIO_SET1_PINSET27_Pos (27UL)
10101#define GPIO_SET1_PINSET27_Msk (0x8000000UL)
10102#define GPIO_SET1_PINSET28_Pos (28UL)
10103#define GPIO_SET1_PINSET28_Msk (0x10000000UL)
10104#define GPIO_SET1_PINSET29_Pos (29UL)
10105#define GPIO_SET1_PINSET29_Msk (0x20000000UL)
10106#define GPIO_SET1_PINSET30_Pos (30UL)
10107#define GPIO_SET1_PINSET30_Msk (0x40000000UL)
10108#define GPIO_SET1_PINSET31_Pos (31UL)
10109#define GPIO_SET1_PINSET31_Msk (0x80000000UL)
10110/* ========================================================= SET2 ========================================================== */
10111#define GPIO_SET2_PINSET0_Pos (0UL)
10112#define GPIO_SET2_PINSET0_Msk (0x1UL)
10113#define GPIO_SET2_PINSET1_Pos (1UL)
10114#define GPIO_SET2_PINSET1_Msk (0x2UL)
10115#define GPIO_SET2_PINSET2_Pos (2UL)
10116#define GPIO_SET2_PINSET2_Msk (0x4UL)
10117#define GPIO_SET2_PINSET3_Pos (3UL)
10118#define GPIO_SET2_PINSET3_Msk (0x8UL)
10119#define GPIO_SET2_PINSET4_Pos (4UL)
10120#define GPIO_SET2_PINSET4_Msk (0x10UL)
10121#define GPIO_SET2_PINSET5_Pos (5UL)
10122#define GPIO_SET2_PINSET5_Msk (0x20UL)
10123#define GPIO_SET2_PINSET6_Pos (6UL)
10124#define GPIO_SET2_PINSET6_Msk (0x40UL)
10125#define GPIO_SET2_PINSET7_Pos (7UL)
10126#define GPIO_SET2_PINSET7_Msk (0x80UL)
10127#define GPIO_SET2_PINSET8_Pos (8UL)
10128#define GPIO_SET2_PINSET8_Msk (0x100UL)
10129#define GPIO_SET2_PINSET9_Pos (9UL)
10130#define GPIO_SET2_PINSET9_Msk (0x200UL)
10131#define GPIO_SET2_PINSET10_Pos (10UL)
10132#define GPIO_SET2_PINSET10_Msk (0x400UL)
10133#define GPIO_SET2_PINSET11_Pos (11UL)
10134#define GPIO_SET2_PINSET11_Msk (0x800UL)
10135#define GPIO_SET2_PINSET12_Pos (12UL)
10136#define GPIO_SET2_PINSET12_Msk (0x1000UL)
10137#define GPIO_SET2_PINSET13_Pos (13UL)
10138#define GPIO_SET2_PINSET13_Msk (0x2000UL)
10139#define GPIO_SET2_PINSET14_Pos (14UL)
10140#define GPIO_SET2_PINSET14_Msk (0x4000UL)
10141#define GPIO_SET2_PINSET15_Pos (15UL)
10142#define GPIO_SET2_PINSET15_Msk (0x8000UL)
10143#define GPIO_SET2_PINSET16_Pos (16UL)
10144#define GPIO_SET2_PINSET16_Msk (0x10000UL)
10145#define GPIO_SET2_PINSET17_Pos (17UL)
10146#define GPIO_SET2_PINSET17_Msk (0x20000UL)
10147#define GPIO_SET2_PINSET18_Pos (18UL)
10148#define GPIO_SET2_PINSET18_Msk (0x40000UL)
10149#define GPIO_SET2_PINSET19_Pos (19UL)
10150#define GPIO_SET2_PINSET19_Msk (0x80000UL)
10151#define GPIO_SET2_PINSET20_Pos (20UL)
10152#define GPIO_SET2_PINSET20_Msk (0x100000UL)
10153#define GPIO_SET2_PINSET21_Pos (21UL)
10154#define GPIO_SET2_PINSET21_Msk (0x200000UL)
10155#define GPIO_SET2_PINSET22_Pos (22UL)
10156#define GPIO_SET2_PINSET22_Msk (0x400000UL)
10157#define GPIO_SET2_PINSET23_Pos (23UL)
10158#define GPIO_SET2_PINSET23_Msk (0x800000UL)
10159#define GPIO_SET2_PINSET24_Pos (24UL)
10160#define GPIO_SET2_PINSET24_Msk (0x1000000UL)
10161#define GPIO_SET2_PINSET25_Pos (25UL)
10162#define GPIO_SET2_PINSET25_Msk (0x2000000UL)
10163#define GPIO_SET2_PINSET26_Pos (26UL)
10164#define GPIO_SET2_PINSET26_Msk (0x4000000UL)
10165#define GPIO_SET2_PINSET27_Pos (27UL)
10166#define GPIO_SET2_PINSET27_Msk (0x8000000UL)
10167#define GPIO_SET2_PINSET28_Pos (28UL)
10168#define GPIO_SET2_PINSET28_Msk (0x10000000UL)
10169#define GPIO_SET2_PINSET29_Pos (29UL)
10170#define GPIO_SET2_PINSET29_Msk (0x20000000UL)
10171#define GPIO_SET2_PINSET30_Pos (30UL)
10172#define GPIO_SET2_PINSET30_Msk (0x40000000UL)
10173#define GPIO_SET2_PINSET31_Pos (31UL)
10174#define GPIO_SET2_PINSET31_Msk (0x80000000UL)
10175/* ========================================================= SET3 ========================================================== */
10176#define GPIO_SET3_PINSET0_Pos (0UL)
10177#define GPIO_SET3_PINSET0_Msk (0x1UL)
10178#define GPIO_SET3_PINSET1_Pos (1UL)
10179#define GPIO_SET3_PINSET1_Msk (0x2UL)
10180#define GPIO_SET3_PINSET2_Pos (2UL)
10181#define GPIO_SET3_PINSET2_Msk (0x4UL)
10182#define GPIO_SET3_PINSET3_Pos (3UL)
10183#define GPIO_SET3_PINSET3_Msk (0x8UL)
10184#define GPIO_SET3_PINSET4_Pos (4UL)
10185#define GPIO_SET3_PINSET4_Msk (0x10UL)
10186#define GPIO_SET3_PINSET5_Pos (5UL)
10187#define GPIO_SET3_PINSET5_Msk (0x20UL)
10188#define GPIO_SET3_PINSET6_Pos (6UL)
10189#define GPIO_SET3_PINSET6_Msk (0x40UL)
10190#define GPIO_SET3_PINSET7_Pos (7UL)
10191#define GPIO_SET3_PINSET7_Msk (0x80UL)
10192#define GPIO_SET3_PINSET8_Pos (8UL)
10193#define GPIO_SET3_PINSET8_Msk (0x100UL)
10194#define GPIO_SET3_PINSET9_Pos (9UL)
10195#define GPIO_SET3_PINSET9_Msk (0x200UL)
10196#define GPIO_SET3_PINSET10_Pos (10UL)
10197#define GPIO_SET3_PINSET10_Msk (0x400UL)
10198#define GPIO_SET3_PINSET11_Pos (11UL)
10199#define GPIO_SET3_PINSET11_Msk (0x800UL)
10200#define GPIO_SET3_PINSET12_Pos (12UL)
10201#define GPIO_SET3_PINSET12_Msk (0x1000UL)
10202#define GPIO_SET3_PINSET13_Pos (13UL)
10203#define GPIO_SET3_PINSET13_Msk (0x2000UL)
10204#define GPIO_SET3_PINSET14_Pos (14UL)
10205#define GPIO_SET3_PINSET14_Msk (0x4000UL)
10206#define GPIO_SET3_PINSET15_Pos (15UL)
10207#define GPIO_SET3_PINSET15_Msk (0x8000UL)
10208#define GPIO_SET3_PINSET16_Pos (16UL)
10209#define GPIO_SET3_PINSET16_Msk (0x10000UL)
10210#define GPIO_SET3_PINSET17_Pos (17UL)
10211#define GPIO_SET3_PINSET17_Msk (0x20000UL)
10212#define GPIO_SET3_PINSET18_Pos (18UL)
10213#define GPIO_SET3_PINSET18_Msk (0x40000UL)
10214#define GPIO_SET3_PINSET19_Pos (19UL)
10215#define GPIO_SET3_PINSET19_Msk (0x80000UL)
10216#define GPIO_SET3_PINSET20_Pos (20UL)
10217#define GPIO_SET3_PINSET20_Msk (0x100000UL)
10218#define GPIO_SET3_PINSET21_Pos (21UL)
10219#define GPIO_SET3_PINSET21_Msk (0x200000UL)
10220#define GPIO_SET3_PINSET22_Pos (22UL)
10221#define GPIO_SET3_PINSET22_Msk (0x400000UL)
10222#define GPIO_SET3_PINSET23_Pos (23UL)
10223#define GPIO_SET3_PINSET23_Msk (0x800000UL)
10224#define GPIO_SET3_PINSET24_Pos (24UL)
10225#define GPIO_SET3_PINSET24_Msk (0x1000000UL)
10226#define GPIO_SET3_PINSET25_Pos (25UL)
10227#define GPIO_SET3_PINSET25_Msk (0x2000000UL)
10228#define GPIO_SET3_PINSET26_Pos (26UL)
10229#define GPIO_SET3_PINSET26_Msk (0x4000000UL)
10230#define GPIO_SET3_PINSET27_Pos (27UL)
10231#define GPIO_SET3_PINSET27_Msk (0x8000000UL)
10232#define GPIO_SET3_PINSET28_Pos (28UL)
10233#define GPIO_SET3_PINSET28_Msk (0x10000000UL)
10234#define GPIO_SET3_PINSET29_Pos (29UL)
10235#define GPIO_SET3_PINSET29_Msk (0x20000000UL)
10236#define GPIO_SET3_PINSET30_Pos (30UL)
10237#define GPIO_SET3_PINSET30_Msk (0x40000000UL)
10238#define GPIO_SET3_PINSET31_Pos (31UL)
10239#define GPIO_SET3_PINSET31_Msk (0x80000000UL)
10240/* ========================================================= SET4 ========================================================== */
10241#define GPIO_SET4_PINSET0_Pos (0UL)
10242#define GPIO_SET4_PINSET0_Msk (0x1UL)
10243#define GPIO_SET4_PINSET1_Pos (1UL)
10244#define GPIO_SET4_PINSET1_Msk (0x2UL)
10245#define GPIO_SET4_PINSET2_Pos (2UL)
10246#define GPIO_SET4_PINSET2_Msk (0x4UL)
10247#define GPIO_SET4_PINSET3_Pos (3UL)
10248#define GPIO_SET4_PINSET3_Msk (0x8UL)
10249#define GPIO_SET4_PINSET4_Pos (4UL)
10250#define GPIO_SET4_PINSET4_Msk (0x10UL)
10251#define GPIO_SET4_PINSET5_Pos (5UL)
10252#define GPIO_SET4_PINSET5_Msk (0x20UL)
10253#define GPIO_SET4_PINSET6_Pos (6UL)
10254#define GPIO_SET4_PINSET6_Msk (0x40UL)
10255#define GPIO_SET4_PINSET7_Pos (7UL)
10256#define GPIO_SET4_PINSET7_Msk (0x80UL)
10257#define GPIO_SET4_PINSET8_Pos (8UL)
10258#define GPIO_SET4_PINSET8_Msk (0x100UL)
10259#define GPIO_SET4_PINSET9_Pos (9UL)
10260#define GPIO_SET4_PINSET9_Msk (0x200UL)
10261#define GPIO_SET4_PINSET10_Pos (10UL)
10262#define GPIO_SET4_PINSET10_Msk (0x400UL)
10263#define GPIO_SET4_PINSET11_Pos (11UL)
10264#define GPIO_SET4_PINSET11_Msk (0x800UL)
10265#define GPIO_SET4_PINSET12_Pos (12UL)
10266#define GPIO_SET4_PINSET12_Msk (0x1000UL)
10267#define GPIO_SET4_PINSET13_Pos (13UL)
10268#define GPIO_SET4_PINSET13_Msk (0x2000UL)
10269#define GPIO_SET4_PINSET14_Pos (14UL)
10270#define GPIO_SET4_PINSET14_Msk (0x4000UL)
10271#define GPIO_SET4_PINSET15_Pos (15UL)
10272#define GPIO_SET4_PINSET15_Msk (0x8000UL)
10273#define GPIO_SET4_PINSET16_Pos (16UL)
10274#define GPIO_SET4_PINSET16_Msk (0x10000UL)
10275#define GPIO_SET4_PINSET17_Pos (17UL)
10276#define GPIO_SET4_PINSET17_Msk (0x20000UL)
10277#define GPIO_SET4_PINSET18_Pos (18UL)
10278#define GPIO_SET4_PINSET18_Msk (0x40000UL)
10279#define GPIO_SET4_PINSET19_Pos (19UL)
10280#define GPIO_SET4_PINSET19_Msk (0x80000UL)
10281#define GPIO_SET4_PINSET20_Pos (20UL)
10282#define GPIO_SET4_PINSET20_Msk (0x100000UL)
10283#define GPIO_SET4_PINSET21_Pos (21UL)
10284#define GPIO_SET4_PINSET21_Msk (0x200000UL)
10285#define GPIO_SET4_PINSET22_Pos (22UL)
10286#define GPIO_SET4_PINSET22_Msk (0x400000UL)
10287#define GPIO_SET4_PINSET23_Pos (23UL)
10288#define GPIO_SET4_PINSET23_Msk (0x800000UL)
10289#define GPIO_SET4_PINSET24_Pos (24UL)
10290#define GPIO_SET4_PINSET24_Msk (0x1000000UL)
10291#define GPIO_SET4_PINSET25_Pos (25UL)
10292#define GPIO_SET4_PINSET25_Msk (0x2000000UL)
10293#define GPIO_SET4_PINSET26_Pos (26UL)
10294#define GPIO_SET4_PINSET26_Msk (0x4000000UL)
10295#define GPIO_SET4_PINSET27_Pos (27UL)
10296#define GPIO_SET4_PINSET27_Msk (0x8000000UL)
10297#define GPIO_SET4_PINSET28_Pos (28UL)
10298#define GPIO_SET4_PINSET28_Msk (0x10000000UL)
10299#define GPIO_SET4_PINSET29_Pos (29UL)
10300#define GPIO_SET4_PINSET29_Msk (0x20000000UL)
10301#define GPIO_SET4_PINSET30_Pos (30UL)
10302#define GPIO_SET4_PINSET30_Msk (0x40000000UL)
10303#define GPIO_SET4_PINSET31_Pos (31UL)
10304#define GPIO_SET4_PINSET31_Msk (0x80000000UL)
10305/* ========================================================= CLR0 ========================================================== */
10306#define GPIO_CLR0_PINCLR0_Pos (0UL)
10307#define GPIO_CLR0_PINCLR0_Msk (0x1UL)
10308#define GPIO_CLR0_PINCLR1_Pos (1UL)
10309#define GPIO_CLR0_PINCLR1_Msk (0x2UL)
10310#define GPIO_CLR0_PINCLR2_Pos (2UL)
10311#define GPIO_CLR0_PINCLR2_Msk (0x4UL)
10312#define GPIO_CLR0_PINCLR3_Pos (3UL)
10313#define GPIO_CLR0_PINCLR3_Msk (0x8UL)
10314#define GPIO_CLR0_PINCLR4_Pos (4UL)
10315#define GPIO_CLR0_PINCLR4_Msk (0x10UL)
10316#define GPIO_CLR0_PINCLR5_Pos (5UL)
10317#define GPIO_CLR0_PINCLR5_Msk (0x20UL)
10318#define GPIO_CLR0_PINCLR6_Pos (6UL)
10319#define GPIO_CLR0_PINCLR6_Msk (0x40UL)
10320#define GPIO_CLR0_PINCLR7_Pos (7UL)
10321#define GPIO_CLR0_PINCLR7_Msk (0x80UL)
10322#define GPIO_CLR0_PINCLR8_Pos (8UL)
10323#define GPIO_CLR0_PINCLR8_Msk (0x100UL)
10324#define GPIO_CLR0_PINCLR9_Pos (9UL)
10325#define GPIO_CLR0_PINCLR9_Msk (0x200UL)
10326#define GPIO_CLR0_PINCLR10_Pos (10UL)
10327#define GPIO_CLR0_PINCLR10_Msk (0x400UL)
10328#define GPIO_CLR0_PINCLR11_Pos (11UL)
10329#define GPIO_CLR0_PINCLR11_Msk (0x800UL)
10330#define GPIO_CLR0_PINCLR12_Pos (12UL)
10331#define GPIO_CLR0_PINCLR12_Msk (0x1000UL)
10332#define GPIO_CLR0_PINCLR13_Pos (13UL)
10333#define GPIO_CLR0_PINCLR13_Msk (0x2000UL)
10334#define GPIO_CLR0_PINCLR14_Pos (14UL)
10335#define GPIO_CLR0_PINCLR14_Msk (0x4000UL)
10336#define GPIO_CLR0_PINCLR15_Pos (15UL)
10337#define GPIO_CLR0_PINCLR15_Msk (0x8000UL)
10338#define GPIO_CLR0_PINCLR16_Pos (16UL)
10339#define GPIO_CLR0_PINCLR16_Msk (0x10000UL)
10340#define GPIO_CLR0_PINCLR17_Pos (17UL)
10341#define GPIO_CLR0_PINCLR17_Msk (0x20000UL)
10342#define GPIO_CLR0_PINCLR18_Pos (18UL)
10343#define GPIO_CLR0_PINCLR18_Msk (0x40000UL)
10344#define GPIO_CLR0_PINCLR19_Pos (19UL)
10345#define GPIO_CLR0_PINCLR19_Msk (0x80000UL)
10346#define GPIO_CLR0_PINCLR20_Pos (20UL)
10347#define GPIO_CLR0_PINCLR20_Msk (0x100000UL)
10348#define GPIO_CLR0_PINCLR21_Pos (21UL)
10349#define GPIO_CLR0_PINCLR21_Msk (0x200000UL)
10350#define GPIO_CLR0_PINCLR22_Pos (22UL)
10351#define GPIO_CLR0_PINCLR22_Msk (0x400000UL)
10352#define GPIO_CLR0_PINCLR23_Pos (23UL)
10353#define GPIO_CLR0_PINCLR23_Msk (0x800000UL)
10354#define GPIO_CLR0_PINCLR24_Pos (24UL)
10355#define GPIO_CLR0_PINCLR24_Msk (0x1000000UL)
10356#define GPIO_CLR0_PINCLR25_Pos (25UL)
10357#define GPIO_CLR0_PINCLR25_Msk (0x2000000UL)
10358#define GPIO_CLR0_PINCLR26_Pos (26UL)
10359#define GPIO_CLR0_PINCLR26_Msk (0x4000000UL)
10360#define GPIO_CLR0_PINCLR27_Pos (27UL)
10361#define GPIO_CLR0_PINCLR27_Msk (0x8000000UL)
10362#define GPIO_CLR0_PINCLR28_Pos (28UL)
10363#define GPIO_CLR0_PINCLR28_Msk (0x10000000UL)
10364#define GPIO_CLR0_PINCLR29_Pos (29UL)
10365#define GPIO_CLR0_PINCLR29_Msk (0x20000000UL)
10366#define GPIO_CLR0_PINCLR30_Pos (30UL)
10367#define GPIO_CLR0_PINCLR30_Msk (0x40000000UL)
10368#define GPIO_CLR0_PINCLR31_Pos (31UL)
10369#define GPIO_CLR0_PINCLR31_Msk (0x80000000UL)
10370/* ========================================================= CLR1 ========================================================== */
10371#define GPIO_CLR1_PINCLR0_Pos (0UL)
10372#define GPIO_CLR1_PINCLR0_Msk (0x1UL)
10373#define GPIO_CLR1_PINCLR1_Pos (1UL)
10374#define GPIO_CLR1_PINCLR1_Msk (0x2UL)
10375#define GPIO_CLR1_PINCLR2_Pos (2UL)
10376#define GPIO_CLR1_PINCLR2_Msk (0x4UL)
10377#define GPIO_CLR1_PINCLR3_Pos (3UL)
10378#define GPIO_CLR1_PINCLR3_Msk (0x8UL)
10379#define GPIO_CLR1_PINCLR4_Pos (4UL)
10380#define GPIO_CLR1_PINCLR4_Msk (0x10UL)
10381#define GPIO_CLR1_PINCLR5_Pos (5UL)
10382#define GPIO_CLR1_PINCLR5_Msk (0x20UL)
10383#define GPIO_CLR1_PINCLR6_Pos (6UL)
10384#define GPIO_CLR1_PINCLR6_Msk (0x40UL)
10385#define GPIO_CLR1_PINCLR7_Pos (7UL)
10386#define GPIO_CLR1_PINCLR7_Msk (0x80UL)
10387#define GPIO_CLR1_PINCLR8_Pos (8UL)
10388#define GPIO_CLR1_PINCLR8_Msk (0x100UL)
10389#define GPIO_CLR1_PINCLR9_Pos (9UL)
10390#define GPIO_CLR1_PINCLR9_Msk (0x200UL)
10391#define GPIO_CLR1_PINCLR10_Pos (10UL)
10392#define GPIO_CLR1_PINCLR10_Msk (0x400UL)
10393#define GPIO_CLR1_PINCLR11_Pos (11UL)
10394#define GPIO_CLR1_PINCLR11_Msk (0x800UL)
10395#define GPIO_CLR1_PINCLR12_Pos (12UL)
10396#define GPIO_CLR1_PINCLR12_Msk (0x1000UL)
10397#define GPIO_CLR1_PINCLR13_Pos (13UL)
10398#define GPIO_CLR1_PINCLR13_Msk (0x2000UL)
10399#define GPIO_CLR1_PINCLR14_Pos (14UL)
10400#define GPIO_CLR1_PINCLR14_Msk (0x4000UL)
10401#define GPIO_CLR1_PINCLR15_Pos (15UL)
10402#define GPIO_CLR1_PINCLR15_Msk (0x8000UL)
10403#define GPIO_CLR1_PINCLR16_Pos (16UL)
10404#define GPIO_CLR1_PINCLR16_Msk (0x10000UL)
10405#define GPIO_CLR1_PINCLR17_Pos (17UL)
10406#define GPIO_CLR1_PINCLR17_Msk (0x20000UL)
10407#define GPIO_CLR1_PINCLR18_Pos (18UL)
10408#define GPIO_CLR1_PINCLR18_Msk (0x40000UL)
10409#define GPIO_CLR1_PINCLR19_Pos (19UL)
10410#define GPIO_CLR1_PINCLR19_Msk (0x80000UL)
10411#define GPIO_CLR1_PINCLR20_Pos (20UL)
10412#define GPIO_CLR1_PINCLR20_Msk (0x100000UL)
10413#define GPIO_CLR1_PINCLR21_Pos (21UL)
10414#define GPIO_CLR1_PINCLR21_Msk (0x200000UL)
10415#define GPIO_CLR1_PINCLR22_Pos (22UL)
10416#define GPIO_CLR1_PINCLR22_Msk (0x400000UL)
10417#define GPIO_CLR1_PINCLR23_Pos (23UL)
10418#define GPIO_CLR1_PINCLR23_Msk (0x800000UL)
10419#define GPIO_CLR1_PINCLR24_Pos (24UL)
10420#define GPIO_CLR1_PINCLR24_Msk (0x1000000UL)
10421#define GPIO_CLR1_PINCLR25_Pos (25UL)
10422#define GPIO_CLR1_PINCLR25_Msk (0x2000000UL)
10423#define GPIO_CLR1_PINCLR26_Pos (26UL)
10424#define GPIO_CLR1_PINCLR26_Msk (0x4000000UL)
10425#define GPIO_CLR1_PINCLR27_Pos (27UL)
10426#define GPIO_CLR1_PINCLR27_Msk (0x8000000UL)
10427#define GPIO_CLR1_PINCLR28_Pos (28UL)
10428#define GPIO_CLR1_PINCLR28_Msk (0x10000000UL)
10429#define GPIO_CLR1_PINCLR29_Pos (29UL)
10430#define GPIO_CLR1_PINCLR29_Msk (0x20000000UL)
10431#define GPIO_CLR1_PINCLR30_Pos (30UL)
10432#define GPIO_CLR1_PINCLR30_Msk (0x40000000UL)
10433#define GPIO_CLR1_PINCLR31_Pos (31UL)
10434#define GPIO_CLR1_PINCLR31_Msk (0x80000000UL)
10435/* ========================================================= CLR2 ========================================================== */
10436#define GPIO_CLR2_PINCLR0_Pos (0UL)
10437#define GPIO_CLR2_PINCLR0_Msk (0x1UL)
10438#define GPIO_CLR2_PINCLR1_Pos (1UL)
10439#define GPIO_CLR2_PINCLR1_Msk (0x2UL)
10440#define GPIO_CLR2_PINCLR2_Pos (2UL)
10441#define GPIO_CLR2_PINCLR2_Msk (0x4UL)
10442#define GPIO_CLR2_PINCLR3_Pos (3UL)
10443#define GPIO_CLR2_PINCLR3_Msk (0x8UL)
10444#define GPIO_CLR2_PINCLR4_Pos (4UL)
10445#define GPIO_CLR2_PINCLR4_Msk (0x10UL)
10446#define GPIO_CLR2_PINCLR5_Pos (5UL)
10447#define GPIO_CLR2_PINCLR5_Msk (0x20UL)
10448#define GPIO_CLR2_PINCLR6_Pos (6UL)
10449#define GPIO_CLR2_PINCLR6_Msk (0x40UL)
10450#define GPIO_CLR2_PINCLR7_Pos (7UL)
10451#define GPIO_CLR2_PINCLR7_Msk (0x80UL)
10452#define GPIO_CLR2_PINCLR8_Pos (8UL)
10453#define GPIO_CLR2_PINCLR8_Msk (0x100UL)
10454#define GPIO_CLR2_PINCLR9_Pos (9UL)
10455#define GPIO_CLR2_PINCLR9_Msk (0x200UL)
10456#define GPIO_CLR2_PINCLR10_Pos (10UL)
10457#define GPIO_CLR2_PINCLR10_Msk (0x400UL)
10458#define GPIO_CLR2_PINCLR11_Pos (11UL)
10459#define GPIO_CLR2_PINCLR11_Msk (0x800UL)
10460#define GPIO_CLR2_PINCLR12_Pos (12UL)
10461#define GPIO_CLR2_PINCLR12_Msk (0x1000UL)
10462#define GPIO_CLR2_PINCLR13_Pos (13UL)
10463#define GPIO_CLR2_PINCLR13_Msk (0x2000UL)
10464#define GPIO_CLR2_PINCLR14_Pos (14UL)
10465#define GPIO_CLR2_PINCLR14_Msk (0x4000UL)
10466#define GPIO_CLR2_PINCLR15_Pos (15UL)
10467#define GPIO_CLR2_PINCLR15_Msk (0x8000UL)
10468#define GPIO_CLR2_PINCLR16_Pos (16UL)
10469#define GPIO_CLR2_PINCLR16_Msk (0x10000UL)
10470#define GPIO_CLR2_PINCLR17_Pos (17UL)
10471#define GPIO_CLR2_PINCLR17_Msk (0x20000UL)
10472#define GPIO_CLR2_PINCLR18_Pos (18UL)
10473#define GPIO_CLR2_PINCLR18_Msk (0x40000UL)
10474#define GPIO_CLR2_PINCLR19_Pos (19UL)
10475#define GPIO_CLR2_PINCLR19_Msk (0x80000UL)
10476#define GPIO_CLR2_PINCLR20_Pos (20UL)
10477#define GPIO_CLR2_PINCLR20_Msk (0x100000UL)
10478#define GPIO_CLR2_PINCLR21_Pos (21UL)
10479#define GPIO_CLR2_PINCLR21_Msk (0x200000UL)
10480#define GPIO_CLR2_PINCLR22_Pos (22UL)
10481#define GPIO_CLR2_PINCLR22_Msk (0x400000UL)
10482#define GPIO_CLR2_PINCLR23_Pos (23UL)
10483#define GPIO_CLR2_PINCLR23_Msk (0x800000UL)
10484#define GPIO_CLR2_PINCLR24_Pos (24UL)
10485#define GPIO_CLR2_PINCLR24_Msk (0x1000000UL)
10486#define GPIO_CLR2_PINCLR25_Pos (25UL)
10487#define GPIO_CLR2_PINCLR25_Msk (0x2000000UL)
10488#define GPIO_CLR2_PINCLR26_Pos (26UL)
10489#define GPIO_CLR2_PINCLR26_Msk (0x4000000UL)
10490#define GPIO_CLR2_PINCLR27_Pos (27UL)
10491#define GPIO_CLR2_PINCLR27_Msk (0x8000000UL)
10492#define GPIO_CLR2_PINCLR28_Pos (28UL)
10493#define GPIO_CLR2_PINCLR28_Msk (0x10000000UL)
10494#define GPIO_CLR2_PINCLR29_Pos (29UL)
10495#define GPIO_CLR2_PINCLR29_Msk (0x20000000UL)
10496#define GPIO_CLR2_PINCLR30_Pos (30UL)
10497#define GPIO_CLR2_PINCLR30_Msk (0x40000000UL)
10498#define GPIO_CLR2_PINCLR31_Pos (31UL)
10499#define GPIO_CLR2_PINCLR31_Msk (0x80000000UL)
10500/* ========================================================= CLR3 ========================================================== */
10501#define GPIO_CLR3_PINCLR0_Pos (0UL)
10502#define GPIO_CLR3_PINCLR0_Msk (0x1UL)
10503#define GPIO_CLR3_PINCLR1_Pos (1UL)
10504#define GPIO_CLR3_PINCLR1_Msk (0x2UL)
10505#define GPIO_CLR3_PINCLR2_Pos (2UL)
10506#define GPIO_CLR3_PINCLR2_Msk (0x4UL)
10507#define GPIO_CLR3_PINCLR3_Pos (3UL)
10508#define GPIO_CLR3_PINCLR3_Msk (0x8UL)
10509#define GPIO_CLR3_PINCLR4_Pos (4UL)
10510#define GPIO_CLR3_PINCLR4_Msk (0x10UL)
10511#define GPIO_CLR3_PINCLR5_Pos (5UL)
10512#define GPIO_CLR3_PINCLR5_Msk (0x20UL)
10513#define GPIO_CLR3_PINCLR6_Pos (6UL)
10514#define GPIO_CLR3_PINCLR6_Msk (0x40UL)
10515#define GPIO_CLR3_PINCLR7_Pos (7UL)
10516#define GPIO_CLR3_PINCLR7_Msk (0x80UL)
10517#define GPIO_CLR3_PINCLR8_Pos (8UL)
10518#define GPIO_CLR3_PINCLR8_Msk (0x100UL)
10519#define GPIO_CLR3_PINCLR9_Pos (9UL)
10520#define GPIO_CLR3_PINCLR9_Msk (0x200UL)
10521#define GPIO_CLR3_PINCLR10_Pos (10UL)
10522#define GPIO_CLR3_PINCLR10_Msk (0x400UL)
10523#define GPIO_CLR3_PINCLR11_Pos (11UL)
10524#define GPIO_CLR3_PINCLR11_Msk (0x800UL)
10525#define GPIO_CLR3_PINCLR12_Pos (12UL)
10526#define GPIO_CLR3_PINCLR12_Msk (0x1000UL)
10527#define GPIO_CLR3_PINCLR13_Pos (13UL)
10528#define GPIO_CLR3_PINCLR13_Msk (0x2000UL)
10529#define GPIO_CLR3_PINCLR14_Pos (14UL)
10530#define GPIO_CLR3_PINCLR14_Msk (0x4000UL)
10531#define GPIO_CLR3_PINCLR15_Pos (15UL)
10532#define GPIO_CLR3_PINCLR15_Msk (0x8000UL)
10533#define GPIO_CLR3_PINCLR16_Pos (16UL)
10534#define GPIO_CLR3_PINCLR16_Msk (0x10000UL)
10535#define GPIO_CLR3_PINCLR17_Pos (17UL)
10536#define GPIO_CLR3_PINCLR17_Msk (0x20000UL)
10537#define GPIO_CLR3_PINCLR18_Pos (18UL)
10538#define GPIO_CLR3_PINCLR18_Msk (0x40000UL)
10539#define GPIO_CLR3_PINCLR19_Pos (19UL)
10540#define GPIO_CLR3_PINCLR19_Msk (0x80000UL)
10541#define GPIO_CLR3_PINCLR20_Pos (20UL)
10542#define GPIO_CLR3_PINCLR20_Msk (0x100000UL)
10543#define GPIO_CLR3_PINCLR21_Pos (21UL)
10544#define GPIO_CLR3_PINCLR21_Msk (0x200000UL)
10545#define GPIO_CLR3_PINCLR22_Pos (22UL)
10546#define GPIO_CLR3_PINCLR22_Msk (0x400000UL)
10547#define GPIO_CLR3_PINCLR23_Pos (23UL)
10548#define GPIO_CLR3_PINCLR23_Msk (0x800000UL)
10549#define GPIO_CLR3_PINCLR24_Pos (24UL)
10550#define GPIO_CLR3_PINCLR24_Msk (0x1000000UL)
10551#define GPIO_CLR3_PINCLR25_Pos (25UL)
10552#define GPIO_CLR3_PINCLR25_Msk (0x2000000UL)
10553#define GPIO_CLR3_PINCLR26_Pos (26UL)
10554#define GPIO_CLR3_PINCLR26_Msk (0x4000000UL)
10555#define GPIO_CLR3_PINCLR27_Pos (27UL)
10556#define GPIO_CLR3_PINCLR27_Msk (0x8000000UL)
10557#define GPIO_CLR3_PINCLR28_Pos (28UL)
10558#define GPIO_CLR3_PINCLR28_Msk (0x10000000UL)
10559#define GPIO_CLR3_PINCLR29_Pos (29UL)
10560#define GPIO_CLR3_PINCLR29_Msk (0x20000000UL)
10561#define GPIO_CLR3_PINCLR30_Pos (30UL)
10562#define GPIO_CLR3_PINCLR30_Msk (0x40000000UL)
10563#define GPIO_CLR3_PINCLR31_Pos (31UL)
10564#define GPIO_CLR3_PINCLR31_Msk (0x80000000UL)
10565/* ========================================================= CLR4 ========================================================== */
10566#define GPIO_CLR4_PINCLR0_Pos (0UL)
10567#define GPIO_CLR4_PINCLR0_Msk (0x1UL)
10568#define GPIO_CLR4_PINCLR1_Pos (1UL)
10569#define GPIO_CLR4_PINCLR1_Msk (0x2UL)
10570#define GPIO_CLR4_PINCLR2_Pos (2UL)
10571#define GPIO_CLR4_PINCLR2_Msk (0x4UL)
10572#define GPIO_CLR4_PINCLR3_Pos (3UL)
10573#define GPIO_CLR4_PINCLR3_Msk (0x8UL)
10574#define GPIO_CLR4_PINCLR4_Pos (4UL)
10575#define GPIO_CLR4_PINCLR4_Msk (0x10UL)
10576#define GPIO_CLR4_PINCLR5_Pos (5UL)
10577#define GPIO_CLR4_PINCLR5_Msk (0x20UL)
10578#define GPIO_CLR4_PINCLR6_Pos (6UL)
10579#define GPIO_CLR4_PINCLR6_Msk (0x40UL)
10580#define GPIO_CLR4_PINCLR7_Pos (7UL)
10581#define GPIO_CLR4_PINCLR7_Msk (0x80UL)
10582#define GPIO_CLR4_PINCLR8_Pos (8UL)
10583#define GPIO_CLR4_PINCLR8_Msk (0x100UL)
10584#define GPIO_CLR4_PINCLR9_Pos (9UL)
10585#define GPIO_CLR4_PINCLR9_Msk (0x200UL)
10586#define GPIO_CLR4_PINCLR10_Pos (10UL)
10587#define GPIO_CLR4_PINCLR10_Msk (0x400UL)
10588#define GPIO_CLR4_PINCLR11_Pos (11UL)
10589#define GPIO_CLR4_PINCLR11_Msk (0x800UL)
10590#define GPIO_CLR4_PINCLR12_Pos (12UL)
10591#define GPIO_CLR4_PINCLR12_Msk (0x1000UL)
10592#define GPIO_CLR4_PINCLR13_Pos (13UL)
10593#define GPIO_CLR4_PINCLR13_Msk (0x2000UL)
10594#define GPIO_CLR4_PINCLR14_Pos (14UL)
10595#define GPIO_CLR4_PINCLR14_Msk (0x4000UL)
10596#define GPIO_CLR4_PINCLR15_Pos (15UL)
10597#define GPIO_CLR4_PINCLR15_Msk (0x8000UL)
10598#define GPIO_CLR4_PINCLR16_Pos (16UL)
10599#define GPIO_CLR4_PINCLR16_Msk (0x10000UL)
10600#define GPIO_CLR4_PINCLR17_Pos (17UL)
10601#define GPIO_CLR4_PINCLR17_Msk (0x20000UL)
10602#define GPIO_CLR4_PINCLR18_Pos (18UL)
10603#define GPIO_CLR4_PINCLR18_Msk (0x40000UL)
10604#define GPIO_CLR4_PINCLR19_Pos (19UL)
10605#define GPIO_CLR4_PINCLR19_Msk (0x80000UL)
10606#define GPIO_CLR4_PINCLR20_Pos (20UL)
10607#define GPIO_CLR4_PINCLR20_Msk (0x100000UL)
10608#define GPIO_CLR4_PINCLR21_Pos (21UL)
10609#define GPIO_CLR4_PINCLR21_Msk (0x200000UL)
10610#define GPIO_CLR4_PINCLR22_Pos (22UL)
10611#define GPIO_CLR4_PINCLR22_Msk (0x400000UL)
10612#define GPIO_CLR4_PINCLR23_Pos (23UL)
10613#define GPIO_CLR4_PINCLR23_Msk (0x800000UL)
10614#define GPIO_CLR4_PINCLR24_Pos (24UL)
10615#define GPIO_CLR4_PINCLR24_Msk (0x1000000UL)
10616#define GPIO_CLR4_PINCLR25_Pos (25UL)
10617#define GPIO_CLR4_PINCLR25_Msk (0x2000000UL)
10618#define GPIO_CLR4_PINCLR26_Pos (26UL)
10619#define GPIO_CLR4_PINCLR26_Msk (0x4000000UL)
10620#define GPIO_CLR4_PINCLR27_Pos (27UL)
10621#define GPIO_CLR4_PINCLR27_Msk (0x8000000UL)
10622#define GPIO_CLR4_PINCLR28_Pos (28UL)
10623#define GPIO_CLR4_PINCLR28_Msk (0x10000000UL)
10624#define GPIO_CLR4_PINCLR29_Pos (29UL)
10625#define GPIO_CLR4_PINCLR29_Msk (0x20000000UL)
10626#define GPIO_CLR4_PINCLR30_Pos (30UL)
10627#define GPIO_CLR4_PINCLR30_Msk (0x40000000UL)
10628#define GPIO_CLR4_PINCLR31_Pos (31UL)
10629#define GPIO_CLR4_PINCLR31_Msk (0x80000000UL)
10631 /* End of group PosMask_peripherals */
10632
10633
10634#ifdef __cplusplus
10635}
10636#endif
10637
10638#endif /* LPC176X5X_H */
10639
10640
10641 /* End of group LPC176x5x */
10642
10643 /* End of group */
core_cm3.h
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
__OM
#define __OM
Definition core_cm3.h:174
__IM
#define __IM
Definition core_cm3.h:173
__IOM
#define __IOM
Definition core_cm3.h:175
IRQn_Type
IRQn_Type
Definition LPC176x5x.h:56
PendSV_IRQn
@ PendSV_IRQn
Definition LPC176x5x.h:68
RIT_IRQn
@ RIT_IRQn
Definition LPC176x5x.h:100
EINT0_IRQn
@ EINT0_IRQn
Definition LPC176x5x.h:89
TIMER1_IRQn
@ TIMER1_IRQn
Definition LPC176x5x.h:73
PWM1_IRQn
@ PWM1_IRQn
Definition LPC176x5x.h:80
I2C2_IRQn
@ I2C2_IRQn
Definition LPC176x5x.h:83
PLL1_IRQn
@ PLL1_IRQn
Definition LPC176x5x.h:103
I2C0_IRQn
@ I2C0_IRQn
Definition LPC176x5x.h:81
UART3_IRQn
@ UART3_IRQn
Definition LPC176x5x.h:79
I2S_IRQn
@ I2S_IRQn
Definition LPC176x5x.h:98
EINT3_IRQn
@ EINT3_IRQn
Definition LPC176x5x.h:92
CAN_IRQn
@ CAN_IRQn
Definition LPC176x5x.h:96
TIMER0_IRQn
@ TIMER0_IRQn
Definition LPC176x5x.h:72
CANActivity_IRQn
@ CANActivity_IRQn
Definition LPC176x5x.h:105
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition LPC176x5x.h:61
EINT2_IRQn
@ EINT2_IRQn
Definition LPC176x5x.h:91
DMA_IRQn
@ DMA_IRQn
Definition LPC176x5x.h:97
SVCall_IRQn
@ SVCall_IRQn
Definition LPC176x5x.h:66
ADC_IRQn
@ ADC_IRQn
Definition LPC176x5x.h:93
USB_IRQn
@ USB_IRQn
Definition LPC176x5x.h:95
Reset_IRQn
@ Reset_IRQn
Definition LPC176x5x.h:58
MCPWM_IRQn
@ MCPWM_IRQn
Definition LPC176x5x.h:101
UsageFault_IRQn
@ UsageFault_IRQn
Definition LPC176x5x.h:65
SSP0_IRQn
@ SSP0_IRQn
Definition LPC176x5x.h:85
SysTick_IRQn
@ SysTick_IRQn
Definition LPC176x5x.h:69
PLL0_IRQn
@ PLL0_IRQn
Definition LPC176x5x.h:87
WDT_IRQn
@ WDT_IRQn
Definition LPC176x5x.h:71
TIMER3_IRQn
@ TIMER3_IRQn
Definition LPC176x5x.h:75
QEI_IRQn
@ QEI_IRQn
Definition LPC176x5x.h:102
BusFault_IRQn
@ BusFault_IRQn
Definition LPC176x5x.h:63
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition LPC176x5x.h:67
SPI_IRQn
@ SPI_IRQn
Definition LPC176x5x.h:84
UART1_IRQn
@ UART1_IRQn
Definition LPC176x5x.h:77
USBActivity_IRQn
@ USBActivity_IRQn
Definition LPC176x5x.h:104
UART2_IRQn
@ UART2_IRQn
Definition LPC176x5x.h:78
HardFault_IRQn
@ HardFault_IRQn
Definition LPC176x5x.h:60
BOD_IRQn
@ BOD_IRQn
Definition LPC176x5x.h:94
EINT1_IRQn
@ EINT1_IRQn
Definition LPC176x5x.h:90
TIMER2_IRQn
@ TIMER2_IRQn
Definition LPC176x5x.h:74
SSP1_IRQn
@ SSP1_IRQn
Definition LPC176x5x.h:86
RTC_IRQn
@ RTC_IRQn
Definition LPC176x5x.h:88
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition LPC176x5x.h:59
UART0_IRQn
@ UART0_IRQn
Definition LPC176x5x.h:76
ENET_IRQn
@ ENET_IRQn
Definition LPC176x5x.h:99
I2C1_IRQn
@ I2C1_IRQn
Definition LPC176x5x.h:82
LPC_ADC_Type
Analog-to-Digital Converter (ADC) (ADC)
Definition LPC176x5x.h:767
LPC_ADC_Type::GDR
__IOM uint32_t GDR
Definition LPC176x5x.h:771
LPC_ADC_Type::INTEN
__IOM uint32_t INTEN
Definition LPC176x5x.h:775
LPC_ADC_Type::STAT
__IM uint32_t STAT
Definition LPC176x5x.h:783
LPC_ADC_Type::RESERVED
__IM uint32_t RESERVED
Definition LPC176x5x.h:774
LPC_ADC_Type::TRM
__IOM uint32_t TRM
Definition LPC176x5x.h:786
LPC_ADC_Type::CR
__IOM uint32_t CR
Definition LPC176x5x.h:768
LPC_CAN1_Type
CAN1 controller (CAN1)
Definition LPC176x5x.h:857
LPC_CAN1_Type::GSR
__IM uint32_t GSR
Definition LPC176x5x.h:861
LPC_CAN1_Type::TDB3
__IOM uint32_t TDB3
Definition LPC176x5x.h:891
LPC_CAN1_Type::SR
__IM uint32_t SR
Definition LPC176x5x.h:871
LPC_CAN1_Type::TDA2
__IOM uint32_t TDA2
Definition LPC176x5x.h:886
LPC_CAN1_Type::CMR
__OM uint32_t CMR
Definition LPC176x5x.h:859
LPC_CAN1_Type::RFS
__IOM uint32_t RFS
Definition LPC176x5x.h:872
LPC_CAN1_Type::TDB2
__IOM uint32_t TDB2
Definition LPC176x5x.h:887
LPC_CAN1_Type::IER
__IOM uint32_t IER
Definition LPC176x5x.h:866
LPC_CAN1_Type::TFI3
__IOM uint32_t TFI3
Definition LPC176x5x.h:888
LPC_CAN1_Type::TID2
__IOM uint32_t TID2
Definition LPC176x5x.h:885
LPC_CAN1_Type::ICR
__IM uint32_t ICR
Definition LPC176x5x.h:864
LPC_CAN1_Type::TID1
__IOM uint32_t TID1
Definition LPC176x5x.h:881
LPC_CAN1_Type::BTR
__IOM uint32_t BTR
Definition LPC176x5x.h:867
LPC_CAN1_Type::EWL
__IOM uint32_t EWL
Definition LPC176x5x.h:869
LPC_CAN1_Type::TID3
__IOM uint32_t TID3
Definition LPC176x5x.h:889
LPC_CAN1_Type::RID
__IOM uint32_t RID
Definition LPC176x5x.h:874
LPC_CAN1_Type::TDA1
__IOM uint32_t TDA1
Definition LPC176x5x.h:882
LPC_CAN1_Type::RDB
__IOM uint32_t RDB
Definition LPC176x5x.h:878
LPC_CAN1_Type::TFI1
__IOM uint32_t TFI1
Definition LPC176x5x.h:880
LPC_CAN1_Type::TDB1
__IOM uint32_t TDB1
Definition LPC176x5x.h:883
LPC_CAN1_Type::TDA3
__IOM uint32_t TDA3
Definition LPC176x5x.h:890
LPC_CAN1_Type::RDA
__IOM uint32_t RDA
Definition LPC176x5x.h:876
LPC_CAN1_Type::MOD
__IOM uint32_t MOD
Definition LPC176x5x.h:858
LPC_CAN1_Type::TFI2
__IOM uint32_t TFI2
Definition LPC176x5x.h:884
LPC_CAN2_Type
CAN1 controller (CAN2)
Definition LPC176x5x.h:905
LPC_CAN2_Type::CMR
__OM uint32_t CMR
Definition LPC176x5x.h:907
LPC_CAN2_Type::SR
__IM uint32_t SR
Definition LPC176x5x.h:919
LPC_CAN2_Type::RDA
__IOM uint32_t RDA
Definition LPC176x5x.h:924
LPC_CAN2_Type::TID1
__IOM uint32_t TID1
Definition LPC176x5x.h:929
LPC_CAN2_Type::TDB1
__IOM uint32_t TDB1
Definition LPC176x5x.h:931
LPC_CAN2_Type::RID
__IOM uint32_t RID
Definition LPC176x5x.h:922
LPC_CAN2_Type::TDB3
__IOM uint32_t TDB3
Definition LPC176x5x.h:939
LPC_CAN2_Type::RFS
__IOM uint32_t RFS
Definition LPC176x5x.h:920
LPC_CAN2_Type::IER
__IOM uint32_t IER
Definition LPC176x5x.h:914
LPC_CAN2_Type::TFI2
__IOM uint32_t TFI2
Definition LPC176x5x.h:932
LPC_CAN2_Type::RDB
__IOM uint32_t RDB
Definition LPC176x5x.h:926
LPC_CAN2_Type::TDA3
__IOM uint32_t TDA3
Definition LPC176x5x.h:938
LPC_CAN2_Type::TID3
__IOM uint32_t TID3
Definition LPC176x5x.h:937
LPC_CAN2_Type::TID2
__IOM uint32_t TID2
Definition LPC176x5x.h:933
LPC_CAN2_Type::TFI1
__IOM uint32_t TFI1
Definition LPC176x5x.h:928
LPC_CAN2_Type::BTR
__IOM uint32_t BTR
Definition LPC176x5x.h:915
LPC_CAN2_Type::TDA1
__IOM uint32_t TDA1
Definition LPC176x5x.h:930
LPC_CAN2_Type::GSR
__IM uint32_t GSR
Definition LPC176x5x.h:909
LPC_CAN2_Type::TDA2
__IOM uint32_t TDA2
Definition LPC176x5x.h:934
LPC_CAN2_Type::TDB2
__IOM uint32_t TDB2
Definition LPC176x5x.h:935
LPC_CAN2_Type::ICR
__IM uint32_t ICR
Definition LPC176x5x.h:912
LPC_CAN2_Type::MOD
__IOM uint32_t MOD
Definition LPC176x5x.h:906
LPC_CAN2_Type::EWL
__IOM uint32_t EWL
Definition LPC176x5x.h:917
LPC_CAN2_Type::TFI3
__IOM uint32_t TFI3
Definition LPC176x5x.h:936
LPC_CANAFRAM_Type
CAN acceptance filter RAM (CANAFRAM)
Definition LPC176x5x.h:800
LPC_CANAF_Type
CAN controller acceptance filter (CANAF)
Definition LPC176x5x.h:815
LPC_CANAF_Type::AFMR
__IOM uint32_t AFMR
Definition LPC176x5x.h:816
LPC_CANAF_Type::SFF_SA
__IOM uint32_t SFF_SA
Definition LPC176x5x.h:817
LPC_CANAF_Type::FCANIC1
__IOM uint32_t FCANIC1
Definition LPC176x5x.h:826
LPC_CANAF_Type::EFF_GRP_SA
__IOM uint32_t EFF_GRP_SA
Definition LPC176x5x.h:820
LPC_CANAF_Type::FCANIE
__IOM uint32_t FCANIE
Definition LPC176x5x.h:824
LPC_CANAF_Type::ENDOFTABLE
__IOM uint32_t ENDOFTABLE
Definition LPC176x5x.h:821
LPC_CANAF_Type::LUTERR
__IM uint32_t LUTERR
Definition LPC176x5x.h:823
LPC_CANAF_Type::EFF_SA
__IOM uint32_t EFF_SA
Definition LPC176x5x.h:819
LPC_CANAF_Type::LUTERRAD
__IM uint32_t LUTERRAD
Definition LPC176x5x.h:822
LPC_CANAF_Type::FCANIC0
__IOM uint32_t FCANIC0
Definition LPC176x5x.h:825
LPC_CANAF_Type::SFF_GRP_SA
__IOM uint32_t SFF_GRP_SA
Definition LPC176x5x.h:818
LPC_CCAN_Type
Central CAN controller (CCAN)
Definition LPC176x5x.h:840
LPC_CCAN_Type::RXSR
__IM uint32_t RXSR
Definition LPC176x5x.h:842
LPC_CCAN_Type::TXSR
__IM uint32_t TXSR
Definition LPC176x5x.h:841
LPC_CCAN_Type::MSR
__IM uint32_t MSR
Definition LPC176x5x.h:843
LPC_DAC_Type
Digital-to-Analog Converter (DAC) (DAC)
Definition LPC176x5x.h:980
LPC_DAC_Type::CTRL
__IOM uint32_t CTRL
Definition LPC176x5x.h:984
LPC_DAC_Type::CNTVAL
__IOM uint32_t CNTVAL
Definition LPC176x5x.h:986
LPC_DAC_Type::CR
__IOM uint32_t CR
Definition LPC176x5x.h:981
LPC_EMAC_Type
Ethernet (EMAC)
Definition LPC176x5x.h:1438
LPC_EMAC_Type::TXSTATUS
__IOM uint32_t TXSTATUS
Definition LPC176x5x.h:1466
LPC_EMAC_Type::HASHFILTERH
__IOM uint32_t HASHFILTERH
Definition LPC176x5x.h:1483
LPC_EMAC_Type::INTCLEAR
__OM uint32_t INTCLEAR
Definition LPC176x5x.h:1487
LPC_EMAC_Type::RXFILTERWOLCLEAR
__OM uint32_t RXFILTERWOLCLEAR
Definition LPC176x5x.h:1480
LPC_EMAC_Type::RESERVED7
__IM uint32_t RESERVED7
Definition LPC176x5x.h:1489
LPC_EMAC_Type::MADR
__IOM uint32_t MADR
Definition LPC176x5x.h:1449
LPC_EMAC_Type::SUPP
__IOM uint32_t SUPP
Definition LPC176x5x.h:1445
LPC_EMAC_Type::TSV0
__IM uint32_t TSV0
Definition LPC176x5x.h:1471
LPC_EMAC_Type::MAC2
__IOM uint32_t MAC2
Definition LPC176x5x.h:1440
LPC_EMAC_Type::RXFILTERWOLSTATUS
__IM uint32_t RXFILTERWOLSTATUS
Definition LPC176x5x.h:1479
LPC_EMAC_Type::FLOWCONTROLCOUNTER
__IOM uint32_t FLOWCONTROLCOUNTER
Definition LPC176x5x.h:1475
LPC_EMAC_Type::TSV1
__IM uint32_t TSV1
Definition LPC176x5x.h:1472
LPC_EMAC_Type::TXDESCRIPTOR
__IOM uint32_t TXDESCRIPTOR
Definition LPC176x5x.h:1465
LPC_EMAC_Type::INTSET
__OM uint32_t INTSET
Definition LPC176x5x.h:1488
LPC_EMAC_Type::RXDESCRIPTOR
__IOM uint32_t RXDESCRIPTOR
Definition LPC176x5x.h:1460
LPC_EMAC_Type::SA1
__IOM uint32_t SA1
Definition LPC176x5x.h:1455
LPC_EMAC_Type::FLOWCONTROLSTATUS
__IM uint32_t FLOWCONTROLSTATUS
Definition LPC176x5x.h:1476
LPC_EMAC_Type::POWERDOWN
__IOM uint32_t POWERDOWN
Definition LPC176x5x.h:1490
LPC_EMAC_Type::COMMAND
__IOM uint32_t COMMAND
Definition LPC176x5x.h:1458
LPC_EMAC_Type::RXSTATUS
__IOM uint32_t RXSTATUS
Definition LPC176x5x.h:1461
LPC_EMAC_Type::MAXF
__IOM uint32_t MAXF
Definition LPC176x5x.h:1444
LPC_EMAC_Type::STATUS
__IM uint32_t STATUS
Definition LPC176x5x.h:1459
LPC_EMAC_Type::MCFG
__IOM uint32_t MCFG
Definition LPC176x5x.h:1447
LPC_EMAC_Type::IPGT
__IOM uint32_t IPGT
Definition LPC176x5x.h:1441
LPC_EMAC_Type::MRDD
__IM uint32_t MRDD
Definition LPC176x5x.h:1451
LPC_EMAC_Type::TXDESCRIPTORNUMBER
__IOM uint32_t TXDESCRIPTORNUMBER
Definition LPC176x5x.h:1467
LPC_EMAC_Type::INTENABLE
__IOM uint32_t INTENABLE
Definition LPC176x5x.h:1486
LPC_EMAC_Type::RXPRODUCEINDEX
__IM uint32_t RXPRODUCEINDEX
Definition LPC176x5x.h:1463
LPC_EMAC_Type::TXPRODUCEINDEX
__IOM uint32_t TXPRODUCEINDEX
Definition LPC176x5x.h:1468
LPC_EMAC_Type::RESERVED5
__IM uint32_t RESERVED5
Definition LPC176x5x.h:1481
LPC_EMAC_Type::CLRT
__IOM uint32_t CLRT
Definition LPC176x5x.h:1443
LPC_EMAC_Type::INTSTATUS
__IM uint32_t INTSTATUS
Definition LPC176x5x.h:1485
LPC_EMAC_Type::TXCONSUMEINDEX
__IM uint32_t TXCONSUMEINDEX
Definition LPC176x5x.h:1469
LPC_EMAC_Type::MIND
__IM uint32_t MIND
Definition LPC176x5x.h:1452
LPC_EMAC_Type::RXFILTERCTRL
__IOM uint32_t RXFILTERCTRL
Definition LPC176x5x.h:1478
LPC_EMAC_Type::SA0
__IOM uint32_t SA0
Definition LPC176x5x.h:1454
LPC_EMAC_Type::TEST
__IOM uint32_t TEST
Definition LPC176x5x.h:1446
LPC_EMAC_Type::RSV
__IM uint32_t RSV
Definition LPC176x5x.h:1473
LPC_EMAC_Type::IPGR
__IOM uint32_t IPGR
Definition LPC176x5x.h:1442
LPC_EMAC_Type::SA2
__IOM uint32_t SA2
Definition LPC176x5x.h:1456
LPC_EMAC_Type::RXCONSUMEINDEX
__IOM uint32_t RXCONSUMEINDEX
Definition LPC176x5x.h:1464
LPC_EMAC_Type::MWTD
__OM uint32_t MWTD
Definition LPC176x5x.h:1450
LPC_EMAC_Type::RXDESCRIPTORNUMBER
__IOM uint32_t RXDESCRIPTORNUMBER
Definition LPC176x5x.h:1462
LPC_EMAC_Type::MAC1
__IOM uint32_t MAC1
Definition LPC176x5x.h:1439
LPC_EMAC_Type::HASHFILTERL
__IOM uint32_t HASHFILTERL
Definition LPC176x5x.h:1482
LPC_EMAC_Type::MCMD
__IOM uint32_t MCMD
Definition LPC176x5x.h:1448
LPC_GPDMA_Type
General purpose DMA controller (GPDMA)
Definition LPC176x5x.h:1504
LPC_GPDMA_Type::SRCADDR1
__IOM uint32_t SRCADDR1
Definition LPC176x5x.h:1526
LPC_GPDMA_Type::CONTROL7
__IOM uint32_t CONTROL7
Definition LPC176x5x.h:1565
LPC_GPDMA_Type::LLI1
__IOM uint32_t LLI1
Definition LPC176x5x.h:1528
LPC_GPDMA_Type::INTTCCLEAR
__OM uint32_t INTTCCLEAR
Definition LPC176x5x.h:1507
LPC_GPDMA_Type::CONTROL6
__IOM uint32_t CONTROL6
Definition LPC176x5x.h:1559
LPC_GPDMA_Type::DESTADDR3
__IOM uint32_t DESTADDR3
Definition LPC176x5x.h:1539
LPC_GPDMA_Type::CONFIG7
__IOM uint32_t CONFIG7
Definition LPC176x5x.h:1566
LPC_GPDMA_Type::SOFTBREQ
__IOM uint32_t SOFTBREQ
Definition LPC176x5x.h:1513
LPC_GPDMA_Type::CONFIG
__IOM uint32_t CONFIG
Definition LPC176x5x.h:1517
LPC_GPDMA_Type::RAWINTERRSTAT
__IM uint32_t RAWINTERRSTAT
Definition LPC176x5x.h:1511
LPC_GPDMA_Type::SRCADDR4
__IOM uint32_t SRCADDR4
Definition LPC176x5x.h:1544
LPC_GPDMA_Type::DESTADDR2
__IOM uint32_t DESTADDR2
Definition LPC176x5x.h:1533
LPC_GPDMA_Type::SRCADDR3
__IOM uint32_t SRCADDR3
Definition LPC176x5x.h:1538
LPC_GPDMA_Type::INTTCSTAT
__IM uint32_t INTTCSTAT
Definition LPC176x5x.h:1506
LPC_GPDMA_Type::SRCADDR5
__IOM uint32_t SRCADDR5
Definition LPC176x5x.h:1550
LPC_GPDMA_Type::DESTADDR5
__IOM uint32_t DESTADDR5
Definition LPC176x5x.h:1551
LPC_GPDMA_Type::CONTROL2
__IOM uint32_t CONTROL2
Definition LPC176x5x.h:1535
LPC_GPDMA_Type::CONFIG3
__IOM uint32_t CONFIG3
Definition LPC176x5x.h:1542
LPC_GPDMA_Type::INTSTAT
__IM uint32_t INTSTAT
Definition LPC176x5x.h:1505
LPC_GPDMA_Type::CONTROL1
__IOM uint32_t CONTROL1
Definition LPC176x5x.h:1529
LPC_GPDMA_Type::CONFIG6
__IOM uint32_t CONFIG6
Definition LPC176x5x.h:1560
LPC_GPDMA_Type::SRCADDR7
__IOM uint32_t SRCADDR7
Definition LPC176x5x.h:1562
LPC_GPDMA_Type::SRCADDR2
__IOM uint32_t SRCADDR2
Definition LPC176x5x.h:1532
LPC_GPDMA_Type::LLI2
__IOM uint32_t LLI2
Definition LPC176x5x.h:1534
LPC_GPDMA_Type::SOFTLSREQ
__IOM uint32_t SOFTLSREQ
Definition LPC176x5x.h:1516
LPC_GPDMA_Type::LLI4
__IOM uint32_t LLI4
Definition LPC176x5x.h:1546
LPC_GPDMA_Type::DESTADDR0
__IOM uint32_t DESTADDR0
Definition LPC176x5x.h:1521
LPC_GPDMA_Type::CONFIG2
__IOM uint32_t CONFIG2
Definition LPC176x5x.h:1536
LPC_GPDMA_Type::DESTADDR1
__IOM uint32_t DESTADDR1
Definition LPC176x5x.h:1527
LPC_GPDMA_Type::CONFIG4
__IOM uint32_t CONFIG4
Definition LPC176x5x.h:1548
LPC_GPDMA_Type::SOFTLBREQ
__IOM uint32_t SOFTLBREQ
Definition LPC176x5x.h:1515
LPC_GPDMA_Type::DESTADDR6
__IOM uint32_t DESTADDR6
Definition LPC176x5x.h:1557
LPC_GPDMA_Type::CONTROL5
__IOM uint32_t CONTROL5
Definition LPC176x5x.h:1553
LPC_GPDMA_Type::CONTROL4
__IOM uint32_t CONTROL4
Definition LPC176x5x.h:1547
LPC_GPDMA_Type::DESTADDR7
__IOM uint32_t DESTADDR7
Definition LPC176x5x.h:1563
LPC_GPDMA_Type::ENBLDCHNS
__IM uint32_t ENBLDCHNS
Definition LPC176x5x.h:1512
LPC_GPDMA_Type::SYNC
__IOM uint32_t SYNC
Definition LPC176x5x.h:1518
LPC_GPDMA_Type::CONTROL3
__IOM uint32_t CONTROL3
Definition LPC176x5x.h:1541
LPC_GPDMA_Type::DESTADDR4
__IOM uint32_t DESTADDR4
Definition LPC176x5x.h:1545
LPC_GPDMA_Type::INTERRCLR
__OM uint32_t INTERRCLR
Definition LPC176x5x.h:1509
LPC_GPDMA_Type::LLI3
__IOM uint32_t LLI3
Definition LPC176x5x.h:1540
LPC_GPDMA_Type::CONTROL0
__IOM uint32_t CONTROL0
Definition LPC176x5x.h:1523
LPC_GPDMA_Type::SRCADDR0
__IOM uint32_t SRCADDR0
Definition LPC176x5x.h:1520
LPC_GPDMA_Type::SOFTSREQ
__IOM uint32_t SOFTSREQ
Definition LPC176x5x.h:1514
LPC_GPDMA_Type::CONFIG5
__IOM uint32_t CONFIG5
Definition LPC176x5x.h:1554
LPC_GPDMA_Type::RAWINTTCSTAT
__IM uint32_t RAWINTTCSTAT
Definition LPC176x5x.h:1510
LPC_GPDMA_Type::LLI5
__IOM uint32_t LLI5
Definition LPC176x5x.h:1552
LPC_GPDMA_Type::SRCADDR6
__IOM uint32_t SRCADDR6
Definition LPC176x5x.h:1556
LPC_GPDMA_Type::LLI0
__IOM uint32_t LLI0
Definition LPC176x5x.h:1522
LPC_GPDMA_Type::LLI6
__IOM uint32_t LLI6
Definition LPC176x5x.h:1558
LPC_GPDMA_Type::CONFIG0
__IOM uint32_t CONFIG0
Definition LPC176x5x.h:1524
LPC_GPDMA_Type::INTERRSTAT
__IM uint32_t INTERRSTAT
Definition LPC176x5x.h:1508
LPC_GPDMA_Type::CONFIG1
__IOM uint32_t CONFIG1
Definition LPC176x5x.h:1530
LPC_GPDMA_Type::LLI7
__IOM uint32_t LLI7
Definition LPC176x5x.h:1564
LPC_GPIOINT_Type
GPIO (GPIOINT)
Definition LPC176x5x.h:666
LPC_GPIOINT_Type::ENR0
__IOM uint32_t ENR0
Definition LPC176x5x.h:673
LPC_GPIOINT_Type::ENF0
__IOM uint32_t ENF0
Definition LPC176x5x.h:675
LPC_GPIOINT_Type::STATF0
__IM uint32_t STATF0
Definition LPC176x5x.h:670
LPC_GPIOINT_Type::STATF2
__IM uint32_t STATF2
Definition LPC176x5x.h:680
LPC_GPIOINT_Type::STATUS
__IM uint32_t STATUS
Definition LPC176x5x.h:667
LPC_GPIOINT_Type::ENF2
__IOM uint32_t ENF2
Definition LPC176x5x.h:685
LPC_GPIOINT_Type::ENR2
__IOM uint32_t ENR2
Definition LPC176x5x.h:683
LPC_GPIOINT_Type::CLR2
__OM uint32_t CLR2
Definition LPC176x5x.h:682
LPC_GPIOINT_Type::CLR0
__OM uint32_t CLR0
Definition LPC176x5x.h:672
LPC_GPIOINT_Type::STATR2
__IM uint32_t STATR2
Definition LPC176x5x.h:678
LPC_GPIOINT_Type::STATR0
__IM uint32_t STATR0
Definition LPC176x5x.h:668
LPC_GPIO_Type
General Purpose I/O (GPIO)
Definition LPC176x5x.h:1665
LPC_GPIO_Type::PIN1
__IOM uint32_t PIN1
Definition LPC176x5x.h:1675
LPC_GPIO_Type::CLR4
__OM uint32_t CLR4
Definition LPC176x5x.h:1695
LPC_GPIO_Type::MASK1
__IOM uint32_t MASK1
Definition LPC176x5x.h:1674
LPC_GPIO_Type::SET1
__IOM uint32_t SET1
Definition LPC176x5x.h:1676
LPC_GPIO_Type::CLR0
__OM uint32_t CLR0
Definition LPC176x5x.h:1671
LPC_GPIO_Type::MASK3
__IOM uint32_t MASK3
Definition LPC176x5x.h:1686
LPC_GPIO_Type::PIN2
__IOM uint32_t PIN2
Definition LPC176x5x.h:1681
LPC_GPIO_Type::DIR3
__IOM uint32_t DIR3
Definition LPC176x5x.h:1684
LPC_GPIO_Type::DIR1
__IOM uint32_t DIR1
Definition LPC176x5x.h:1672
LPC_GPIO_Type::SET3
__IOM uint32_t SET3
Definition LPC176x5x.h:1688
LPC_GPIO_Type::SET4
__IOM uint32_t SET4
Definition LPC176x5x.h:1694
LPC_GPIO_Type::SET0
__IOM uint32_t SET0
Definition LPC176x5x.h:1670
LPC_GPIO_Type::PIN0
__IOM uint32_t PIN0
Definition LPC176x5x.h:1669
LPC_GPIO_Type::DIR0
__IOM uint32_t DIR0
Definition LPC176x5x.h:1666
LPC_GPIO_Type::SET2
__IOM uint32_t SET2
Definition LPC176x5x.h:1682
LPC_GPIO_Type::DIR2
__IOM uint32_t DIR2
Definition LPC176x5x.h:1678
LPC_GPIO_Type::CLR1
__OM uint32_t CLR1
Definition LPC176x5x.h:1677
LPC_GPIO_Type::CLR3
__OM uint32_t CLR3
Definition LPC176x5x.h:1689
LPC_GPIO_Type::MASK4
__IOM uint32_t MASK4
Definition LPC176x5x.h:1692
LPC_GPIO_Type::CLR2
__OM uint32_t CLR2
Definition LPC176x5x.h:1683
LPC_GPIO_Type::PIN3
__IOM uint32_t PIN3
Definition LPC176x5x.h:1687
LPC_GPIO_Type::MASK2
__IOM uint32_t MASK2
Definition LPC176x5x.h:1680
LPC_GPIO_Type::PIN4
__IOM uint32_t PIN4
Definition LPC176x5x.h:1693
LPC_GPIO_Type::DIR4
__IOM uint32_t DIR4
Definition LPC176x5x.h:1690
LPC_GPIO_Type::MASK0
__IOM uint32_t MASK0
Definition LPC176x5x.h:1668
LPC_I2C0_Type
I2C bus interface (I2C0)
Definition LPC176x5x.h:521
LPC_I2C0_Type::ADR2
__IOM uint32_t ADR2
Definition LPC176x5x.h:561
LPC_I2C0_Type::CONSET
__IOM uint32_t CONSET
Definition LPC176x5x.h:522
LPC_I2C0_Type::ADR1
__IOM uint32_t ADR1
Definition LPC176x5x.h:555
LPC_I2C0_Type::CONCLR
__OM uint32_t CONCLR
Definition LPC176x5x.h:549
LPC_I2C0_Type::SCLH
__IOM uint32_t SCLH
Definition LPC176x5x.h:542
LPC_I2C0_Type::ADR0
__IOM uint32_t ADR0
Definition LPC176x5x.h:536
LPC_I2C0_Type::DATA_BUFFER
__IM uint32_t DATA_BUFFER
Definition LPC176x5x.h:573
LPC_I2C0_Type::SCLL
__IOM uint32_t SCLL
Definition LPC176x5x.h:544
LPC_I2C0_Type::STAT
__IM uint32_t STAT
Definition LPC176x5x.h:527
LPC_I2C0_Type::DAT
__IOM uint32_t DAT
Definition LPC176x5x.h:531
LPC_I2C0_Type::MMCTRL
__IOM uint32_t MMCTRL
Definition LPC176x5x.h:554
LPC_I2C0_Type::ADR3
__IOM uint32_t ADR3
Definition LPC176x5x.h:567
LPC_I2S_Type
I2S interface (I2S)
Definition LPC176x5x.h:1244
LPC_I2S_Type::DAO
__IOM uint32_t DAO
Definition LPC176x5x.h:1245
LPC_I2S_Type::DAI
__IOM uint32_t DAI
Definition LPC176x5x.h:1247
LPC_I2S_Type::RXRATE
__IOM uint32_t RXRATE
Definition LPC176x5x.h:1265
LPC_I2S_Type::STATE
__IM uint32_t STATE
Definition LPC176x5x.h:1253
LPC_I2S_Type::TXFIFO
__OM uint32_t TXFIFO
Definition LPC176x5x.h:1249
LPC_I2S_Type::DMA2
__IOM uint32_t DMA2
Definition LPC176x5x.h:1257
LPC_I2S_Type::RXFIFO
__IM uint32_t RXFIFO
Definition LPC176x5x.h:1251
LPC_I2S_Type::RXMODE
__IOM uint32_t RXMODE
Definition LPC176x5x.h:1277
LPC_I2S_Type::DMA1
__IOM uint32_t DMA1
Definition LPC176x5x.h:1255
LPC_I2S_Type::IRQ
__IOM uint32_t IRQ
Definition LPC176x5x.h:1259
LPC_I2S_Type::TXMODE
__IOM uint32_t TXMODE
Definition LPC176x5x.h:1276
LPC_I2S_Type::TXRATE
__IOM uint32_t TXRATE
Definition LPC176x5x.h:1262
LPC_I2S_Type::TXBITRATE
__IOM uint32_t TXBITRATE
Definition LPC176x5x.h:1268
LPC_I2S_Type::RXBITRATE
__IOM uint32_t RXBITRATE
Definition LPC176x5x.h:1272
LPC_MCPWM_Type
Motor Control PWM (MCPWM)
Definition LPC176x5x.h:1312
LPC_MCPWM_Type::CON
__IM uint32_t CON
Definition LPC176x5x.h:1313
LPC_MCPWM_Type::CON_CLR
__OM uint32_t CON_CLR
Definition LPC176x5x.h:1315
LPC_MCPWM_Type::INTEN
__IM uint32_t INTEN
Definition LPC176x5x.h:1325
LPC_MCPWM_Type::CNTCON_CLR
__OM uint32_t CNTCON_CLR
Definition LPC176x5x.h:1330
LPC_MCPWM_Type::CON_SET
__OM uint32_t CON_SET
Definition LPC176x5x.h:1314
LPC_MCPWM_Type::CAPCON_SET
__OM uint32_t CAPCON_SET
Definition LPC176x5x.h:1317
LPC_MCPWM_Type::DT
__IOM uint32_t DT
Definition LPC176x5x.h:1322
LPC_MCPWM_Type::INTEN_CLR
__OM uint32_t INTEN_CLR
Definition LPC176x5x.h:1327
LPC_MCPWM_Type::CAPCON
__IM uint32_t CAPCON
Definition LPC176x5x.h:1316
LPC_MCPWM_Type::CAP_CLR
__OM uint32_t CAP_CLR
Definition LPC176x5x.h:1334
LPC_MCPWM_Type::INTF_CLR
__OM uint32_t INTF_CLR
Definition LPC176x5x.h:1333
LPC_MCPWM_Type::INTEN_SET
__OM uint32_t INTEN_SET
Definition LPC176x5x.h:1326
LPC_MCPWM_Type::INTF
__IM uint32_t INTF
Definition LPC176x5x.h:1331
LPC_MCPWM_Type::CAPCON_CLR
__OM uint32_t CAPCON_CLR
Definition LPC176x5x.h:1318
LPC_MCPWM_Type::CNTCON_SET
__OM uint32_t CNTCON_SET
Definition LPC176x5x.h:1329
LPC_MCPWM_Type::CNTCON
__IM uint32_t CNTCON
Definition LPC176x5x.h:1328
LPC_MCPWM_Type::CP
__IOM uint32_t CP
Definition LPC176x5x.h:1323
LPC_MCPWM_Type::INTF_SET
__OM uint32_t INTF_SET
Definition LPC176x5x.h:1332
LPC_PINCONNECT_Type
Pin connect block (PINCONNECT)
Definition LPC176x5x.h:700
LPC_PINCONNECT_Type::PINSEL3
__IOM uint32_t PINSEL3
Definition LPC176x5x.h:704
LPC_PINCONNECT_Type::PINSEL7
__IOM uint32_t PINSEL7
Definition LPC176x5x.h:707
LPC_PINCONNECT_Type::RESERVED1
__IM uint32_t RESERVED1
Definition LPC176x5x.h:708
LPC_PINCONNECT_Type::PINSEL1
__IOM uint32_t PINSEL1
Definition LPC176x5x.h:702
LPC_PINCONNECT_Type::PINMODE7
__IOM uint32_t PINMODE7
Definition LPC176x5x.h:718
LPC_PINCONNECT_Type::I2CPADCFG
__IOM uint32_t I2CPADCFG
Definition LPC176x5x.h:726
LPC_PINCONNECT_Type::PINMODE_OD1
__IOM uint32_t PINMODE_OD1
Definition LPC176x5x.h:722
LPC_PINCONNECT_Type::RESERVED4
__IM uint32_t RESERVED4
Definition LPC176x5x.h:719
LPC_PINCONNECT_Type::PINMODE_OD0
__IOM uint32_t PINMODE_OD0
Definition LPC176x5x.h:721
LPC_PINCONNECT_Type::PINMODE4
__IOM uint32_t PINMODE4
Definition LPC176x5x.h:716
LPC_PINCONNECT_Type::PINMODE3
__IOM uint32_t PINMODE3
Definition LPC176x5x.h:715
LPC_PINCONNECT_Type::PINSEL10
__IOM uint32_t PINSEL10
Definition LPC176x5x.h:710
LPC_PINCONNECT_Type::PINSEL4
__IOM uint32_t PINSEL4
Definition LPC176x5x.h:705
LPC_PINCONNECT_Type::PINSEL2
__IOM uint32_t PINSEL2
Definition LPC176x5x.h:703
LPC_PINCONNECT_Type::PINMODE_OD4
__IOM uint32_t PINMODE_OD4
Definition LPC176x5x.h:725
LPC_PINCONNECT_Type::PINMODE_OD2
__IOM uint32_t PINMODE_OD2
Definition LPC176x5x.h:723
LPC_PINCONNECT_Type::PINMODE_OD3
__IOM uint32_t PINMODE_OD3
Definition LPC176x5x.h:724
LPC_PINCONNECT_Type::PINMODE1
__IOM uint32_t PINMODE1
Definition LPC176x5x.h:713
LPC_PINCONNECT_Type::PINSEL0
__IOM uint32_t PINSEL0
Definition LPC176x5x.h:701
LPC_PINCONNECT_Type::PINMODE9
__IOM uint32_t PINMODE9
Definition LPC176x5x.h:720
LPC_PINCONNECT_Type::PINMODE2
__IOM uint32_t PINMODE2
Definition LPC176x5x.h:714
LPC_PINCONNECT_Type::PINSEL9
__IOM uint32_t PINSEL9
Definition LPC176x5x.h:709
LPC_PINCONNECT_Type::PINMODE0
__IOM uint32_t PINMODE0
Definition LPC176x5x.h:712
LPC_PWM1_Type
Pulse Width Modulators (PWM1) (PWM1)
Definition LPC176x5x.h:453
LPC_PWM1_Type::MR0
__IOM uint32_t MR0
Definition LPC176x5x.h:469
LPC_PWM1_Type::PCR
__IOM uint32_t PCR
Definition LPC176x5x.h:499
LPC_PWM1_Type::MR1
__IOM uint32_t MR1
Definition LPC176x5x.h:472
LPC_PWM1_Type::MR4
__IOM uint32_t MR4
Definition LPC176x5x.h:490
LPC_PWM1_Type::IR
__IOM uint32_t IR
Definition LPC176x5x.h:454
LPC_PWM1_Type::MR3
__IOM uint32_t MR3
Definition LPC176x5x.h:478
LPC_PWM1_Type::PR
__IOM uint32_t PR
Definition LPC176x5x.h:462
LPC_PWM1_Type::PC
__IOM uint32_t PC
Definition LPC176x5x.h:464
LPC_PWM1_Type::MR2
__IOM uint32_t MR2
Definition LPC176x5x.h:475
LPC_PWM1_Type::TC
__IOM uint32_t TC
Definition LPC176x5x.h:459
LPC_PWM1_Type::LER
__IOM uint32_t LER
Definition LPC176x5x.h:502
LPC_PWM1_Type::TCR
__IOM uint32_t TCR
Definition LPC176x5x.h:457
LPC_PWM1_Type::MCR
__IOM uint32_t MCR
Definition LPC176x5x.h:466
LPC_PWM1_Type::MR6
__IOM uint32_t MR6
Definition LPC176x5x.h:496
LPC_PWM1_Type::CTCR
__IOM uint32_t CTCR
Definition LPC176x5x.h:505
LPC_PWM1_Type::MR5
__IOM uint32_t MR5
Definition LPC176x5x.h:493
LPC_PWM1_Type::CCR
__IOM uint32_t CCR
Definition LPC176x5x.h:481
LPC_QEI_Type
Quadrature Encoder Interface (QEI) (QEI)
Definition LPC176x5x.h:1348
LPC_QEI_Type::IE
__IM uint32_t IE
Definition LPC176x5x.h:1369
LPC_QEI_Type::TIME
__IM uint32_t TIME
Definition LPC176x5x.h:1360
LPC_QEI_Type::POS
__IM uint32_t POS
Definition LPC176x5x.h:1352
LPC_QEI_Type::INXCNT
__IM uint32_t INXCNT
Definition LPC176x5x.h:1357
LPC_QEI_Type::SET
__OM uint32_t SET
Definition LPC176x5x.h:1371
LPC_QEI_Type::INTSTAT
__IM uint32_t INTSTAT
Definition LPC176x5x.h:1368
LPC_QEI_Type::CLR
__OM uint32_t CLR
Definition LPC176x5x.h:1370
LPC_QEI_Type::STAT
__IM uint32_t STAT
Definition LPC176x5x.h:1350
LPC_QEI_Type::VEL
__IM uint32_t VEL
Definition LPC176x5x.h:1361
LPC_QEI_Type::INXCMP0
__IOM uint32_t INXCMP0
Definition LPC176x5x.h:1358
LPC_QEI_Type::CMPOS0
__IOM uint32_t CMPOS0
Definition LPC176x5x.h:1354
LPC_QEI_Type::IES
__OM uint32_t IES
Definition LPC176x5x.h:1367
LPC_QEI_Type::CONF
__IOM uint32_t CONF
Definition LPC176x5x.h:1351
LPC_QEI_Type::CAP
__IM uint32_t CAP
Definition LPC176x5x.h:1362
LPC_QEI_Type::CON
__OM uint32_t CON
Definition LPC176x5x.h:1349
LPC_QEI_Type::CMPOS1
__IOM uint32_t CMPOS1
Definition LPC176x5x.h:1355
LPC_QEI_Type::CMPOS2
__IOM uint32_t CMPOS2
Definition LPC176x5x.h:1356
LPC_QEI_Type::LOAD
__IOM uint32_t LOAD
Definition LPC176x5x.h:1359
LPC_QEI_Type::MAXPOS
__IOM uint32_t MAXPOS
Definition LPC176x5x.h:1353
LPC_QEI_Type::VELCOMP
__IOM uint32_t VELCOMP
Definition LPC176x5x.h:1363
LPC_QEI_Type::FILTER
__IOM uint32_t FILTER
Definition LPC176x5x.h:1364
LPC_QEI_Type::IEC
__OM uint32_t IEC
Definition LPC176x5x.h:1366
LPC_RITIMER_Type
Repetitive Interrupt Timer (RIT) (RITIMER)
Definition LPC176x5x.h:1291
LPC_RITIMER_Type::MASK
__IOM uint32_t MASK
Definition LPC176x5x.h:1293
LPC_RITIMER_Type::COUNTER
__IOM uint32_t COUNTER
Definition LPC176x5x.h:1298
LPC_RITIMER_Type::CTRL
__IOM uint32_t CTRL
Definition LPC176x5x.h:1297
LPC_RITIMER_Type::COMPVAL
__IOM uint32_t COMPVAL
Definition LPC176x5x.h:1292
LPC_RTC_Type
Real Time Clock (RTC) (RTC)
Definition LPC176x5x.h:620
LPC_RTC_Type::CTIME2
__IM uint32_t CTIME2
Definition LPC176x5x.h:628
LPC_RTC_Type::MONTH
__IOM uint32_t MONTH
Definition LPC176x5x.h:635
LPC_RTC_Type::ADOY
__IOM uint32_t ADOY
Definition LPC176x5x.h:650
LPC_RTC_Type::MIN
__IOM uint32_t MIN
Definition LPC176x5x.h:630
LPC_RTC_Type::AMON
__IOM uint32_t AMON
Definition LPC176x5x.h:651
LPC_RTC_Type::GPREG2
__IOM uint32_t GPREG2
Definition LPC176x5x.h:640
LPC_RTC_Type::AYRS
__IOM uint32_t AYRS
Definition LPC176x5x.h:652
LPC_RTC_Type::RESERVED
__IM uint32_t RESERVED
Definition LPC176x5x.h:622
LPC_RTC_Type::CCR
__IOM uint32_t CCR
Definition LPC176x5x.h:623
LPC_RTC_Type::CTIME0
__IM uint32_t CTIME0
Definition LPC176x5x.h:626
LPC_RTC_Type::AMIN
__IOM uint32_t AMIN
Definition LPC176x5x.h:646
LPC_RTC_Type::CIIR
__IOM uint32_t CIIR
Definition LPC176x5x.h:624
LPC_RTC_Type::GPREG1
__IOM uint32_t GPREG1
Definition LPC176x5x.h:639
LPC_RTC_Type::DOM
__IOM uint32_t DOM
Definition LPC176x5x.h:632
LPC_RTC_Type::YEAR
__IOM uint32_t YEAR
Definition LPC176x5x.h:636
LPC_RTC_Type::HRS
__IOM uint32_t HRS
Definition LPC176x5x.h:631
LPC_RTC_Type::ADOM
__IOM uint32_t ADOM
Definition LPC176x5x.h:648
LPC_RTC_Type::DOW
__IOM uint32_t DOW
Definition LPC176x5x.h:633
LPC_RTC_Type::AMR
__IOM uint32_t AMR
Definition LPC176x5x.h:625
LPC_RTC_Type::RTC_AUX
__IOM uint32_t RTC_AUX
Definition LPC176x5x.h:644
LPC_RTC_Type::GPREG0
__IOM uint32_t GPREG0
Definition LPC176x5x.h:638
LPC_RTC_Type::ADOW
__IOM uint32_t ADOW
Definition LPC176x5x.h:649
LPC_RTC_Type::AHRS
__IOM uint32_t AHRS
Definition LPC176x5x.h:647
LPC_RTC_Type::CTIME1
__IM uint32_t CTIME1
Definition LPC176x5x.h:627
LPC_RTC_Type::GPREG4
__IOM uint32_t GPREG4
Definition LPC176x5x.h:642
LPC_RTC_Type::DOY
__IOM uint32_t DOY
Definition LPC176x5x.h:634
LPC_RTC_Type::ASEC
__IOM uint32_t ASEC
Definition LPC176x5x.h:645
LPC_RTC_Type::ILR
__IOM uint32_t ILR
Definition LPC176x5x.h:621
LPC_RTC_Type::GPREG3
__IOM uint32_t GPREG3
Definition LPC176x5x.h:641
LPC_RTC_Type::CALIBRATION
__IOM uint32_t CALIBRATION
Definition LPC176x5x.h:637
LPC_RTC_Type::SEC
__IOM uint32_t SEC
Definition LPC176x5x.h:629
LPC_RTC_Type::RTC_AUXEN
__IOM uint32_t RTC_AUXEN
Definition LPC176x5x.h:643
LPC_SPI_Type
SPI (SPI)
Definition LPC176x5x.h:592
LPC_SPI_Type::SR
__IM uint32_t SR
Definition LPC176x5x.h:595
LPC_SPI_Type::INT
__IOM uint32_t INT
Definition LPC176x5x.h:605
LPC_SPI_Type::CCR
__IOM uint32_t CCR
Definition LPC176x5x.h:602
LPC_SPI_Type::DR
__IOM uint32_t DR
Definition LPC176x5x.h:597
LPC_SPI_Type::CR
__IOM uint32_t CR
Definition LPC176x5x.h:593
LPC_SSP0_Type
SSP controller (SSP0)
Definition LPC176x5x.h:953
LPC_SSP0_Type::IMSC
__IOM uint32_t IMSC
Definition LPC176x5x.h:962
LPC_SSP0_Type::DR
__IOM uint32_t DR
Definition LPC176x5x.h:958
LPC_SSP0_Type::CPSR
__IOM uint32_t CPSR
Definition LPC176x5x.h:961
LPC_SSP0_Type::MIS
__IM uint32_t MIS
Definition LPC176x5x.h:964
LPC_SSP0_Type::RIS
__IM uint32_t RIS
Definition LPC176x5x.h:963
LPC_SSP0_Type::CR1
__IOM uint32_t CR1
Definition LPC176x5x.h:956
LPC_SSP0_Type::SR
__IM uint32_t SR
Definition LPC176x5x.h:960
LPC_SSP0_Type::ICR
__OM uint32_t ICR
Definition LPC176x5x.h:965
LPC_SSP0_Type::CR0
__IOM uint32_t CR0
Definition LPC176x5x.h:954
LPC_SSP0_Type::DMACR
__IOM uint32_t DMACR
Definition LPC176x5x.h:966
LPC_SSP1_Type
SSP1 controller (SSP1)
Definition LPC176x5x.h:740
LPC_SSP1_Type::RIS
__IM uint32_t RIS
Definition LPC176x5x.h:750
LPC_SSP1_Type::ICR
__OM uint32_t ICR
Definition LPC176x5x.h:752
LPC_SSP1_Type::CR1
__IOM uint32_t CR1
Definition LPC176x5x.h:743
LPC_SSP1_Type::IMSC
__IOM uint32_t IMSC
Definition LPC176x5x.h:749
LPC_SSP1_Type::DMACR
__IOM uint32_t DMACR
Definition LPC176x5x.h:753
LPC_SSP1_Type::CPSR
__IOM uint32_t CPSR
Definition LPC176x5x.h:748
LPC_SSP1_Type::SR
__IM uint32_t SR
Definition LPC176x5x.h:747
LPC_SSP1_Type::DR
__IOM uint32_t DR
Definition LPC176x5x.h:745
LPC_SSP1_Type::MIS
__IM uint32_t MIS
Definition LPC176x5x.h:751
LPC_SSP1_Type::CR0
__IOM uint32_t CR0
Definition LPC176x5x.h:741
LPC_SYSCON_Type
System and clock control (SYSCON)
Definition LPC176x5x.h:1385
LPC_SYSCON_Type::PCONP
__IOM uint32_t PCONP
Definition LPC176x5x.h:1400
LPC_SYSCON_Type::PLL1STAT
__IM uint32_t PLL1STAT
Definition LPC176x5x.h:1396
LPC_SYSCON_Type::PCLKSEL0
__IOM uint32_t PCLKSEL0
Definition LPC176x5x.h:1418
LPC_SYSCON_Type::PCON
__IOM uint32_t PCON
Definition LPC176x5x.h:1399
LPC_SYSCON_Type::PLL1CON
__IOM uint32_t PLL1CON
Definition LPC176x5x.h:1394
LPC_SYSCON_Type::RSID
__IOM uint32_t RSID
Definition LPC176x5x.h:1414
LPC_SYSCON_Type::PLL0STAT
__IM uint32_t PLL0STAT
Definition LPC176x5x.h:1391
LPC_SYSCON_Type::RESERVED8
__IM uint32_t RESERVED8
Definition LPC176x5x.h:1417
LPC_SYSCON_Type::USBINTST
__IOM uint32_t USBINTST
Definition LPC176x5x.h:1421
LPC_SYSCON_Type::SCS
__IOM uint32_t SCS
Definition LPC176x5x.h:1416
LPC_SYSCON_Type::PLL1FEED
__OM uint32_t PLL1FEED
Definition LPC176x5x.h:1397
LPC_SYSCON_Type::USBCLKCFG
__IOM uint32_t USBCLKCFG
Definition LPC176x5x.h:1403
LPC_SYSCON_Type::EXTMODE
__IOM uint32_t EXTMODE
Definition LPC176x5x.h:1411
LPC_SYSCON_Type::PLL0FEED
__OM uint32_t PLL0FEED
Definition LPC176x5x.h:1392
LPC_SYSCON_Type::EXTINT
__IOM uint32_t EXTINT
Definition LPC176x5x.h:1409
LPC_SYSCON_Type::PCLKSEL1
__IOM uint32_t PCLKSEL1
Definition LPC176x5x.h:1419
LPC_SYSCON_Type::PLL0CFG
__IOM uint32_t PLL0CFG
Definition LPC176x5x.h:1390
LPC_SYSCON_Type::PLL1CFG
__IOM uint32_t PLL1CFG
Definition LPC176x5x.h:1395
LPC_SYSCON_Type::CANWAKEFLAGS
__IOM uint32_t CANWAKEFLAGS
Definition LPC176x5x.h:1407
LPC_SYSCON_Type::DMACREQSEL
__IOM uint32_t DMACREQSEL
Definition LPC176x5x.h:1422
LPC_SYSCON_Type::CCLKCFG
__IOM uint32_t CCLKCFG
Definition LPC176x5x.h:1402
LPC_SYSCON_Type::RESERVED5
__IM uint32_t RESERVED5
Definition LPC176x5x.h:1410
LPC_SYSCON_Type::FLASHCFG
__IOM uint32_t FLASHCFG
Definition LPC176x5x.h:1386
LPC_SYSCON_Type::CANSLEEPCLR
__IOM uint32_t CANSLEEPCLR
Definition LPC176x5x.h:1405
LPC_SYSCON_Type::CLKSRCSEL
__IOM uint32_t CLKSRCSEL
Definition LPC176x5x.h:1404
LPC_SYSCON_Type::EXTPOLAR
__IOM uint32_t EXTPOLAR
Definition LPC176x5x.h:1412
LPC_SYSCON_Type::CLKOUTCFG
__IOM uint32_t CLKOUTCFG
Definition LPC176x5x.h:1424
LPC_SYSCON_Type::PLL0CON
__IOM uint32_t PLL0CON
Definition LPC176x5x.h:1389
LPC_TIMER0_Type
Timer0/1/2/3 (TIMER0)
Definition LPC176x5x.h:210
LPC_TIMER0_Type::EMR
__IOM uint32_t EMR
Definition LPC176x5x.h:246
LPC_TIMER0_Type::CCR
__IOM uint32_t CCR
Definition LPC176x5x.h:237
LPC_TIMER0_Type::CTCR
__IOM uint32_t CTCR
Definition LPC176x5x.h:249
LPC_TIMER0_Type::PC
__IOM uint32_t PC
Definition LPC176x5x.h:224
LPC_TIMER0_Type::TCR
__IOM uint32_t TCR
Definition LPC176x5x.h:215
LPC_TIMER0_Type::TC
__IOM uint32_t TC
Definition LPC176x5x.h:218
LPC_TIMER0_Type::IR
__IOM uint32_t IR
Definition LPC176x5x.h:211
LPC_TIMER0_Type::PR
__IOM uint32_t PR
Definition LPC176x5x.h:221
LPC_TIMER0_Type::MCR
__IOM uint32_t MCR
Definition LPC176x5x.h:230
LPC_TIMER1_Type
Timer0/1/2/3 (TIMER1)
Definition LPC176x5x.h:265
LPC_TIMER1_Type::CCR
__IOM uint32_t CCR
Definition LPC176x5x.h:292
LPC_TIMER1_Type::TCR
__IOM uint32_t TCR
Definition LPC176x5x.h:270
LPC_TIMER1_Type::IR
__IOM uint32_t IR
Definition LPC176x5x.h:266
LPC_TIMER1_Type::MCR
__IOM uint32_t MCR
Definition LPC176x5x.h:285
LPC_TIMER1_Type::PR
__IOM uint32_t PR
Definition LPC176x5x.h:276
LPC_TIMER1_Type::EMR
__IOM uint32_t EMR
Definition LPC176x5x.h:301
LPC_TIMER1_Type::PC
__IOM uint32_t PC
Definition LPC176x5x.h:279
LPC_TIMER1_Type::CTCR
__IOM uint32_t CTCR
Definition LPC176x5x.h:304
LPC_TIMER1_Type::TC
__IOM uint32_t TC
Definition LPC176x5x.h:273
LPC_TIMER2_Type
Timer0/1/2/3 (TIMER2)
Definition LPC176x5x.h:1002
LPC_TIMER2_Type::PR
__IOM uint32_t PR
Definition LPC176x5x.h:1013
LPC_TIMER2_Type::CTCR
__IOM uint32_t CTCR
Definition LPC176x5x.h:1041
LPC_TIMER2_Type::IR
__IOM uint32_t IR
Definition LPC176x5x.h:1003
LPC_TIMER2_Type::EMR
__IOM uint32_t EMR
Definition LPC176x5x.h:1038
LPC_TIMER2_Type::PC
__IOM uint32_t PC
Definition LPC176x5x.h:1016
LPC_TIMER2_Type::CCR
__IOM uint32_t CCR
Definition LPC176x5x.h:1029
LPC_TIMER2_Type::TC
__IOM uint32_t TC
Definition LPC176x5x.h:1010
LPC_TIMER2_Type::MCR
__IOM uint32_t MCR
Definition LPC176x5x.h:1022
LPC_TIMER2_Type::TCR
__IOM uint32_t TCR
Definition LPC176x5x.h:1007
LPC_TIMER3_Type
Timer0/1/2/3 (TIMER3)
Definition LPC176x5x.h:1057
LPC_TIMER3_Type::TCR
__IOM uint32_t TCR
Definition LPC176x5x.h:1062
LPC_TIMER3_Type::PR
__IOM uint32_t PR
Definition LPC176x5x.h:1068
LPC_TIMER3_Type::MCR
__IOM uint32_t MCR
Definition LPC176x5x.h:1077
LPC_TIMER3_Type::CTCR
__IOM uint32_t CTCR
Definition LPC176x5x.h:1096
LPC_TIMER3_Type::TC
__IOM uint32_t TC
Definition LPC176x5x.h:1065
LPC_TIMER3_Type::IR
__IOM uint32_t IR
Definition LPC176x5x.h:1058
LPC_TIMER3_Type::EMR
__IOM uint32_t EMR
Definition LPC176x5x.h:1093
LPC_TIMER3_Type::CCR
__IOM uint32_t CCR
Definition LPC176x5x.h:1084
LPC_TIMER3_Type::PC
__IOM uint32_t PC
Definition LPC176x5x.h:1071
LPC_UART0_Type
UART0/2/3 (UART0)
Definition LPC176x5x.h:320
LPC_UART0_Type::IIR
__IM uint32_t IIR
Definition LPC176x5x.h:345
LPC_UART0_Type::RS485DLY
__IOM uint32_t RS485DLY
Definition LPC176x5x.h:372
LPC_UART0_Type::THR
__OM uint32_t THR
Definition LPC176x5x.h:325
LPC_UART0_Type::FDR
__IOM uint32_t FDR
Definition LPC176x5x.h:361
LPC_UART0_Type::TER
__IOM uint32_t TER
Definition LPC176x5x.h:364
LPC_UART0_Type::RESERVED3
__IM uint32_t RESERVED3
Definition LPC176x5x.h:363
LPC_UART0_Type::RESERVED
__IM uint32_t RESERVED
Definition LPC176x5x.h:352
LPC_UART0_Type::SCR
__IOM uint32_t SCR
Definition LPC176x5x.h:356
LPC_UART0_Type::ACR
__IOM uint32_t ACR
Definition LPC176x5x.h:358
LPC_UART0_Type::RBR
__IM uint32_t RBR
Definition LPC176x5x.h:323
LPC_UART0_Type::LSR
__IM uint32_t LSR
Definition LPC176x5x.h:353
LPC_UART0_Type::DLM
__IOM uint32_t DLM
Definition LPC176x5x.h:335
LPC_UART0_Type::DLL
__IOM uint32_t DLL
Definition LPC176x5x.h:328
LPC_UART0_Type::RESERVED1
__IM uint32_t RESERVED1
Definition LPC176x5x.h:355
LPC_UART0_Type::RS485ADRMATCH
__IOM uint32_t RS485ADRMATCH
Definition LPC176x5x.h:370
LPC_UART0_Type::LCR
__IOM uint32_t LCR
Definition LPC176x5x.h:350
LPC_UART0_Type::RESERVED2
__IM uint32_t RESERVED2
Definition LPC176x5x.h:360
LPC_UART0_Type::IER
__IOM uint32_t IER
Definition LPC176x5x.h:339
LPC_UART0_Type::FCR
__OM uint32_t FCR
Definition LPC176x5x.h:347
LPC_UART0_Type::RS485CTRL
__IOM uint32_t RS485CTRL
Definition LPC176x5x.h:367
LPC_UART1_Type
UART1 (UART1)
Definition LPC176x5x.h:386
LPC_UART1_Type::RESERVED1
__IM uint32_t RESERVED1
Definition LPC176x5x.h:430
LPC_UART1_Type::DLL
__IOM uint32_t DLL
Definition LPC176x5x.h:393
LPC_UART1_Type::RS485DLY
__IOM uint32_t RS485DLY
Definition LPC176x5x.h:439
LPC_UART1_Type::THR
__OM uint32_t THR
Definition LPC176x5x.h:391
LPC_UART1_Type::RS485ADRMATCH
__IOM uint32_t RS485ADRMATCH
Definition LPC176x5x.h:437
LPC_UART1_Type::RBR
__IM uint32_t RBR
Definition LPC176x5x.h:389
LPC_UART1_Type::DLM
__IOM uint32_t DLM
Definition LPC176x5x.h:400
LPC_UART1_Type::FCR
__OM uint32_t FCR
Definition LPC176x5x.h:412
LPC_UART1_Type::IER
__IOM uint32_t IER
Definition LPC176x5x.h:404
LPC_UART1_Type::MSR
__IM uint32_t MSR
Definition LPC176x5x.h:421
LPC_UART1_Type::RESERVED
__IM uint32_t RESERVED
Definition LPC176x5x.h:427
LPC_UART1_Type::IIR
__IM uint32_t IIR
Definition LPC176x5x.h:410
LPC_UART1_Type::RS485CTRL
__IOM uint32_t RS485CTRL
Definition LPC176x5x.h:434
LPC_UART1_Type::MCR
__IOM uint32_t MCR
Definition LPC176x5x.h:417
LPC_UART1_Type::LSR
__IM uint32_t LSR
Definition LPC176x5x.h:419
LPC_UART1_Type::TER
__IOM uint32_t TER
Definition LPC176x5x.h:431
LPC_UART1_Type::ACR
__IOM uint32_t ACR
Definition LPC176x5x.h:425
LPC_UART1_Type::LCR
__IOM uint32_t LCR
Definition LPC176x5x.h:415
LPC_UART1_Type::SCR
__IOM uint32_t SCR
Definition LPC176x5x.h:423
LPC_UART1_Type::FDR
__IOM uint32_t FDR
Definition LPC176x5x.h:428
LPC_UART2_Type
UART0/2/3 (UART2)
Definition LPC176x5x.h:1112
LPC_UART2_Type::FDR
__IOM uint32_t FDR
Definition LPC176x5x.h:1153
LPC_UART2_Type::LSR
__IM uint32_t LSR
Definition LPC176x5x.h:1145
LPC_UART2_Type::IIR
__IM uint32_t IIR
Definition LPC176x5x.h:1137
LPC_UART2_Type::LCR
__IOM uint32_t LCR
Definition LPC176x5x.h:1142
LPC_UART2_Type::RESERVED1
__IM uint32_t RESERVED1
Definition LPC176x5x.h:1147
LPC_UART2_Type::RS485ADRMATCH
__IOM uint32_t RS485ADRMATCH
Definition LPC176x5x.h:1162
LPC_UART2_Type::DLM
__IOM uint32_t DLM
Definition LPC176x5x.h:1127
LPC_UART2_Type::RBR
__IM uint32_t RBR
Definition LPC176x5x.h:1115
LPC_UART2_Type::THR
__OM uint32_t THR
Definition LPC176x5x.h:1117
LPC_UART2_Type::TER
__IOM uint32_t TER
Definition LPC176x5x.h:1156
LPC_UART2_Type::SCR
__IOM uint32_t SCR
Definition LPC176x5x.h:1148
LPC_UART2_Type::RESERVED2
__IM uint32_t RESERVED2
Definition LPC176x5x.h:1152
LPC_UART2_Type::DLL
__IOM uint32_t DLL
Definition LPC176x5x.h:1120
LPC_UART2_Type::IER
__IOM uint32_t IER
Definition LPC176x5x.h:1131
LPC_UART2_Type::RESERVED3
__IM uint32_t RESERVED3
Definition LPC176x5x.h:1155
LPC_UART2_Type::RS485CTRL
__IOM uint32_t RS485CTRL
Definition LPC176x5x.h:1159
LPC_UART2_Type::RS485DLY
__IOM uint32_t RS485DLY
Definition LPC176x5x.h:1164
LPC_UART2_Type::RESERVED
__IM uint32_t RESERVED
Definition LPC176x5x.h:1144
LPC_UART2_Type::FCR
__OM uint32_t FCR
Definition LPC176x5x.h:1139
LPC_UART2_Type::ACR
__IOM uint32_t ACR
Definition LPC176x5x.h:1150
LPC_UART3_Type
UART0/2/3 (UART3)
Definition LPC176x5x.h:1178
LPC_UART3_Type::RS485ADRMATCH
__IOM uint32_t RS485ADRMATCH
Definition LPC176x5x.h:1228
LPC_UART3_Type::RESERVED2
__IM uint32_t RESERVED2
Definition LPC176x5x.h:1218
LPC_UART3_Type::RBR
__IM uint32_t RBR
Definition LPC176x5x.h:1181
LPC_UART3_Type::RESERVED3
__IM uint32_t RESERVED3
Definition LPC176x5x.h:1221
LPC_UART3_Type::THR
__OM uint32_t THR
Definition LPC176x5x.h:1183
LPC_UART3_Type::FCR
__OM uint32_t FCR
Definition LPC176x5x.h:1205
LPC_UART3_Type::LSR
__IM uint32_t LSR
Definition LPC176x5x.h:1211
LPC_UART3_Type::FDR
__IOM uint32_t FDR
Definition LPC176x5x.h:1219
LPC_UART3_Type::TER
__IOM uint32_t TER
Definition LPC176x5x.h:1222
LPC_UART3_Type::ACR
__IOM uint32_t ACR
Definition LPC176x5x.h:1216
LPC_UART3_Type::RS485DLY
__IOM uint32_t RS485DLY
Definition LPC176x5x.h:1230
LPC_UART3_Type::RS485CTRL
__IOM uint32_t RS485CTRL
Definition LPC176x5x.h:1225
LPC_UART3_Type::SCR
__IOM uint32_t SCR
Definition LPC176x5x.h:1214
LPC_UART3_Type::DLM
__IOM uint32_t DLM
Definition LPC176x5x.h:1193
LPC_UART3_Type::LCR
__IOM uint32_t LCR
Definition LPC176x5x.h:1208
LPC_UART3_Type::DLL
__IOM uint32_t DLL
Definition LPC176x5x.h:1186
LPC_UART3_Type::IER
__IOM uint32_t IER
Definition LPC176x5x.h:1197
LPC_UART3_Type::RESERVED1
__IM uint32_t RESERVED1
Definition LPC176x5x.h:1213
LPC_UART3_Type::IIR
__IM uint32_t IIR
Definition LPC176x5x.h:1203
LPC_UART3_Type::RESERVED
__IM uint32_t RESERVED
Definition LPC176x5x.h:1210
LPC_USB_Type
USB device/host/OTG controller (USB)
Definition LPC176x5x.h:1580
LPC_USB_Type::OTGCLKCTRL
__IOM uint32_t OTGCLKCTRL
Definition LPC176x5x.h:1645
LPC_USB_Type::CTRL
__IOM uint32_t CTRL
Definition LPC176x5x.h:1601
LPC_USB_Type::EPINTST
__IM uint32_t EPINTST
Definition LPC176x5x.h:1603
LPC_USB_Type::DMARSET
__OM uint32_t DMARSET
Definition LPC176x5x.h:1613
LPC_USB_Type::DEVINTPRI
__OM uint32_t DEVINTPRI
Definition LPC176x5x.h:1602
LPC_USB_Type::I2C_RX
__IM uint32_t I2C_RX
Definition LPC176x5x.h:1634
LPC_USB_Type::NDDRINTSET
__OM uint32_t NDDRINTSET
Definition LPC176x5x.h:1627
LPC_USB_Type::EPINTPRI
__OM uint32_t EPINTPRI
Definition LPC176x5x.h:1607
LPC_USB_Type::INTSET
__OM uint32_t INTSET
Definition LPC176x5x.h:1586
LPC_USB_Type::SYSERRINTST
__IM uint32_t SYSERRINTST
Definition LPC176x5x.h:1628
LPC_USB_Type::DEVINTEN
__IOM uint32_t DEVINTEN
Definition LPC176x5x.h:1592
LPC_USB_Type::USBCLKCTRL
__IOM uint32_t USBCLKCTRL
Definition LPC176x5x.h:1644
LPC_USB_Type::TMR
__IOM uint32_t TMR
Definition LPC176x5x.h:1589
LPC_USB_Type::EPINTSET
__OM uint32_t EPINTSET
Definition LPC176x5x.h:1606
LPC_USB_Type::TXDATA
__OM uint32_t TXDATA
Definition LPC176x5x.h:1598
LPC_USB_Type::NDDRINTCLR
__OM uint32_t NDDRINTCLR
Definition LPC176x5x.h:1626
LPC_USB_Type::I2C_CLKLO
__OM uint32_t I2C_CLKLO
Definition LPC176x5x.h:1640
LPC_USB_Type::I2C_WO
__OM uint32_t I2C_WO
Definition LPC176x5x.h:1635
LPC_USB_Type::RXDATA
__IM uint32_t RXDATA
Definition LPC176x5x.h:1597
LPC_USB_Type::TXPLEN
__OM uint32_t TXPLEN
Definition LPC176x5x.h:1600
LPC_USB_Type::INTEN
__IOM uint32_t INTEN
Definition LPC176x5x.h:1585
LPC_USB_Type::EPINTCLR
__OM uint32_t EPINTCLR
Definition LPC176x5x.h:1605
LPC_USB_Type::EPDMADIS
__OM uint32_t EPDMADIS
Definition LPC176x5x.h:1618
LPC_USB_Type::DMAINTEN
__IOM uint32_t DMAINTEN
Definition LPC176x5x.h:1620
LPC_USB_Type::NDDRINTST
__IM uint32_t NDDRINTST
Definition LPC176x5x.h:1625
LPC_USB_Type::EPDMAST
__IM uint32_t EPDMAST
Definition LPC176x5x.h:1616
LPC_USB_Type::EPINTEN
__IOM uint32_t EPINTEN
Definition LPC176x5x.h:1604
LPC_USB_Type::EOTINTCLR
__OM uint32_t EOTINTCLR
Definition LPC176x5x.h:1623
LPC_USB_Type::DEVINTST
__IM uint32_t DEVINTST
Definition LPC176x5x.h:1591
LPC_USB_Type::DMARST
__IM uint32_t DMARST
Definition LPC176x5x.h:1611
LPC_USB_Type::EPIND
__OM uint32_t EPIND
Definition LPC176x5x.h:1609
LPC_USB_Type::I2C_CLKHI
__IOM uint32_t I2C_CLKHI
Definition LPC176x5x.h:1639
LPC_USB_Type::DEVINTCLR
__OM uint32_t DEVINTCLR
Definition LPC176x5x.h:1593
LPC_USB_Type::INTST
__IM uint32_t INTST
Definition LPC176x5x.h:1584
LPC_USB_Type::SYSERRINTCLR
__OM uint32_t SYSERRINTCLR
Definition LPC176x5x.h:1629
LPC_USB_Type::REEP
__IOM uint32_t REEP
Definition LPC176x5x.h:1608
LPC_USB_Type::DMARCLR
__OM uint32_t DMARCLR
Definition LPC176x5x.h:1612
LPC_USB_Type::RESERVED3
__IM uint32_t RESERVED3
Definition LPC176x5x.h:1599
LPC_USB_Type::I2C_STS
__IM uint32_t I2C_STS
Definition LPC176x5x.h:1637
LPC_USB_Type::EOTINTST
__IM uint32_t EOTINTST
Definition LPC176x5x.h:1622
LPC_USB_Type::USBCLKST
__IM uint32_t USBCLKST
Definition LPC176x5x.h:1649
LPC_USB_Type::EOTINTSET
__OM uint32_t EOTINTSET
Definition LPC176x5x.h:1624
LPC_USB_Type::DMAINTST
__IM uint32_t DMAINTST
Definition LPC176x5x.h:1619
LPC_USB_Type::MAXPSIZE
__IOM uint32_t MAXPSIZE
Definition LPC176x5x.h:1610
LPC_USB_Type::OTGCLKST
__IM uint32_t OTGCLKST
Definition LPC176x5x.h:1650
LPC_USB_Type::CMDCODE
__OM uint32_t CMDCODE
Definition LPC176x5x.h:1595
LPC_USB_Type::DEVINTSET
__OM uint32_t DEVINTSET
Definition LPC176x5x.h:1594
LPC_USB_Type::EPDMAEN
__OM uint32_t EPDMAEN
Definition LPC176x5x.h:1617
LPC_USB_Type::INTCLR
__OM uint32_t INTCLR
Definition LPC176x5x.h:1587
LPC_USB_Type::STCTRL
__IOM uint32_t STCTRL
Definition LPC176x5x.h:1588
LPC_USB_Type::SYSERRINTSET
__OM uint32_t SYSERRINTSET
Definition LPC176x5x.h:1630
LPC_USB_Type::UDCAH
__IOM uint32_t UDCAH
Definition LPC176x5x.h:1615
LPC_USB_Type::CMDDATA
__IM uint32_t CMDDATA
Definition LPC176x5x.h:1596
LPC_USB_Type::I2C_CTL
__IOM uint32_t I2C_CTL
Definition LPC176x5x.h:1638
LPC_USB_Type::RXPLEN
__IM uint32_t RXPLEN
Definition LPC176x5x.h:1582
LPC_WDT_Type
Watchdog Timer (WDT) (WDT)
Definition LPC176x5x.h:183
LPC_WDT_Type::TC
__IOM uint32_t TC
Definition LPC176x5x.h:187
LPC_WDT_Type::TV
__IM uint32_t TV
Definition LPC176x5x.h:193
LPC_WDT_Type::MOD
__IOM uint32_t MOD
Definition LPC176x5x.h:184
LPC_WDT_Type::FEED
__OM uint32_t FEED
Definition LPC176x5x.h:189
LPC_WDT_Type::CLKSEL
__IOM uint32_t CLKSEL
Definition LPC176x5x.h:196