SSP controller (SSP0) More...

#include <LPC176x5x.h>

Data Fields
__IOM uint32_t	CR0

__IOM uint32_t	CR1

__IOM uint32_t	DR

__IM uint32_t	SR

__IOM uint32_t	CPSR

__IOM uint32_t	IMSC

__IM uint32_t	RIS

__IM uint32_t	MIS

__OM uint32_t	ICR

__IOM uint32_t	DMACR

Detailed Description

SSP controller (SSP0)

Field Documentation

◆ CPSR

__IOM uint32_t LPC_SSP0_Type::CPSR

(@ 0x00000010) Clock Prescale Register

◆ CR0

__IOM uint32_t LPC_SSP0_Type::CR0

< (@ 0x40088000) SSP0 Structure
(@ 0x00000000) Control Register 0. Selects the serial clock rate, bus type, and data size.

◆ CR1

__IOM uint32_t LPC_SSP0_Type::CR1

(@ 0x00000004) Control Register 1. Selects master/slave and other modes.

◆ DMACR

__IOM uint32_t LPC_SSP0_Type::DMACR

(@ 0x00000024) SSP0 DMA control register

◆ DR

__IOM uint32_t LPC_SSP0_Type::DR

(@ 0x00000008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.

◆ ICR

__OM uint32_t LPC_SSP0_Type::ICR

(@ 0x00000020) SSPICR Interrupt Clear Register

◆ IMSC

__IOM uint32_t LPC_SSP0_Type::IMSC

(@ 0x00000014) Interrupt Mask Set and Clear Register

◆ MIS

__IM uint32_t LPC_SSP0_Type::MIS

(@ 0x0000001C) Masked Interrupt Status Register

◆ RIS

__IM uint32_t LPC_SSP0_Type::RIS

(@ 0x00000018) Raw Interrupt Status Register

◆ SR

__IM uint32_t LPC_SSP0_Type::SR

(@ 0x0000000C) Status Register

The documentation for this struct was generated from the following file:

port/ucontroller/nxp/lpc17xx/bootloader/inc/LPC176x5x.h

Data Fields