LPC_UART1_Type Struct Reference

UART1 (UART1) More...

#include <LPC176x5x.h>

Data Fields
union {
__IM uint32_t   RBR
__OM uint32_t   THR
__IOM uint32_t   DLL
};
union {
__IOM uint32_t   DLM
__IOM uint32_t   IER
};
union {
__IM uint32_t   IIR
__OM uint32_t   FCR
};
__IOM uint32_t	LCR
__IOM uint32_t	MCR
__IM uint32_t	LSR
__IM uint32_t	MSR
__IOM uint32_t	SCR
__IOM uint32_t	ACR
__IM uint32_t	RESERVED
__IOM uint32_t	FDR
__IM uint32_t	RESERVED1
__IOM uint32_t	TER
__IM uint32_t	RESERVED2 [6]
__IOM uint32_t	RS485CTRL
__IOM uint32_t	RS485ADRMATCH
__IOM uint32_t	RS485DLY

Detailed Description

UART1 (UART1)

Field Documentation

[union]

union { ... } LPC_UART1_Type

< (@ 0x40010000) UART1 Structure

[union]

union { ... } LPC_UART1_Type

[union]

union { ... } LPC_UART1_Type

ACR

__IOM uint32_t LPC_UART1_Type::ACR

(@ 0x00000020) Auto-baud Control Register. Contains controls for the auto-baud feature.

DLL

__IOM uint32_t LPC_UART1_Type::DLL

(@ 0x00000000) DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.

DLM

__IOM uint32_t LPC_UART1_Type::DLM

(@ 0x00000004) DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.

FCR

__OM uint32_t LPC_UART1_Type::FCR

(@ 0x00000008) FIFO Control Register. Controls UART1 FIFO usage and modes.

FDR

__IOM uint32_t LPC_UART1_Type::FDR

(@ 0x00000028) Fractional Divider Register. Generates a clock input for the baud rate divider.

IER

__IOM uint32_t LPC_UART1_Type::IER

(@ 0x00000004) DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.

IIR

__IM uint32_t LPC_UART1_Type::IIR

(@ 0x00000008) Interrupt ID Register. Identifies which interrupt(s) are pending.

LCR

__IOM uint32_t LPC_UART1_Type::LCR

(@ 0x0000000C) Line Control Register. Contains controls for frame formatting and break generation.

LSR

__IM uint32_t LPC_UART1_Type::LSR

(@ 0x00000014) Line Status Register. Contains flags for transmit and receive status, including line errors.

MCR

__IOM uint32_t LPC_UART1_Type::MCR

(@ 0x00000010) Modem Control Register. Contains controls for flow control handshaking and loopback mode.

MSR

__IM uint32_t LPC_UART1_Type::MSR

(@ 0x00000018) Modem Status Register. Contains handshake signal status flags.

RBR

__IM uint32_t LPC_UART1_Type::RBR

(@ 0x00000000) DLAB =0 Receiver Buffer Register. Contains the next received character to be read.

RESERVED

__IM uint32_t LPC_UART1_Type::RESERVED

RESERVED1

__IM uint32_t LPC_UART1_Type::RESERVED1

RESERVED2

__IM uint32_t LPC_UART1_Type::RESERVED2[6]

RS485ADRMATCH

__IOM uint32_t LPC_UART1_Type::RS485ADRMATCH

(@ 0x00000050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.

RS485CTRL

__IOM uint32_t LPC_UART1_Type::RS485CTRL

(@ 0x0000004C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.

RS485DLY

__IOM uint32_t LPC_UART1_Type::RS485DLY

(@ 0x00000054) RS-485/EIA-485 direction control delay.

SCR

__IOM uint32_t LPC_UART1_Type::SCR

(@ 0x0000001C) Scratch Pad Register. 8-bit temporary storage for software.

TER

__IOM uint32_t LPC_UART1_Type::TER

(@ 0x00000030) Transmit Enable Register. Turns off UART transmitter for use with software flow control.

THR

__OM uint32_t LPC_UART1_Type::THR

(@ 0x00000000) DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.

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The documentation for this struct was generated from the following file:

• port/ucontroller/nxp/lpc17xx/bootloader/inc/LPC176x5x.h