I2C bus interface (I2C0) More...

#include <LPC176x5x.h>

Data Fields
__IOM uint32_t	CONSET

__IM uint32_t	STAT

__IOM uint32_t	DAT

__IOM uint32_t	ADR0

__IOM uint32_t	SCLH

__IOM uint32_t	SCLL

__OM uint32_t	CONCLR

__IOM uint32_t	MMCTRL

__IOM uint32_t	ADR1

__IOM uint32_t	ADR2

__IOM uint32_t	ADR3

__IM uint32_t	DATA_BUFFER

__IOM uint32_t	MASK [4]

Detailed Description

I2C bus interface (I2C0)

Field Documentation

◆ ADR0

__IOM uint32_t LPC_I2C0_Type::ADR0

(@ 0x0000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

◆ ADR1

__IOM uint32_t LPC_I2C0_Type::ADR1

(@ 0x00000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

◆ ADR2

__IOM uint32_t LPC_I2C0_Type::ADR2

(@ 0x00000024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

◆ ADR3

__IOM uint32_t LPC_I2C0_Type::ADR3

(@ 0x00000028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

◆ CONCLR

__OM uint32_t LPC_I2C0_Type::CONCLR

(@ 0x00000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.

◆ CONSET

__IOM uint32_t LPC_I2C0_Type::CONSET

< (@ 0x4001C000) I2C0 Structure
(@ 0x00000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.

◆ DAT

__IOM uint32_t LPC_I2C0_Type::DAT

(@ 0x00000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.

◆ DATA_BUFFER

__IM uint32_t LPC_I2C0_Type::DATA_BUFFER

(@ 0x0000002C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.

◆ MASK

__IOM uint32_t LPC_I2C0_Type::MASK[4]

(@ 0x00000030) I2C Slave address mask register

◆ MMCTRL

__IOM uint32_t LPC_I2C0_Type::MMCTRL

(@ 0x0000001C) Monitor mode control register.

◆ SCLH

__IOM uint32_t LPC_I2C0_Type::SCLH

(@ 0x00000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.

◆ SCLL

__IOM uint32_t LPC_I2C0_Type::SCLL

(@ 0x00000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.

◆ STAT

__IM uint32_t LPC_I2C0_Type::STAT

(@ 0x00000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.

The documentation for this struct was generated from the following file:

port/ucontroller/nxp/lpc17xx/bootloader/inc/LPC176x5x.h

Data Fields