LPC_TIMER0_Type Struct Reference

Timer0/1/2/3 (TIMER0) More...

#include <LPC176x5x.h>

Data Fields
__IOM uint32_t	IR
__IOM uint32_t	TCR
__IOM uint32_t	TC
__IOM uint32_t	PR
__IOM uint32_t	PC
__IOM uint32_t	MCR
__IOM uint32_t	MR [4]
__IOM uint32_t	CCR
__IM uint32_t	CR [2]
__IM uint32_t	RESERVED [2]
__IOM uint32_t	EMR
__IM uint32_t	RESERVED1 [12]
__IOM uint32_t	CTCR

Detailed Description

Timer0/1/2/3 (TIMER0)

Field Documentation

CCR

__IOM uint32_t LPC_TIMER0_Type::CCR

(@ 0x00000028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

CR

__IM uint32_t LPC_TIMER0_Type::CR[2]

(@ 0x0000002C) Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.

CTCR

__IOM uint32_t LPC_TIMER0_Type::CTCR

(@ 0x00000070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

EMR

__IOM uint32_t LPC_TIMER0_Type::EMR

(@ 0x0000003C) External Match Register. The EMR controls the external match pins.

IR

__IOM uint32_t LPC_TIMER0_Type::IR

< (@ 0x40004000) TIMER0 Structure
(@ 0x00000000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.

MCR

__IOM uint32_t LPC_TIMER0_Type::MCR

(@ 0x00000014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

MR

__IOM uint32_t LPC_TIMER0_Type::MR[4]

(@ 0x00000018) Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

PC

__IOM uint32_t LPC_TIMER0_Type::PC

(@ 0x00000010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

PR

__IOM uint32_t LPC_TIMER0_Type::PR

(@ 0x0000000C) Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.

RESERVED

__IM uint32_t LPC_TIMER0_Type::RESERVED[2]

RESERVED1

__IM uint32_t LPC_TIMER0_Type::RESERVED1[12]

TC

__IOM uint32_t LPC_TIMER0_Type::TC

(@ 0x00000008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.

TCR

__IOM uint32_t LPC_TIMER0_Type::TCR

(@ 0x00000004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

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The documentation for this struct was generated from the following file:

• port/ucontroller/nxp/lpc17xx/bootloader/inc/LPC176x5x.h