LPC_I2S_Type Struct Reference

I2S interface (I2S) More...

#include <LPC176x5x.h>

Data Fields
__IOM uint32_t	DAO
__IOM uint32_t	DAI
__OM uint32_t	TXFIFO
__IM uint32_t	RXFIFO
__IM uint32_t	STATE
__IOM uint32_t	DMA1
__IOM uint32_t	DMA2
__IOM uint32_t	IRQ
__IOM uint32_t	TXRATE
__IOM uint32_t	RXRATE
__IOM uint32_t	TXBITRATE
__IOM uint32_t	RXBITRATE
__IOM uint32_t	TXMODE
__IOM uint32_t	RXMODE

Detailed Description

I2S interface (I2S)

Field Documentation

DAI

__IOM uint32_t LPC_I2S_Type::DAI

(@ 0x00000004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.

DAO

__IOM uint32_t LPC_I2S_Type::DAO

< (@ 0x400A8000) I2S Structure
(@ 0x00000000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.

DMA1

__IOM uint32_t LPC_I2S_Type::DMA1

(@ 0x00000014) I2S DMA Configuration Register 1. Contains control information for DMA request 1.

DMA2

__IOM uint32_t LPC_I2S_Type::DMA2

(@ 0x00000018) I2S DMA Configuration Register 2. Contains control information for DMA request 2.

IRQ

__IOM uint32_t LPC_I2S_Type::IRQ

(@ 0x0000001C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.

RXBITRATE

__IOM uint32_t LPC_I2S_Type::RXBITRATE

(@ 0x0000002C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.

RXFIFO

__IM uint32_t LPC_I2S_Type::RXFIFO

(@ 0x0000000C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.

RXMODE

__IOM uint32_t LPC_I2S_Type::RXMODE

(@ 0x00000034) I2S Receive mode control.

RXRATE

__IOM uint32_t LPC_I2S_Type::RXRATE

(@ 0x00000024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.

STATE

__IM uint32_t LPC_I2S_Type::STATE

(@ 0x00000010) I2S Status Feedback Register. Contains status information about the I2S interface.

TXBITRATE

__IOM uint32_t LPC_I2S_Type::TXBITRATE

(@ 0x00000028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.

TXFIFO

__OM uint32_t LPC_I2S_Type::TXFIFO

(@ 0x00000008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.

TXMODE

__IOM uint32_t LPC_I2S_Type::TXMODE

(@ 0x00000030) I2S Transmit mode control.

TXRATE

__IOM uint32_t LPC_I2S_Type::TXRATE

(@ 0x00000020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.

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The documentation for this struct was generated from the following file:

• port/ucontroller/nxp/lpc17xx/bootloader/inc/LPC176x5x.h